From nobody Mon Feb 9 19:31:36 2026 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E5B02356C0; Fri, 21 Mar 2025 19:14:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742584455; cv=none; b=Jsp49SP/dYia5b8B/Hx7nFRxzh6gR+kfX/M2S0ZL9CdSm2aKwRGeY6QdEEMX6HiDo+c2MXpRxDdTDT4APhf3z3jLj1+rPlZltFbeXIrJAw2ScttskXZ94jSxluFRC4up4+T2P3984W99F1tzhb79DyzrVQOCPUgmhniQSKEvPjA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742584455; c=relaxed/simple; bh=VVpNTvIDfiVUf7OueLrc5Deb8r8QmakhhKkgdFLArYA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TGurfM2mzvw6q0L3qjVFaFBjpH/PxKOUZqSE8IKkCVJiyiOnBf6foKknS/epwom7d8tzp+smKEOmeQTUNFFaYz3oxwxcBY5wg+Zg0Dw5v66k+hUm1EUvwOmMC/ezwQYKeOs6NxUOdK3c3patLyXMrYQCooUgCRzFMCct966NxFU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=eT4UXrfY; arc=none smtp.client-ip=217.70.183.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="eT4UXrfY" Received: by mail.gandi.net (Postfix) with ESMTPSA id 5213044557; Fri, 21 Mar 2025 19:14:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1742584451; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=e87+RGdSOMXNWau7DVuhIt+zOGbm1RxUIpw5rMrMWvc=; b=eT4UXrfYvPWiZPi6pfaU4YnJdwis65lGwbBiCac2ZVwkmCObq6bnHXL5sjTzinqg2bFx9X OQkgqk2fV9+cRD1BMlSyodlgZG7l3r1kfxXtMLoP2F2SUplUQWcyZqLD/r5RNq0deV++JQ +bMGCXQKfZEP7EizxNFNUKQto46FnpXX9Il4z0L0JWujNiTMGSj/OuhAB6b+pBFPnBiFQd mN5H7GMTxFFQUuCzCPxSA2GGfPSY55SDty54IfSnftLCJILlpMJQ2lVXIaY23+CExx1hyv +uzPYvKHbNM35DK6Sa5/w53Oykt3t+5DfOEZ3vEEE/5uX5nLMUduCseRYdULcg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Fri, 21 Mar 2025 20:09:41 +0100 Subject: [PATCH net-next 10/13] net: macb: Add "mobileye,eyeq5-gem" compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250321-macb-v1-10-537b7e37971d@bootlin.com> References: <20250321-macb-v1-0-537b7e37971d@bootlin.com> In-Reply-To: <20250321-macb-v1-0-537b7e37971d@bootlin.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Samuel Holland , Richard Cochran , Russell King , Thomas Bogendoerfer , Vladimir Kondratiev , Gregory CLEMENT Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-mips@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeefvddrtddtgdduheduledtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuifetpfffkfdpucggtfgfnhhsuhgsshgtrhhisggvnecuuegrihhlohhuthemuceftddunecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhfffugggtgffkfhgjvfevofesthekredtredtjeenucfhrhhomhepvfhhrohoucfnvggsrhhunhcuoehthhgvohdrlhgvsghruhhnsegsohhothhlihhnrdgtohhmqeenucggtffrrghtthgvrhhnpeelvefhkeeufedvkefghefhgfdukeejlefgtdehtdeivddtteetgedvieelieeuhfenucfkphepjeejrddufeehrdekuddrieehnecuvehluhhsthgvrhfuihiivgepkeenucfrrghrrghmpehinhgvthepjeejrddufeehrdekuddrieehpdhhvghloheplgduledvrdduieekrddurdeftdgnpdhmrghilhhfrhhomhepthhhvghordhlvggsrhhunhessghoohhtlhhinhdrtghomhdpnhgspghrtghpthhtohepvdekpdhrtghpthhtohepghhrvghgohhrhidrtghlvghmvghnthessghoohhtlhhinhdrtghomhdprhgtphhtthhopehlihhnuhigqdhrihhstghvsehlihhsthhsrdhinhhfrhgruggvrggurdhorhhgpdhrtghpthhtohepphgruhhlrdifrghlmhhslhgvhiesshhifhhivhgvrdgtohhmpdhrtghpthhtohepthhssghoghgvnhgusegrlhhphhgrrdhfrhgrnhhkvghnrdguvgdprhgtphhtthhopehkuhgsrgesk hgvrhhnvghlrdhorhhgpdhrtghpthhtohepnhgvthguvghvsehvghgvrhdrkhgvrhhnvghlrdhorhhgpdhrtghpthhtohepnhhitgholhgrshdrfhgvrhhrvgesmhhitghrohgthhhiphdrtghomhdprhgtphhtthhopehthhhomhgrshdrphgvthgriiiiohhnihessghoohhtlhhinhdrtghomh X-GND-Sasl: theo.lebrun@bootlin.com Add support for the two GEM instances inside Mobileye EyeQ5 SoCs, using compatible "mobileye,eyeq5-gem". With it, add a custom init sequence that accesses two system-controller registers. Noteworthy: NET_IP_ALIGN=3D2 on MIPS but the hardware does not align and low bits aren't configurable, so we cannot respect the requested IP header alignment. Signed-off-by: Th=C3=A9o Lebrun --- drivers/net/ethernet/cadence/macb_main.c | 95 ++++++++++++++++++++++++++++= ++++ 1 file changed, 95 insertions(+) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/etherne= t/cadence/macb_main.c index 79161d559166478f85a6f8294d488ed961d9be7f..9f2a5bf9a5ebca5941229bd9609= 1a0fb96f0607d 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -34,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -4967,6 +4969,86 @@ static int init_reset_optional(struct platform_devic= e *pdev) return ret; } =20 +#define EYEQ5_OLB_GP_TX_SWRST_DIS BIT(0) // Tx SW reset +#define EYEQ5_OLB_GP_TX_M_CLKE BIT(1) // Tx M clock enable +#define EYEQ5_OLB_GP_SYS_SWRST_DIS BIT(2) // Sys SW reset +#define EYEQ5_OLB_GP_SYS_M_CLKE BIT(3) // Sys clock enable +#define EYEQ5_OLB_GP_SGMII_MODE BIT(4) // SGMII mode +#define EYEQ5_OLB_GP_RGMII_DRV GENMASK(8, 5) // RGMII mode +#define EYEQ5_OLB_GP_SMA_DRV GENMASK(12, 9) +#define EYEQ5_OLB_GP_RGMII_PD BIT(13) // RGMII pull-down +#define EYEQ5_OLB_GP_MDIO_PU BIT(14) // RGMII pull-up +#define EYEQ5_OLB_GP_RGMII_RX_ST BIT(15) // Schmitt trigger on RGMII Rx +#define EYEQ5_OLB_GP_RGMII_TX_ST BIT(16) // Schmitt trigger on RGMII Tx +#define EYEQ5_OLB_GP_MDIO_ST BIT(17) +#define EYEQ5_OLB_GP_MDC_ST BIT(18) +#define EYEQ5_OLB_GP_MBIST_ENABLE BIT(19) + +#define EYEQ5_OLB_SGMII_PWR_EN BIT(0) +#define EYEQ5_OLB_SGMII_RST_DIS BIT(1) +#define EYEQ5_OLB_SGMII_PLL_EN BIT(2) +#define EYEQ5_OLB_SGMII_SIG_DET_SW BIT(3) +#define EYEQ5_OLB_SGMII_PWR_STATE_MASK GENMASK(8, 4) +#define EYEQ5_OLB_SGMII_PWR_STATE BIT(4) +#define EYEQ5_OLB_SGMII_TX_ELECT_IDLE BIT(9) // Tx elect idle +#define EYEQ5_OLB_SGMII_POWER_ACK BIT(16) +#define EYEQ5_OLB_SGMII_PLL_ACK BIT(18) +#define EYEQ5_OLB_SGMII_SIG_DET BIT(19) +#define EYEQ5_OLB_SGMII_PWR_STATE_ACK GENMASK(24, 20) + +static int eyeq5_init(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct net_device *netdev =3D platform_get_drvdata(pdev); + struct macb *bp =3D netdev_priv(netdev); + struct device_node *np =3D dev->of_node; + unsigned int gp, sgmii; + struct regmap *regmap; + unsigned int args[2]; + unsigned int reg; + int ret; + + regmap =3D syscon_regmap_lookup_by_phandle_args(np, "mobileye,olb", 2, ar= gs); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + gp =3D args[0]; + sgmii =3D args[1]; + + /* Forced reset */ + regmap_write(regmap, gp, 0); + regmap_write(regmap, sgmii, 0); + usleep_range(5, 20); + + if (bp->phy_interface =3D=3D PHY_INTERFACE_MODE_SGMII) { + regmap_write(regmap, gp, EYEQ5_OLB_GP_SGMII_MODE); + + reg =3D EYEQ5_OLB_SGMII_PWR_EN | EYEQ5_OLB_SGMII_RST_DIS | + EYEQ5_OLB_SGMII_PLL_EN; + regmap_write(regmap, sgmii, reg); + + ret =3D regmap_read_poll_timeout(regmap, sgmii, reg, + reg & EYEQ5_OLB_SGMII_PLL_ACK, + 1, 100); + if (ret) + return dev_err_probe(dev, ret, "PLL timeout"); + + regmap_read(regmap, sgmii, ®); + reg |=3D EYEQ5_OLB_SGMII_PWR_STATE | EYEQ5_OLB_SGMII_SIG_DET_SW; + regmap_write(regmap, sgmii, reg); + } + + regmap_read(regmap, gp, ®); + reg &=3D ~EYEQ5_OLB_GP_RGMII_DRV; + if (phy_interface_mode_is_rgmii(bp->phy_interface)) + reg |=3D FIELD_PREP(EYEQ5_OLB_GP_RGMII_DRV, 0x9); + reg |=3D EYEQ5_OLB_GP_TX_SWRST_DIS | EYEQ5_OLB_GP_TX_M_CLKE; + reg |=3D EYEQ5_OLB_GP_SYS_SWRST_DIS | EYEQ5_OLB_GP_SYS_M_CLKE; + regmap_write(regmap, gp, reg); + + return macb_init(pdev); +} + static const struct macb_usrio_config sama7g5_usrio =3D { .mii =3D 0, .rmii =3D 1, @@ -5135,6 +5217,18 @@ static const struct macb_config versal_config =3D { .usrio =3D &macb_default_usrio, }; =20 +static const struct macb_config eyeq5_config =3D { + .caps =3D MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | + MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_QUEUE_DISABLE | + MACB_CAPS_NO_LSO, + .hw_ip_align =3D 0, + .dma_burst_length =3D 16, + .clk_init =3D macb_clk_init, + .init =3D eyeq5_init, + .jumbo_max_len =3D 10240, + .usrio =3D &macb_default_usrio, +}; + static const struct of_device_id macb_dt_ids[] =3D { { .compatible =3D "cdns,at91sam9260-macb", .data =3D &at91sam9260_config = }, { .compatible =3D "cdns,macb" }, @@ -5152,6 +5246,7 @@ static const struct of_device_id macb_dt_ids[] =3D { { .compatible =3D "cdns,zynqmp-gem", .data =3D &zynqmp_config}, /* deprec= ated */ { .compatible =3D "cdns,zynq-gem", .data =3D &zynq_config }, /* deprecate= d */ { .compatible =3D "sifive,fu540-c000-gem", .data =3D &fu540_c000_config }, + { .compatible =3D "mobileye,eyeq5-gem", .data =3D &eyeq5_config }, { .compatible =3D "microchip,mpfs-macb", .data =3D &mpfs_config }, { .compatible =3D "microchip,sama7g5-gem", .data =3D &sama7g5_gem_config = }, { .compatible =3D "microchip,sama7g5-emac", .data =3D &sama7g5_emac_confi= g }, --=20 2.48.1