From nobody Wed Dec 17 08:54:45 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C254D21C19E for ; Thu, 20 Mar 2025 23:43:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742514189; cv=none; b=UqACpMorZWeAecqv1xHbbFpozJgC8QKiQ6q2lscITzVVqYo3VRr423qa+3OrPmp7IXZw6uRQennjBaV5ZfqW5nrlcf7F+Htzw9cPMYk62LbwPaDECpDiNBDffquGJc72a6a0pQINCryxhZzlsWGIwjCJ/hkwbhGI7mikdkdsihI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742514189; c=relaxed/simple; bh=sX0VIggX6XGsEWj/HgxAlguQVIvI1fIdZXONOUBygNw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=L5t9A4dhA4V+ifdJiTdJBY2fSxdHqlq3/0QRrmOigCEhso91dIG4Z+VoVVn9ZNIm3lLFMvmymFGmJ6rweDr6pkSElnGXgtWFpJOoegruQOk/Cp38PCS9h7kSwO6qrIsOuODM4IJZf9glN35+zciUOqegv2CMLQObQ5hk+i9Jx4U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IhewwLaI; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IhewwLaI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742514187; x=1774050187; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sX0VIggX6XGsEWj/HgxAlguQVIvI1fIdZXONOUBygNw=; b=IhewwLaI/d7TuLM94jcsep997x7lX8nboLUs/I9kFuYPC6Wp6vUxumCn 76ElR3xMX169Q/2WWPUG3Gw3ZLy/oxWUNCd/vmkwOqAROTu6spYlAW4w7 MBOMcK2pExL8iYjxNG8AMGKdKmokDs1YB1IePkqtF9J68nIF75ThVeyv7 zipEyTB3TfVsw2XysKAxc6R0fmVpRZu4Aqxmwo0FXksrvFYdZjVtF5zDP CwULqSfyhzZO5yINck7Hb48hpwiB8QhhzOvC4wqW1C7QpsxV7/vNekGnQ EDzo+b3cwKtd0G7wgLlYeQH1HyMhWX6Ia4tuBskFCrt3o/kLJkXnLqsKl w==; X-CSE-ConnectionGUID: qaQXSvVcTcWEXhlOMzqFNg== X-CSE-MsgGUID: HNALlYvsT8aWUgT0boyq8A== X-IronPort-AV: E=McAfee;i="6700,10204,11379"; a="43502577" X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="43502577" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2025 16:43:07 -0700 X-CSE-ConnectionGUID: 2FunZjn+SZuRq67IiBE2Gw== X-CSE-MsgGUID: NF4S2XxLT8Cgkwp/9mBIvA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="122962933" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.161.68]) by orviesa009.jf.intel.com with ESMTP; 20 Mar 2025 16:43:07 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v2 1/9] x86/fpu/xstate: Remove xstate offset check Date: Thu, 20 Mar 2025 16:42:52 -0700 Message-ID: <20250320234301.8342-2-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250320234301.8342-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> <20250320234301.8342-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Traditionally, new xstate components have been assigned sequentially, aligning feature numbers with their offsets in the XSAVE buffer. However, this ordering is not architecturally mandated in the non-compacted format, where a component's offset may not correspond to its feature number. The kernel caches CPUID-reported xstate component details, including size and offset in the non-compacted format. As part of this process, a sanity check is also conducted to ensure alignment between feature numbers and offsets. This check was likely intended as a general guideline rather than a strict requirement. Upcoming changes will support out-of-order offsets. Remove the check as becoming obsolete. Signed-off-by: Chang S. Bae --- arch/x86/kernel/fpu/xstate.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 6a41d1610d8b..542c6981180d 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -216,9 +216,6 @@ static bool xfeature_enabled(enum xfeature xfeature) static void __init setup_xstate_cache(void) { u32 eax, ebx, ecx, edx, i; - /* start at the beginning of the "extended state" */ - unsigned int last_good_offset =3D offsetof(struct xregs_state, - extended_state_area); /* * The FP xstates and SSE xstates are legacy states. They are always * in the fixed offsets in the xsave area in either compacted form @@ -246,16 +243,6 @@ static void __init setup_xstate_cache(void) continue; =20 xstate_offsets[i] =3D ebx; - - /* - * In our xstate size checks, we assume that the highest-numbered - * xstate feature has the highest offset in the buffer. Ensure - * it does. - */ - WARN_ONCE(last_good_offset > xstate_offsets[i], - "x86/fpu: misordered xstate at %d\n", last_good_offset); - - last_good_offset =3D xstate_offsets[i]; } } =20 --=20 2.45.2 From nobody Wed Dec 17 08:54:45 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A74EA22B598 for ; Thu, 20 Mar 2025 23:43:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742514192; cv=none; b=qT6EcW8slzWMECCq0axUCVG43krQC79g1uxzXSOvxwjvjHdSOa+Isj5/8CwrzuWSZsWtaK2NMxUGNkNmVY3kdb+SSRLNzBHmsT3jSADlWaSdmCUuINvIJGIpon50zPrwWlwqeWKowRzx0AMA/02YIFJXsd/DwTv6ShPVWA8afxQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742514192; c=relaxed/simple; bh=xkbyojQodbOAEhETLU1zQWNpvzsyZ8UW18+79jCNagE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EG6qyWIO63M9h6YqyrH+SKGatU2XR9eoG+uwDi++F1PWn8CJNwhwpKSMO3+V2dCqf9CD7ax8Zx5eJxodZetK1AzGd/V6ctPOI/ZGuZlNue60RTAIRPX45UgLhnt4vROYp7ihCSFKRqgQST9bsEbfUM4rr3WvtyTy1dzkSQ8iOr0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gEOjxjxl; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gEOjxjxl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742514190; x=1774050190; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xkbyojQodbOAEhETLU1zQWNpvzsyZ8UW18+79jCNagE=; b=gEOjxjxl0QdRUfptJd4SRA1TlvD+yUNDlpY7EHykRpUEexnRTTdgrNkz z+IDvJMffn75AGmZNdfDEYgzoPDObNDMroxaYaAXzqNbWf2E7Pem7aIGy YJzt1NxbtI0DYjc55NNqgjw+y425uIc92QcOviO0V4ZXmqlSfkBICi6E+ EjCj4P17NyQHhs8LRmNBQ5PzhLRrSgmTQVplHTgZf90v/6fWvLhWq/9bi oOv1euFIoedTLsZvhYqox/LNyFP5Rz723HPN+fJ7PV4sOhitMHBJHi8+v HIi47WWSAGd2o1hxXTflF3gtD9j/gi9MUht/xaNQXF0MNZvklcGLYMtvA Q==; X-CSE-ConnectionGUID: 2Wr2/YabSxeTb0ZzGnSaSQ== X-CSE-MsgGUID: OOBV3DU2Qw6nzZM2KmWPtg== X-IronPort-AV: E=McAfee;i="6700,10204,11379"; a="43502583" X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="43502583" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2025 16:43:10 -0700 X-CSE-ConnectionGUID: NtbQglzHSuWh3zuFsxOgYw== X-CSE-MsgGUID: BVQRnDeoQVuDAoWxQKNHzg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="122962938" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.161.68]) by orviesa009.jf.intel.com with ESMTP; 20 Mar 2025 16:43:10 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v2 2/9] x86/fpu/xstate: Introduce xfeature order table and accessor macro Date: Thu, 20 Mar 2025 16:42:53 -0700 Message-ID: <20250320234301.8342-3-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250320234301.8342-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> <20250320234301.8342-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The kernel has largely assumed that higher xstate component numbers correspond to later offsets in the buffer. However, this assumption no longer holds for the non-compacted format, where a newer state component may have a lower offset. When iterating over xstate components in offset order, using the feature number as an index may be misleading. At the same time, the CPU exposes each component=E2=80=99s size and offset based on its feature number, makin= g it a key for state information. To provide flexibility in handling xstate ordering, introduce a mapping table: feature order -> feature number. The table is dynamically populated based on the CPU-exposed features and is sorted in offset order at boot time. Additionally, add an accessor macro to facilitate sequential traversal of xstate components based on their actual buffer positions, given a feature bitmask. This accessor macro will be particularly useful for computing custom non-compacted format sizes and iterating over xstate offsets in non-compacted buffers. Suggested-by: Dave Hansen Signed-off-by: Chang S. Bae Link: https://lore.kernel.org/all/7fa02be2-0884-4702-ae73-a3620938161b@inte= l.com --- RFC-V1 -> RFC-V2: Populate the order table dynamically (Dave). This introduction lays the groundwork for handling APX, which is assigned feature number 19 but appears immediately after FEATURE_YMM in APX-enabled systems. Older CPUs, such as Skylake systems, previously used this region for MPX. Later in this series, APX and MPX will be explicitly marked as mutually exclusive to prevent conflicts. Since the xfeature order table is dynamically populated at boot, it will reflect the correct feature set for each system configuration. --- arch/x86/kernel/fpu/xstate.c | 58 +++++++++++++++++++++++++++++++----- 1 file changed, 50 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 542c6981180d..1e22103a8e17 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -14,6 +14,7 @@ #include #include #include +#include =20 #include #include @@ -88,6 +89,31 @@ static unsigned int xstate_sizes[XFEATURE_MAX] __ro_afte= r_init =3D { [ 0 ... XFEATURE_MAX - 1] =3D -1}; static unsigned int xstate_flags[XFEATURE_MAX] __ro_after_init; =20 +/* + * Ordering of xstate components in uncompacted format: The xfeature + * number does not necessarily indicate its position in the XSAVE buffer. + * This array defines the traversal order of xstate features. + */ +static unsigned int xfeature_uncompact_order[XFEATURE_MAX] __ro_after_init= =3D + { [ 0 ... XFEATURE_MAX - 1] =3D -1}; + +static inline unsigned int next_xfeature_order(unsigned int i, u64 mask) +{ + for (; xfeature_uncompact_order[i] !=3D -1; i++) { + if (mask & BIT_ULL(xfeature_uncompact_order[i])) + break; + } + + return i; +} + +/* Iterate xstate features in uncompacted order: */ +#define for_each_extended_xfeature_in_order(i, mask) \ + for (i =3D 0; \ + i =3D next_xfeature_order(i, mask), \ + xfeature_uncompact_order[i] !=3D -1; \ + i++) + #define XSTATE_FLAG_SUPERVISOR BIT(0) #define XSTATE_FLAG_ALIGNED64 BIT(1) =20 @@ -209,13 +235,20 @@ static bool xfeature_enabled(enum xfeature xfeature) return fpu_kernel_cfg.max_features & BIT_ULL(xfeature); } =20 +static int compare_xstate_offsets(const void *xfeature1, const void *xfeat= ure2) +{ + return xstate_offsets[*(unsigned int *)xfeature1] - + xstate_offsets[*(unsigned int *)xfeature2]; +} + /* * Record the offsets and sizes of various xstates contained - * in the XSAVE state memory layout. + * in the XSAVE state memory layout. Also, create an ordered + * list of xfeatures for handling out-of-order offsets. */ static void __init setup_xstate_cache(void) { - u32 eax, ebx, ecx, edx, i; + u32 eax, ebx, ecx, edx, xfeature, i =3D 0; /* * The FP xstates and SSE xstates are legacy states. They are always * in the fixed offsets in the xsave area in either compacted form @@ -229,21 +262,30 @@ static void __init setup_xstate_cache(void) xstate_sizes[XFEATURE_SSE] =3D sizeof_field(struct fxregs_state, xmm_space); =20 - for_each_extended_xfeature(i, fpu_kernel_cfg.max_features) { - cpuid_count(CPUID_LEAF_XSTATE, i, &eax, &ebx, &ecx, &edx); + for_each_extended_xfeature(xfeature, fpu_kernel_cfg.max_features) { + cpuid_count(CPUID_LEAF_XSTATE, xfeature, &eax, &ebx, &ecx, &edx); =20 - xstate_sizes[i] =3D eax; - xstate_flags[i] =3D ecx; + xstate_sizes[xfeature] =3D eax; + xstate_flags[xfeature] =3D ecx; =20 /* * If an xfeature is supervisor state, the offset in EBX is * invalid, leave it to -1. */ - if (xfeature_is_supervisor(i)) + if (xfeature_is_supervisor(xfeature)) continue; =20 - xstate_offsets[i] =3D ebx; + xstate_offsets[xfeature] =3D ebx; + + /* Populate the list of xfeatures before sorting */ + xfeature_uncompact_order[i++] =3D xfeature; } + + /* + * Sort xfeatures by their offsets to support out-of-order + * offsets in the uncompacted format. + */ + sort(xfeature_uncompact_order, i, sizeof(unsigned int), compare_xstate_of= fsets, NULL); } =20 /* --=20 2.45.2 From nobody Wed Dec 17 08:54:45 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CC7222B8C6 for ; Thu, 20 Mar 2025 23:43:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742514194; cv=none; b=sBoB/AChTTqh0J73smODVR2myIDJljt8yDDtEI+/EueREn5m0bZuKYVzyHXQc0YDh0BRiPwCYlM1Lve34Vyab+rLzdyUriIHH5hGQrVQFw7+uBROcG55lG9Yb9/6r5TEum4j0/4wI/NFjGgykQi9E4xYnI2zj+bYGQ5DjASACyM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742514194; c=relaxed/simple; bh=vnXIpSLZTNEu4ZeR7wVUXuTusggA8dL6xryMPk7B+6g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M8PJBkiAkl9QdWmjfe71BamQKjNVhmDuKpnv3S9xEp/YvZk2qEJJ2s/gb+qmRrSFUYMV2PAGggKVaxvAuAuacS61wumkF8zU3FqU478WfgskkAf2Cf9w4u4EJcV/0zXs/yvSaoGyaDMQZzXgcNUg93RWP9OW1vO5xMK8GMuqL8I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lAHWac1Z; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lAHWac1Z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742514193; x=1774050193; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vnXIpSLZTNEu4ZeR7wVUXuTusggA8dL6xryMPk7B+6g=; b=lAHWac1ZeDqvWIyidkDWtfoSvoKqNkHujAxkXgVtJySbxrV4NWqToGHU lAbVPc62Rn1NBBkjAXyDtnk6d4zQkciu5d0l9jTkDSFRDB3YTv2iWWb2b v4Z6Pd4cI4INhjXFgSDOJ7pw69bc3ieBDfzWSRyipbAtigFl0sgCIYiYh 9gxsyTYEz2DgZJMNQLzVD+kJbcbGlQkwS7IrPWngk6p+pm3YG49qqp98Y rdCN/R5WoV35S9pnR0BIxJdT9WKYBZGd3cfOUeeb5OD5nRbmS5dDRZ7d7 7rf4FcuOFpLBkNDBp12EpxC1Rdk962XXLtAGA2gcDDR53HVZxRdHpn9Wb g==; X-CSE-ConnectionGUID: ualJM1aET4iFosSlSnw+Og== X-CSE-MsgGUID: rs44eFxvQEulNxSGNY40kg== X-IronPort-AV: E=McAfee;i="6700,10204,11379"; a="43502588" X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="43502588" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2025 16:43:13 -0700 X-CSE-ConnectionGUID: 3zyTXTI3TgiSK7151ezx5A== X-CSE-MsgGUID: HjvTWyfzTxWgh1xamkjY8g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="122962947" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.161.68]) by orviesa009.jf.intel.com with ESMTP; 20 Mar 2025 16:43:12 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v2 3/9] x86/fpu/xstate: Adjust XSAVE buffer size calculation Date: Thu, 20 Mar 2025 16:42:54 -0700 Message-ID: <20250320234301.8342-4-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250320234301.8342-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> <20250320234301.8342-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current xstate size calculation assumes that the highest-numbered xstate feature has the highest offset in the buffer, determining the size based on the topmost bit in the feature mask. However, this assumption is not architecturally guaranteed -- higher-numbered features may have lower offsets. With the introduction of the xfeature order table and its helper macro, xstate components can now be traversed in their positional order. Update the non-compacted format handling to iterate through the table to determine the last-positioned feature. Then, set the offset accordingly. Since size calculation primarily occurs during initialization or in non-critical paths, looping to find the last feature is not expected to have a meaningful performance impact. Signed-off-by: Chang S. Bae --- arch/x86/kernel/fpu/xstate.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 1e22103a8e17..93f94013b094 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -581,13 +581,20 @@ static bool __init check_xstate_against_struct(int nr) static unsigned int xstate_calculate_size(u64 xfeatures, bool compacted) { unsigned int topmost =3D fls64(xfeatures) - 1; - unsigned int offset =3D xstate_offsets[topmost]; + unsigned int offset, i; =20 if (topmost <=3D XFEATURE_SSE) return sizeof(struct xregs_state); =20 - if (compacted) + if (compacted) { offset =3D xfeature_get_offset(xfeatures, topmost); + } else { + /* Walk through the xfeature order to pick the last */ + for_each_extended_xfeature_in_order(i, xfeatures) + topmost =3D xfeature_uncompact_order[i]; + offset =3D xstate_offsets[topmost]; + } + return offset + xstate_sizes[topmost]; } =20 --=20 2.45.2 From nobody Wed Dec 17 08:54:45 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7BAD22CBE3 for ; Thu, 20 Mar 2025 23:43:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742514198; cv=none; b=SELgtHsv9+IZ3Liaj0YdwbsLKmqm7rMmhimZrMDHpILHbyHHzrn+HbOXpLTaYY0T4RRKBIzQNtjHeH7UagDJ6xaJVHL5unb7N4hGYsNjSNRwTC8gP+uaNwnhrKE/te6M+esp2ud9B+fQprejcag7lViNcV5yAxGQzdF1G7Xs4j8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742514198; c=relaxed/simple; bh=RNLRsZq30foUqdf9pTnNJcZQdOrD5Yha7VHSwhaeXc0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Uhr6vy4QTMJkZjpnFPa9Y3DbfHiPLYUfrcVMGceuWyCkOT4UTDJtSfSFW7ztrPIvv650EEYhVLo2/1xEt5j8+1W5P7mNOVSLVcSru9nStOUARO8UFAspJxvsRp9vHIi5ukiVqbyPzSgyrxg289bfJraCNw8bj+LbSqj0zf5GVBE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WnYBxdAu; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WnYBxdAu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742514195; x=1774050195; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RNLRsZq30foUqdf9pTnNJcZQdOrD5Yha7VHSwhaeXc0=; b=WnYBxdAuW++QO8gjk767/8lq8rrFBmGugwHByWI2NgGSunpmHGALDqdo W7YOAnSSxZfNBn0ArB827wG264pFDHg+tR3HiJWLfLLC8sJ74N8cUtICp uKJEWrKX0wwjbhBse1Jj9Q4N3Fvx46W66IMvman0STffKp43DHH29HjLy bWyPRsjdlwQqrFQMVHZa0OIN2TrB+Ix3h3gMRHNXcVI6a0j0j2pVYRQi2 4ODXBEQgO9AYJ9YzPqbHI1bwiB+ccafHfDC/jI39+Y12c0DK/wJZJ+lca eu2Gs6JiFASac75LLWqQKdTYFMP9ZIEWCzyXnnoJCbspn1el6MecyMLBx g==; X-CSE-ConnectionGUID: LxhBr/M/QCuQQtOsJR2uJw== X-CSE-MsgGUID: wwvzCw0QTGycwsI+N4zYxw== X-IronPort-AV: E=McAfee;i="6700,10204,11379"; a="43502593" X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="43502593" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2025 16:43:15 -0700 X-CSE-ConnectionGUID: gMya7LexS4eGmNY6RNvFww== X-CSE-MsgGUID: f5/jU1VNQeq5oJ08ibnqqg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="122962968" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.161.68]) by orviesa009.jf.intel.com with ESMTP; 20 Mar 2025 16:43:15 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v2 4/9] x86/fpu/xstate: Adjust xstate copying logic for user ABI Date: Thu, 20 Mar 2025 16:42:55 -0700 Message-ID: <20250320234301.8342-5-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250320234301.8342-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> <20250320234301.8342-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable =3D=3D Background =3D=3D As feature positions in the userspace XSAVE buffer do not always align with their feature numbers, the XSAVE format conversion needs to be reconsidered to align with the revised xstate size calculation logic. * For signal handling, XSAVE and XRSTOR are used directly to save and restore extended registers. * For ptrace, KVM, and signal returns (for 32-bit frame), the kernel copies data between its internal buffer and the userspace XSAVE buffer. If memcpy() were used for these cases, existing offset helpers =E2=80=94 = such as __raw_xsave_addr() or xstate_offsets[] =E2=80=94 would be sufficient to handle the format conversion. =3D=3D Problem =3D=3D When copying data from the compacted in-kernel buffer to the non-compacted userspace buffer, the function follows the user_regset_get2_fn() prototype. This means it utilizes struct membuf helpers for the destination buffer. As defined in regset.h, these helpers update the memory pointer during the copy process, enforcing sequential writes within the loop. Since xstate components are processed sequentially, any component whose buffer position does not align with its feature number has an issue. =3D=3D Solution =3D=3D Replace for_each_extended_xfeature() with the newly introduced for_each_extended_xfeature_in_order(). This macro ensures xstate components are handled in the correct order based on their actual positions in the destination buffer, rather than their feature numbers. Signed-off-by: Chang S. Bae --- arch/x86/kernel/fpu/xstate.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 93f94013b094..46c45e2f2a5a 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -1107,10 +1107,9 @@ void __copy_xstate_to_uabi_buf(struct membuf to, str= uct fpstate *fpstate, const unsigned int off_mxcsr =3D offsetof(struct fxregs_state, mxcsr); struct xregs_state *xinit =3D &init_fpstate.regs.xsave; struct xregs_state *xsave =3D &fpstate->regs.xsave; + unsigned int zerofrom, i, xfeature; struct xstate_header header; - unsigned int zerofrom; u64 mask; - int i; =20 memset(&header, 0, sizeof(header)); header.xfeatures =3D xsave->header.xfeatures; @@ -1179,15 +1178,16 @@ void __copy_xstate_to_uabi_buf(struct membuf to, st= ruct fpstate *fpstate, */ mask =3D header.xfeatures; =20 - for_each_extended_xfeature(i, mask) { + for_each_extended_xfeature_in_order(i, mask) { + xfeature =3D xfeature_uncompact_order[i]; /* * If there was a feature or alignment gap, zero the space * in the destination buffer. */ - if (zerofrom < xstate_offsets[i]) - membuf_zero(&to, xstate_offsets[i] - zerofrom); + if (zerofrom < xstate_offsets[xfeature]) + membuf_zero(&to, xstate_offsets[xfeature] - zerofrom); =20 - if (i =3D=3D XFEATURE_PKRU) { + if (xfeature =3D=3D XFEATURE_PKRU) { struct pkru_state pkru =3D {0}; /* * PKRU is not necessarily up to date in the @@ -1197,14 +1197,14 @@ void __copy_xstate_to_uabi_buf(struct membuf to, st= ruct fpstate *fpstate, membuf_write(&to, &pkru, sizeof(pkru)); } else { membuf_write(&to, - __raw_xsave_addr(xsave, i), - xstate_sizes[i]); + __raw_xsave_addr(xsave, xfeature), + xstate_sizes[xfeature]); } /* * Keep track of the last copied state in the non-compacted * target buffer for gap zeroing. */ - zerofrom =3D xstate_offsets[i] + xstate_sizes[i]; + zerofrom =3D xstate_offsets[xfeature] + xstate_sizes[xfeature]; } =20 out: --=20 2.45.2 From nobody Wed Dec 17 08:54:45 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6E4822A7FE for ; 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a="43502598" X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="43502598" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2025 16:43:18 -0700 X-CSE-ConnectionGUID: qniWYAk9SRqM6xSRIb3YaQ== X-CSE-MsgGUID: hnsvfRm/R3SCyRxNGZV6lw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="122962977" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.161.68]) by orviesa009.jf.intel.com with ESMTP; 20 Mar 2025 16:43:17 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v2 5/9] x86/cpufeatures: Add X86_FEATURE_APX Date: Thu, 20 Mar 2025 16:42:56 -0700 Message-ID: <20250320234301.8342-6-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250320234301.8342-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> <20250320234301.8342-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel Advanced Performance Extensions (APX) introduce a new set of general-purpose registers, managed as an extended state component via the xstate management facility. Before enabling this new xstate, define a feature flag to clarify the dependency in xsave_cpuid_features[]. APX is enumerated under CPUID level 7 with EDX=3D1. Since this CPUID leaf is not yet allocated, place the flag in a scattered feature word. While this feature is intended only for userspace, exposing it via /proc/cpuinfo is unnecessary. Instead, the existing arch_prctl(2) mechanism with the ARCH_GET_XCOMP_SUPP option can be used to query the feature availability. Finally, clarify that APX depends on XSAVE. Signed-off-by: Chang S. Bae --- Allocating a new feature word for this bit seems excessive at this stage, given that no other imminent features are quite known. --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 8b7cf13e0acb..51178d4a6308 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -479,6 +479,7 @@ #define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* Fast CPPC */ #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous C= ore Topology */ #define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32 + 7) /* Workload Classificat= ion */ +#define X86_FEATURE_APX (21*32 + 8) /* Advanced Performance Extensions */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index a2fbea0be535..d5e5013e0e9f 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -84,6 +84,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_AMX_TILE, X86_FEATURE_XFD }, { X86_FEATURE_SHSTK, X86_FEATURE_XSAVES }, { X86_FEATURE_FRED, X86_FEATURE_LKGS }, + { X86_FEATURE_APX, X86_FEATURE_XSAVE }, {} }; =20 diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 16f3ca30626a..6c40d5af8479 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -54,6 +54,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 }, { X86_FEATURE_AMD_HETEROGENEOUS_CORES, CPUID_EAX, 30, 0x80000026, 0 }, + { X86_FEATURE_APX, CPUID_EDX, 21, 0x00000007, 1 }, { 0, 0, 0, 0, 0 } }; =20 --=20 2.45.2 From nobody Wed Dec 17 08:54:45 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 022BD22D4FA for ; Thu, 20 Mar 2025 23:43:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742514203; cv=none; b=i1AhH8rv/TST7XfpdE2Pb6F93pzISVmcIEMvba6w/FdrXuD0JoqHpQ2X+w5lLpySWsQVUSPmd795CNrug+qDIsfxvT0Zmfa6cDazG0wUj89aC7m7M6raF81n0zTiwBAi3VEV8oPmvwQ0zykdOtKCEb1ft70aUj8VQ8DxxyeBKvI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742514203; c=relaxed/simple; bh=lNp44l3ZlB7sSDByBomNZ9z1owRfT9a0f56wu7y0YKY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cTsRH9lrbGho1YCMjS3pWHiaKJiXtsdRaJBS7q49+twp0JaymJ/HEXVzdxcb9saUgMwhL3xkHzx+8SRUOEEmAHFxW7rEjq7tXtAtm/8Lr430az0s1mqoL4SbRdB2sZ71j1uwPjOUzCrIpNwLRgHdV7V6JBY1/w5Zm5y7Lm9WYj4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=AgYPeVG+; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="AgYPeVG+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742514202; x=1774050202; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lNp44l3ZlB7sSDByBomNZ9z1owRfT9a0f56wu7y0YKY=; b=AgYPeVG+5fbWgXofmMLniwLH9WeFRZyF2lAgqIbf8GVfH65mD751Xk54 K+l4EIPN35n4kD1Ruayd7dIXgT8vKF4DxTEi6Ed2CKJykC+HXpskNxj+i wjqrO/H7Qu1n4TfvV4D1cLx6Ca1s2atVjkQuzIPZarcgr6mzET6jeG0kn Qf+FdkC9AKQ+BZiGYYKACBiGitQY7BiDUgBOj5ZituYuKWQv3Q6tU65Ps YsuJh8Mu4Vq1EN4ZAoMt0jjFWR79wFV0r4v2y9v+Y1qrlZ2l6wmWbeced 8IcT4f8Zczz11zTFgH0cpO6yrTnMb/Bew14QUetvH3bd/P1tDKDLLm5Ut w==; X-CSE-ConnectionGUID: qub5apymSpW2DgBLGZLQCg== X-CSE-MsgGUID: XXNeMvumTI2C4w2+oPHEtg== X-IronPort-AV: E=McAfee;i="6700,10204,11379"; a="43502604" X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="43502604" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2025 16:43:21 -0700 X-CSE-ConnectionGUID: FHVKe0erRWW625wtIt7iMw== X-CSE-MsgGUID: V0Kh+QO9ReKaGhqe2P8MZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="122962987" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.161.68]) by orviesa009.jf.intel.com with ESMTP; 20 Mar 2025 16:43:20 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v2 6/9] x86/fpu/apx: Define APX state component Date: Thu, 20 Mar 2025 16:42:57 -0700 Message-ID: <20250320234301.8342-7-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250320234301.8342-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> <20250320234301.8342-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Advanced Performance Extensions (APX) feature flag was previously defined. This feature is associated with a new state component number 19. To support APX, it is essential to define this xstate component and implement the necessary sanity checks. Define the new component number, state name, and those register data type. Then, extend the size checker to validate the register data type and explicitly set the APX feature flag as a dependency for the new component in xsave_cpuid_features[]. Signed-off-by: Chang S. Bae Reviewed-by: Sohil Mehta --- RFC-V1 -> RFC-V2: * Remove the ordering table change, as it is now dynamically populated. --- arch/x86/include/asm/fpu/types.h | 9 +++++++++ arch/x86/kernel/fpu/xstate.c | 3 +++ 2 files changed, 12 insertions(+) diff --git a/arch/x86/include/asm/fpu/types.h b/arch/x86/include/asm/fpu/ty= pes.h index de16862bf230..97310df3ea13 100644 --- a/arch/x86/include/asm/fpu/types.h +++ b/arch/x86/include/asm/fpu/types.h @@ -125,6 +125,7 @@ enum xfeature { XFEATURE_RSRVD_COMP_16, XFEATURE_XTILE_CFG, XFEATURE_XTILE_DATA, + XFEATURE_APX, =20 XFEATURE_MAX, }; @@ -145,6 +146,7 @@ enum xfeature { #define XFEATURE_MASK_LBR (1 << XFEATURE_LBR) #define XFEATURE_MASK_XTILE_CFG (1 << XFEATURE_XTILE_CFG) #define XFEATURE_MASK_XTILE_DATA (1 << XFEATURE_XTILE_DATA) +#define XFEATURE_MASK_APX (1 << XFEATURE_APX) =20 #define XFEATURE_MASK_FPSSE (XFEATURE_MASK_FP | XFEATURE_MASK_SSE) #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK \ @@ -303,6 +305,13 @@ struct xtile_data { struct reg_1024_byte tmm; } __packed; =20 +/* + * State component 19: 8B extended general purpose register. + */ +struct apx_state { + u64 egpr[16]; +} __packed; + /* * State component 10 is supervisor state used for context-switching the * PASID state. diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 46c45e2f2a5a..2a270683a762 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -63,6 +63,7 @@ static const char *xfeature_names[] =3D "unknown xstate feature", "AMX Tile config", "AMX Tile data", + "APX registers", "unknown xstate feature", }; =20 @@ -81,6 +82,7 @@ static unsigned short xsave_cpuid_features[] __initdata = =3D { [XFEATURE_CET_USER] =3D X86_FEATURE_SHSTK, [XFEATURE_XTILE_CFG] =3D X86_FEATURE_AMX_TILE, [XFEATURE_XTILE_DATA] =3D X86_FEATURE_AMX_TILE, + [XFEATURE_APX] =3D X86_FEATURE_APX, }; =20 static unsigned int xstate_offsets[XFEATURE_MAX] __ro_after_init =3D @@ -570,6 +572,7 @@ static bool __init check_xstate_against_struct(int nr) case XFEATURE_XTILE_CFG: return XCHECK_SZ(sz, nr, struct xtile_cfg); case XFEATURE_CET_USER: return XCHECK_SZ(sz, nr, struct cet_user_state); case XFEATURE_XTILE_DATA: check_xtile_data_against_struct(sz); return tru= e; + case XFEATURE_APX: return XCHECK_SZ(sz, nr, struct apx_state); default: XSTATE_WARN_ON(1, "No structure for xstate: %d\n", nr); return false; --=20 2.45.2 From nobody Wed Dec 17 08:54:45 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6C0F22D786 for ; Thu, 20 Mar 2025 23:43:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742514206; cv=none; b=sskYeK1zBie2/OKAVUyDwwB60MZc9kuQmyuzd4hso9dPdJQt9AzlgYD8aiAVcnT+oOQ4x37U0U95vCpNF9GZtOVHz6lBPtcfr3W21xhhj4TBLxv17WqHTj1SsDtmFtUhhP6VYjHkvpfFPDejsKRSa0VjIW2yrHzxaO47b43YD0s= ARC-Message-Signature: i=1; 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d="scan'208";a="122962991" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.161.68]) by orviesa009.jf.intel.com with ESMTP; 20 Mar 2025 16:43:23 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v2 7/9] x86/fpu/apx: Disallow conflicting MPX presence Date: Thu, 20 Mar 2025 16:42:58 -0700 Message-ID: <20250320234301.8342-8-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250320234301.8342-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> <20250320234301.8342-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" APX is introduced as xstate component 19, following AMX. However, in the non-compacted format, its offset overlaps with the space previously occupied by the now-deprecated MPX: 45fc24e89b7c ("x86/mpx: remove MPX from arch/x86") To prevent conflicts, the kernel must ensure the CPU never expose both features at the same time. If so, it indicates unreliable hardware. In such cases, XSAVE should be disabled entirely as a precautionary measure. Add a sanity check to detect this condition and disable XSAVE if an invalid hardware configuration is identified. Note: MPX state components remain enabled on legacy systems solely for KVM guest support. Signed-off-by: Chang S. Bae Reviewed-by: Sohil Mehta --- arch/x86/kernel/fpu/xstate.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 2a270683a762..0d68d5c4bc48 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -814,6 +814,17 @@ void __init fpu__init_system_xstate(unsigned int legac= y_size) goto out_disable; } =20 + if (fpu_kernel_cfg.max_features & XFEATURE_MASK_APX && + fpu_kernel_cfg.max_features & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_= BNDCSR)) { + /* + * This is a problematic CPU configuration where two + * conflicting state components are both enumerated. + */ + pr_err("x86/fpu: both APX and MPX present in the CPU's xstate features: = 0x%llx.\n", + fpu_kernel_cfg.max_features); + goto out_disable; + } + fpu_kernel_cfg.independent_features =3D fpu_kernel_cfg.max_features & XFEATURE_MASK_INDEPENDENT; =20 --=20 2.45.2 From nobody Wed Dec 17 08:54:45 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D3EE22D78A for ; Thu, 20 Mar 2025 23:43:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742514207; cv=none; b=CNQNhbQfCfpQRDr7ED5LCbl85TgOEm68XcvrcZcq5vOT/I+XMUyAsk5JDgh7sXFP9wCcRISvt8feQtYHfVXwLTrho0XBYGZSHnbFp+cXLutjsbpQVCfLvfjJrlX7BhEGBVqt7lYAT2cubS60ka5nF0BkEyyyHKyAP8U7wJ3aAJg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742514207; c=relaxed/simple; bh=qD6P1XLuScC/GDGjJU+aH/i/e6IvzbV5XOIX9N5YGfQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kMoi7o0bv4F5adSKc8GNcL23CT8w+O3Q5PY59/ghFAAm8ZcvzBF4CWHUm8VtWPydUUYJwP4lINMVNzQc567oUptmSohkXufo92lRyZQgla+JNY/ovcYaRYukHmvSybCDDE0Q/PVCaqsXqfHb4ckHduhitsZOXgK4A0ohjXqNL0w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Kve6RE+c; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Kve6RE+c" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742514206; x=1774050206; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qD6P1XLuScC/GDGjJU+aH/i/e6IvzbV5XOIX9N5YGfQ=; b=Kve6RE+c2mXSuH4je95pxNjV2a+Vg8RirHoGIWK12GSazcecsSBoGwxF XXD4LGheJ/vXhXYehSL01CwuPoB/L2o3wxZ5JRwIjgPaJ//XHGeFad8eH 83jZizJkjuulD6dthdT7R7zgEegqZrYmEZ09WCbR9yUYchoMUT/qDvyRT D6aYSeiqt2h1Kc1CaaO77uOdhT+WScWva6tmbKNLrSAjc4i2EkBtb2JZj 7ci7jqSiFX1qmP0iqejWiXs9U0psBWvLMLWusaFFQOYmBKRieoa4XrreA /eMSM8FO71B/bfouzhSdOV6r6c7NxzsvrL6Ui8c4ULy4KefTr8XG8kIDf g==; X-CSE-ConnectionGUID: PU5rCOgoSl6WVr+rVIgJQA== X-CSE-MsgGUID: RMqs61u+QNKfBI6vF8CqZA== X-IronPort-AV: E=McAfee;i="6700,10204,11379"; a="43502615" X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="43502615" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2025 16:43:26 -0700 X-CSE-ConnectionGUID: dQpHxLrzSoGXAR66ALJkFQ== X-CSE-MsgGUID: 4IQi0SRERFKavnepo+EoMQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="122963016" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.161.68]) by orviesa009.jf.intel.com with ESMTP; 20 Mar 2025 16:43:25 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v2 8/9] x86/fpu/apx: Enable APX state support Date: Thu, 20 Mar 2025 16:42:59 -0700 Message-ID: <20250320234301.8342-9-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250320234301.8342-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> <20250320234301.8342-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With securing APX against conflicting MPX, it is now ready to be enabled. Include APX in the enabled xfeature set. Signed-off-by: Chang S. Bae Reviewed-by: Sohil Mehta --- arch/x86/include/asm/fpu/xstate.h | 3 ++- arch/x86/kernel/fpu/xstate.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/fpu/xstate.h b/arch/x86/include/asm/fpu/x= state.h index 7f39fe7980c5..b308a76afbb7 100644 --- a/arch/x86/include/asm/fpu/xstate.h +++ b/arch/x86/include/asm/fpu/xstate.h @@ -32,7 +32,8 @@ XFEATURE_MASK_PKRU | \ XFEATURE_MASK_BNDREGS | \ XFEATURE_MASK_BNDCSR | \ - XFEATURE_MASK_XTILE) + XFEATURE_MASK_XTILE | \ + XFEATURE_MASK_APX) =20 /* * Features which are restored when returning to user space. diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 0d68d5c4bc48..a5e3954dc834 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -371,7 +371,8 @@ static __init void os_xrstor_booting(struct xregs_state= *xstate) XFEATURE_MASK_BNDCSR | \ XFEATURE_MASK_PASID | \ XFEATURE_MASK_CET_USER | \ - XFEATURE_MASK_XTILE) + XFEATURE_MASK_XTILE | \ + XFEATURE_MASK_APX) =20 /* * setup the xstate image representing the init state --=20 2.45.2 From nobody Wed Dec 17 08:54:45 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69EF422DF87 for ; Thu, 20 Mar 2025 23:43:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742514211; cv=none; b=uAUH56axXukzfbfMjs56vu6l1B7sHl2Fszsea6vhG3XT5qJ1q7fQKsN64uHA6HGL8FIw/z2XIWQlTyThTdnMu6bRYveLG+0WPBzojVRtSXcumfFHttqDC/oXmJ9aRQ2E6PtdacRaYZi2ZKjA9wCSh4OYIkdbIhx16b1Olccczyg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742514211; c=relaxed/simple; bh=M2VFfp1v80QZbwwejYrXXquMhO8yZWbF/M5k970bKvA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=esUVX+jQnPejnE+4ZF7jtPB8x/nv37sF3qTWm2iRT+dvQzcisaJBeCgr0AeUarDYpB32Z13AGfJdyw5n53WIOe3eJ64UqqGAzuJveQXJwL9535P67mAr1iVb+3+02xnAhqykkQbiKoa2T7vTkmYR98eIGI7XuLvnqU8PzNW8k9Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=W2xjhYi7; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="W2xjhYi7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742514209; x=1774050209; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=M2VFfp1v80QZbwwejYrXXquMhO8yZWbF/M5k970bKvA=; b=W2xjhYi7kLZ71mQhxI2ni5xL1L5w8uztc+v47PHUws46Pp2Q7HcIk6Ii /Q2FfE7iKH+22Q5GMD/dnQCmnCqPlnO9x70bMDVY5WJje41KFPM3dzCBp Pxcq5LOxQjAWlkFdCWdabmmOXBLEwLdIbYftCBl5Qkp0Lpse/agXPb4tB b6hfN6Id4evxtAT/sw04VFVAOFqmG9uUHFyrY6ZIFZQ6f86bBm7Q7aKJQ k2klUxBgi7r9RVIOZbauyuLpdSyAAdww4PSzJCQvrnOeCGIw6MYgIy/Ff v8DmK0APQBwCq5KfXFRUs7+9LolfB6uVFJWXDrb5zwdaaJiYzW1Jv9Swb w==; X-CSE-ConnectionGUID: vhnqpJo5QWyT3JF3PgYPiQ== X-CSE-MsgGUID: GAN7w1FwRiiOVaS9qo83Sw== X-IronPort-AV: E=McAfee;i="6700,10204,11379"; a="43502620" X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="43502620" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2025 16:43:29 -0700 X-CSE-ConnectionGUID: UQ+ZVJQuTyK5P6/ajFN2ow== X-CSE-MsgGUID: bm0KlM2NTNSoMysijyAMYg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,263,1736841600"; d="scan'208";a="122963028" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.161.68]) by orviesa009.jf.intel.com with ESMTP; 20 Mar 2025 16:43:28 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC v2 9/9] selftests/x86/apx: Add APX test Date: Thu, 20 Mar 2025 16:43:00 -0700 Message-ID: <20250320234301.8342-10-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250320234301.8342-1-chang.seok.bae@intel.com> References: <20250227184502.10288-1-chang.seok.bae@intel.com> <20250320234301.8342-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The extended general-purpose registers for APX may contain random data, which is currently assumed by the xstate testing framework. This allows the testing of the new userspace feature using the common test code. Invoke the test entry function from apx.c after enumerating the state component and adding it to the support list Signed-off-by: Chang S. Bae Reviewed-by: Sohil Mehta --- The patch depends on the selftest xstate series, which was just merged into the x86/fpu branch as of now: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/log/?h=3Dx86/= fpu Here is the original series posting for the record: https://lore.kernel.org/lkml/20250226010731.2456-1-chang.seok.bae@intel.c= om/ --- tools/testing/selftests/x86/Makefile | 3 ++- tools/testing/selftests/x86/apx.c | 10 ++++++++++ tools/testing/selftests/x86/xstate.c | 3 ++- tools/testing/selftests/x86/xstate.h | 2 ++ 4 files changed, 16 insertions(+), 2 deletions(-) create mode 100644 tools/testing/selftests/x86/apx.c diff --git a/tools/testing/selftests/x86/Makefile b/tools/testing/selftests= /x86/Makefile index 28422c32cc8f..f703fcfe9f7c 100644 --- a/tools/testing/selftests/x86/Makefile +++ b/tools/testing/selftests/x86/Makefile @@ -19,7 +19,7 @@ TARGETS_C_32BIT_ONLY :=3D entry_from_vm86 test_syscall_vd= so unwind_vdso \ test_FCMOV test_FCOMI test_FISTTP \ vdso_restorer TARGETS_C_64BIT_ONLY :=3D fsgsbase sysret_rip syscall_numbering \ - corrupt_xstate_header amx lam test_shadow_stack avx + corrupt_xstate_header amx lam test_shadow_stack avx apx # Some selftests require 32bit support enabled also on 64bit systems TARGETS_C_32BIT_NEEDED :=3D ldt_gdt ptrace_syscall =20 @@ -136,3 +136,4 @@ $(OUTPUT)/nx_stack_64: CFLAGS +=3D -Wl,-z,noexecstack $(OUTPUT)/avx_64: CFLAGS +=3D -mno-avx -mno-avx512f $(OUTPUT)/amx_64: EXTRA_FILES +=3D xstate.c $(OUTPUT)/avx_64: EXTRA_FILES +=3D xstate.c +$(OUTPUT)/apx_64: EXTRA_FILES +=3D xstate.c diff --git a/tools/testing/selftests/x86/apx.c b/tools/testing/selftests/x8= 6/apx.c new file mode 100644 index 000000000000..d9c8d41b8c5a --- /dev/null +++ b/tools/testing/selftests/x86/apx.c @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 + +#define _GNU_SOURCE + +#include "xstate.h" + +int main(void) +{ + test_xstate(XFEATURE_APX); +} diff --git a/tools/testing/selftests/x86/xstate.c b/tools/testing/selftests= /x86/xstate.c index 23c1d6c964ea..97fe4bd8bc77 100644 --- a/tools/testing/selftests/x86/xstate.c +++ b/tools/testing/selftests/x86/xstate.c @@ -31,7 +31,8 @@ (1 << XFEATURE_OPMASK) | \ (1 << XFEATURE_ZMM_Hi256) | \ (1 << XFEATURE_Hi16_ZMM) | \ - (1 << XFEATURE_XTILEDATA)) + (1 << XFEATURE_XTILEDATA) | \ + (1 << XFEATURE_APX)) =20 static inline uint64_t xgetbv(uint32_t index) { diff --git a/tools/testing/selftests/x86/xstate.h b/tools/testing/selftests= /x86/xstate.h index 42af36ec852f..e91e3092b5d2 100644 --- a/tools/testing/selftests/x86/xstate.h +++ b/tools/testing/selftests/x86/xstate.h @@ -33,6 +33,7 @@ enum xfeature { XFEATURE_RSRVD_COMP_16, XFEATURE_XTILECFG, XFEATURE_XTILEDATA, + XFEATURE_APX, =20 XFEATURE_MAX, }; @@ -59,6 +60,7 @@ static const char *xfeature_names[] =3D "unknown xstate feature", "AMX Tile config", "AMX Tile data", + "APX registers", "unknown xstate feature", }; =20 --=20 2.45.2