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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7390600b9b1sm249308b3a.76.2025.03.20.13.24.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Mar 2025 13:24:15 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, srinivas.kandagatla@linaro.org, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Subject: [PATCH v3 3/5 RESEND] thermal: qcom-spmi-temp-alarm: Prepare to support additional Temp Alarm subtypes Date: Thu, 20 Mar 2025 13:24:06 -0700 Message-Id: <20250320202408.3940777-4-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250320202408.3940777-1-anjelique.melendez@oss.qualcomm.com> References: <20250320202408.3940777-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: m1VXYcEBut1Xs0iNlrwJ60EaAU3LTyOQ X-Proofpoint-GUID: m1VXYcEBut1Xs0iNlrwJ60EaAU3LTyOQ X-Authority-Analysis: v=2.4 cv=T52MT+KQ c=1 sm=1 tr=0 ts=67dc7971 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=7un5503AD7E7R8fKnWkA:9 a=RVmHIydaz68A:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-20_07,2025-03-20_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 mlxscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 phishscore=0 spamscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503200131 Content-Type: text/plain; charset="utf-8" In preparation to support newer temp alarm subtypes, add the "ops" and "configure_trip_temps" references to spmi_temp_alarm_data. This will allow for each Temp Alarm subtype to define its own thermal_zone_device_ops and properly configure thermal trip temperature. Signed-off-by: Anjelique Melendez Reviewed-by: Dmitry Baryshkov --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 38 ++++++++++++++------- 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index 1cc9369ca9e1..514772e94a28 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights r= eserved. - * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights re= served. */ =20 #include @@ -71,8 +71,10 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_C= OUNT] =3D { struct qpnp_tm_chip; =20 struct spmi_temp_alarm_data { + const struct thermal_zone_device_ops *ops; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; int (*get_temp_stage)(struct qpnp_tm_chip *chip); + int (*configure_trip_temps)(struct qpnp_tm_chip *chip); }; =20 struct qpnp_tm_chip { @@ -312,18 +314,39 @@ static irqreturn_t qpnp_tm_isr(int irq, void *data) return IRQ_HANDLED; } =20 +static int qpnp_tm_configure_trip_temp(struct qpnp_tm_chip *chip) +{ + int crit_temp, ret; + + mutex_unlock(&chip->lock); + + ret =3D thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp); + if (ret) + crit_temp =3D THERMAL_TEMP_INVALID; + + mutex_lock(&chip->lock); + + return qpnp_tm_update_critical_trip_temp(chip, crit_temp); +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { + .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, + .configure_trip_temps =3D qpnp_tm_configure_trip_temp, .get_temp_stage =3D qpnp_tm_gen1_get_temp_stage, }; =20 static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_data =3D { + .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, + .configure_trip_temps =3D qpnp_tm_configure_trip_temp, .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev1_data = =3D { + .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen2_v1, + .configure_trip_temps =3D qpnp_tm_configure_trip_temp, .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 @@ -336,7 +359,6 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) { int ret; u8 reg =3D 0; - int crit_temp; =20 mutex_lock(&chip->lock); =20 @@ -355,15 +377,7 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) if (chip->stage) chip->temp =3D qpnp_tm_decode_temp(chip, chip->stage); =20 - mutex_unlock(&chip->lock); - - ret =3D thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp); - if (ret) - crit_temp =3D THERMAL_TEMP_INVALID; - - mutex_lock(&chip->lock); - - ret =3D qpnp_tm_update_critical_trip_temp(chip, crit_temp); + ret =3D chip->data->configure_trip_temps(chip); if (ret < 0) goto out; =20 @@ -483,7 +497,7 @@ static int qpnp_tm_probe(struct platform_device *pdev) * before the hardware initialization is completed. */ chip->tz_dev =3D devm_thermal_of_zone_register( - &pdev->dev, 0, chip, &qpnp_tm_sensor_ops); + &pdev->dev, 0, chip, chip->data->ops); if (IS_ERR(chip->tz_dev)) return dev_err_probe(&pdev->dev, PTR_ERR(chip->tz_dev), "failed to register sensor\n"); --=20 2.34.1