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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-85e2bd8c40fsm8341439f.32.2025.03.20.12.44.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Mar 2025 12:44:54 -0700 (PDT) From: Alex Elder To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] dt-bindings: soc: spacemit: define spacemit,k1-ccu resets Date: Thu, 20 Mar 2025 14:44:42 -0500 Message-ID: <20250320194449.510569-2-elder@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250320194449.510569-1-elder@riscstar.com> References: <20250320194449.510569-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are additional SpacemiT syscon CCUs whose registers control both clocks and resets: RCPU, RCPU2, and APBC2. Unlike those defined previously, these will initially support only resets. They do not incorporate power domain functionality. Define the index values for resets associated with all SpacemiT K1 syscon nodes, including those with clocks already defined, as well as the new ones (without clocks). Signed-off-by: Alex Elder --- .../soc/spacemit/spacemit,k1-syscon.yaml | 13 +- include/dt-bindings/clock/spacemit,k1-ccu.h | 134 ++++++++++++++++++ 2 files changed, 143 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-sys= con.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-sysco= n.yaml index 07a6728e6f864..333c28e075b6c 100644 --- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml @@ -19,6 +19,9 @@ properties: - spacemit,k1-syscon-apbc - spacemit,k1-syscon-apmu - spacemit,k1-syscon-mpmu + - spacemit,k1-syscon-rcpu + - spacemit,k1-syscon-rcpu2 + - spacemit,k1-syscon-apbc2 =20 reg: maxItems: 1 @@ -57,13 +60,15 @@ allOf: properties: compatible: contains: - const: spacemit,k1-syscon-apbc + enum: + - spacemit,k1-syscon-apmu + - spacemit,k1-syscon-mpmu then: - properties: - "#power-domain-cells": false - else: required: - "#power-domain-cells" + else: + properties: + "#power-domain-cells": false =20 additionalProperties: false =20 diff --git a/include/dt-bindings/clock/spacemit,k1-ccu.h b/include/dt-bindi= ngs/clock/spacemit,k1-ccu.h index 4a0c7163257e3..a1e1b1fe714ce 100644 --- a/include/dt-bindings/clock/spacemit,k1-ccu.h +++ b/include/dt-bindings/clock/spacemit,k1-ccu.h @@ -78,6 +78,9 @@ #define CLK_APB 31 #define CLK_WDT_BUS 32 =20 +/* MPMU resets */ +#define RST_WDT 0 + /* APBC clocks */ #define CLK_UART0 0 #define CLK_UART2 1 @@ -109,6 +112,7 @@ #define CLK_PWM17 27 #define CLK_PWM18 28 #define CLK_PWM19 29 + #define CLK_SSP3 30 #define CLK_RTC 31 #define CLK_TWSI0 32 @@ -180,6 +184,60 @@ #define CLK_TSEN_BUS 98 #define CLK_IPC_AP2AUD_BUS 99 =20 +/* APBC resets */ + +#define RST_UART0 0 +#define RST_UART2 1 +#define RST_UART3 2 +#define RST_UART4 3 +#define RST_UART5 4 +#define RST_UART6 5 +#define RST_UART7 6 +#define RST_UART8 7 +#define RST_UART9 8 +#define RST_GPIO 9 +#define RST_PWM0 10 +#define RST_PWM1 11 +#define RST_PWM2 12 +#define RST_PWM3 13 +#define RST_PWM4 14 +#define RST_PWM5 15 +#define RST_PWM6 16 +#define RST_PWM7 17 +#define RST_PWM8 18 +#define RST_PWM9 19 +#define RST_PWM10 20 +#define RST_PWM11 21 +#define RST_PWM12 22 +#define RST_PWM13 23 +#define RST_PWM14 24 +#define RST_PWM15 25 +#define RST_PWM16 26 +#define RST_PWM17 27 +#define RST_PWM18 28 +#define RST_PWM19 29 +#define RST_SSP3 30 +#define RST_RTC 31 +#define RST_TWSI0 32 +#define RST_TWSI1 33 +#define RST_TWSI2 34 +#define RST_TWSI4 35 +#define RST_TWSI5 36 +#define RST_TWSI6 37 +#define RST_TWSI7 38 +#define RST_TWSI8 39 +#define RST_TIMERS1 40 +#define RST_TIMERS2 41 +#define RST_AIB 42 +#define RST_ONEWIRE 43 +#define RST_SSPA0 44 +#define RST_SSPA1 45 +#define RST_DRO 46 +#define RST_IR 47 +#define RST_TSEN 48 +#define RST_IPC_AP2AUD 49 +#define RST_CAN0 50 + /* APMU clocks */ #define CLK_CCI550 0 #define CLK_CPU_C0_HI 1 @@ -244,4 +302,80 @@ #define CLK_V2D 60 #define CLK_EMMC_BUS 61 =20 +/* APMU resets */ + +#define RST_CCIC_4X 0 +#define RST_CCIC1_PHY 1 +#define RST_SDH_AXI 2 +#define RST_SDH0 3 +#define RST_SDH1 4 +#define RST_SDH2 5 +#define RST_USBP1_AXI 6 +#define RST_USB_AXI 7 +#define RST_USB3_0 8 +#define RST_QSPI 9 +#define RST_QSPI_BUS 10 +#define RST_DMA 11 +#define RST_AES 12 +#define RST_VPU 13 +#define RST_GPU 14 +#define RST_EMMC 15 +#define RST_EMMC_X 16 +#define RST_AUDIO 17 +#define RST_HDMI 18 +#define RST_PCIE0 19 +#define RST_PCIE1 20 +#define RST_PCIE2 21 +#define RST_EMAC0 22 +#define RST_EMAC1 23 +#define RST_JPG 24 +#define RST_CCIC2PHY 25 +#define RST_CCIC3PHY 26 +#define RST_CSI 27 +#define RST_ISP_CPP 28 +#define RST_ISP_BUS 29 +#define RST_ISP 30 +#define RST_ISP_CI 31 +#define RST_DPU_MCLK 32 +#define RST_DPU_ESC 33 +#define RST_DPU_HCLK 34 +#define RST_DPU_SPIBUS 35 +#define RST_DPU_SPI_HBUS 36 +#define RST_V2D 37 +#define RST_MIPI 38 +#define RST_MC 39 + +/* RCPU resets */ + +#define RST_RCPU_SSP0 0 +#define RST_RCPU_I2C0 1 +#define RST_RCPU_UART1 2 +#define RST_RCPU_IR 3 +#define RST_RCPU_CAN 4 +#define RST_RCPU_UART0 5 +#define RST_RCPU_HDMI_AUDIO 6 + +/* RCPU2 resets */ + +#define RST_RCPU2_PWM0 0 +#define RST_RCPU2_PWM1 1 +#define RST_RCPU2_PWM2 2 +#define RST_RCPU2_PWM3 3 +#define RST_RCPU2_PWM4 4 +#define RST_RCPU2_PWM5 5 +#define RST_RCPU2_PWM6 6 +#define RST_RCPU2_PWM7 7 +#define RST_RCPU2_PWM8 8 +#define RST_RCPU2_PWM9 9 + +/* APBC2 resets */ + +#define RST_APBC2_UART1 0 +#define RST_APBC2_SSP2 1 +#define RST_APBC2_TWSI3 2 +#define RST_APBC2_RTC 3 +#define RST_APBC2_TIMERS0 4 +#define RST_APBC2_KPC 5 +#define RST_APBC2_GPIO 6 + #endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */ --=20 2.43.0 From nobody Wed Dec 17 08:56:01 2025 Received: from mail-io1-f45.google.com (mail-io1-f45.google.com [209.85.166.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B787322ACCE for ; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-85e2bd8c40fsm8341439f.32.2025.03.20.12.44.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Mar 2025 12:44:56 -0700 (PDT) From: Alex Elder To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] clk: spacemit: define struct k1_ccu_data Date: Thu, 20 Mar 2025 14:44:43 -0500 Message-ID: <20250320194449.510569-3-elder@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250320194449.510569-1-elder@riscstar.com> References: <20250320194449.510569-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define a new structure type to be used for describing the OF match data. Rather than using the array of spacemit_ccu_clk structures for match data, we use this structure instead. Move the definition of the spacemit_ccu_clk structure closer to the top of the source file, and add the new structure definition below it. Shorten the name of spacemit_ccu_register() to be k1_ccu_register(). Signed-off-by: Alex Elder --- drivers/clk/spacemit/ccu-k1.c | 58 ++++++++++++++++++++++++++--------- 1 file changed, 43 insertions(+), 15 deletions(-) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 44db48ae71313..f7367271396a0 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -129,6 +129,15 @@ #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 #define APMU_EMAC1_CLK_RES_CTRL 0x3ec =20 +struct spacemit_ccu_clk { + int id; + struct clk_hw *hw; +}; + +struct k1_ccu_data { + struct spacemit_ccu_clk *clk; /* array with sentinel */ +}; + /* APBS clocks start */ =20 /* Frequency of pll{1,2} should not be updated at runtime */ @@ -1359,11 +1368,6 @@ static CCU_GATE_DEFINE(emmc_bus_clk, CCU_PARENT_HW(p= mua_aclk), 0); /* APMU clocks end */ =20 -struct spacemit_ccu_clk { - int id; - struct clk_hw *hw; -}; - static struct spacemit_ccu_clk k1_ccu_apbs_clks[] =3D { { CLK_PLL1, &pll1.common.hw }, { CLK_PLL2, &pll2.common.hw }, @@ -1403,6 +1407,10 @@ static struct spacemit_ccu_clk k1_ccu_apbs_clks[] = =3D { { 0, NULL }, }; =20 +static const struct k1_ccu_data k1_ccu_apbs_data =3D { + .clk =3D k1_ccu_apbs_clks, +}; + static struct spacemit_ccu_clk k1_ccu_mpmu_clks[] =3D { { CLK_PLL1_307P2, &pll1_d8_307p2.common.hw }, { CLK_PLL1_76P8, &pll1_d32_76p8.common.hw }, @@ -1440,6 +1448,10 @@ static struct spacemit_ccu_clk k1_ccu_mpmu_clks[] = =3D { { 0, NULL }, }; =20 +static const struct k1_ccu_data k1_ccu_mpmu_data =3D { + .clk =3D k1_ccu_mpmu_clks, +}; + static struct spacemit_ccu_clk k1_ccu_apbc_clks[] =3D { { CLK_UART0, &uart0_clk.common.hw }, { CLK_UART2, &uart2_clk.common.hw }, @@ -1544,6 +1556,10 @@ static struct spacemit_ccu_clk k1_ccu_apbc_clks[] = =3D { { 0, NULL }, }; =20 +static const struct k1_ccu_data k1_ccu_apbc_data =3D { + .clk =3D k1_ccu_apbc_clks, +}; + static struct spacemit_ccu_clk k1_ccu_apmu_clks[] =3D { { CLK_CCI550, &cci550_clk.common.hw }, { CLK_CPU_C0_HI, &cpu_c0_hi_clk.common.hw }, @@ -1610,9 +1626,13 @@ static struct spacemit_ccu_clk k1_ccu_apmu_clks[] = =3D { { 0, NULL }, }; =20 -static int spacemit_ccu_register(struct device *dev, - struct regmap *regmap, struct regmap *lock_regmap, - const struct spacemit_ccu_clk *clks) +static const struct k1_ccu_data k1_ccu_apmu_data =3D { + .clk =3D k1_ccu_apmu_clks, +}; + +static int k1_ccu_register(struct device *dev, struct regmap *regmap, + struct regmap *lock_regmap, + struct spacemit_ccu_clk *clks) { const struct spacemit_ccu_clk *clk; int i, ret, max_id =3D 0; @@ -1648,15 +1668,24 @@ static int spacemit_ccu_register(struct device *dev, =20 clk_data->num =3D max_id + 1; =20 - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret) + dev_err(dev, "error %d adding clock hardware provider\n", ret); + + return ret; } =20 static int k1_ccu_probe(struct platform_device *pdev) { struct regmap *base_regmap, *lock_regmap =3D NULL; struct device *dev =3D &pdev->dev; + const struct k1_ccu_data *data; int ret; =20 + data =3D of_device_get_match_data(dev); + if (!data) + return -EINVAL; + base_regmap =3D device_node_to_regmap(dev->of_node); if (IS_ERR(base_regmap)) return dev_err_probe(dev, PTR_ERR(base_regmap), @@ -1677,8 +1706,7 @@ static int k1_ccu_probe(struct platform_device *pdev) "failed to get lock regmap\n"); } =20 - ret =3D spacemit_ccu_register(dev, base_regmap, lock_regmap, - of_device_get_match_data(dev)); + ret =3D k1_ccu_register(dev, base_regmap, lock_regmap, data->clk); if (ret) return dev_err_probe(dev, ret, "failed to register clocks\n"); =20 @@ -1688,19 +1716,19 @@ static int k1_ccu_probe(struct platform_device *pde= v) static const struct of_device_id of_k1_ccu_match[] =3D { { .compatible =3D "spacemit,k1-pll", - .data =3D k1_ccu_apbs_clks, + .data =3D &k1_ccu_apbs_data, }, { .compatible =3D "spacemit,k1-syscon-mpmu", - .data =3D k1_ccu_mpmu_clks, + .data =3D &k1_ccu_mpmu_data, }, { .compatible =3D "spacemit,k1-syscon-apbc", - .data =3D k1_ccu_apbc_clks, + .data =3D &k1_ccu_apbc_data, }, { .compatible =3D "spacemit,k1-syscon-apmu", - .data =3D k1_ccu_apmu_clks, + .data =3D &k1_ccu_apmu_data, }, { } }; --=20 2.43.0 From nobody Wed Dec 17 08:56:01 2025 Received: from mail-io1-f46.google.com (mail-io1-f46.google.com [209.85.166.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EFC922B590 for ; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-85e2bd8c40fsm8341439f.32.2025.03.20.12.44.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Mar 2025 12:44:58 -0700 (PDT) From: Alex Elder To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] clk: spacemit: add reset controller support Date: Thu, 20 Mar 2025 14:44:44 -0500 Message-ID: <20250320194449.510569-4-elder@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250320194449.510569-1-elder@riscstar.com> References: <20250320194449.510569-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define ccu_reset_data as a structure that contains the constant register offset and bitmasks used to assert and deassert a reset control on a SpacemiT K1 CCU. Define ccu_reset_controller_data as a structure that contains the address of an array of those structures and a count of the number of elements in the array. Add a pointer to a ccu_reset_controller_data structure to the k1_ccu_data structure. Reset support is optional for SpacemiT CCUs; the new pointer field will be null for CCUs without any resets. Finally, define a new ccu_reset_controller structure, which (for a CCU with resets) contains a pointer to the constant reset data, the regmap to be used for the controller, and an embedded a reset controller structure. Each reset control is asserted or deasserted by updating bits in a register. The bits used are defined by an assert mask and a deassert mask. In some cases, one (non-zero) mask asserts reset and a different (non-zero) mask deasserts it. Otherwise one mask is nonzero, and the other is zero. Either way, the bits in both masks are cleared, then either the assert mask or the deassert mask is set in a register to affect the state of a reset control. Signed-off-by: Alex Elder --- drivers/clk/spacemit/ccu-k1.c | 93 +++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index f7367271396a0..6d879411c6c05 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 #include "ccu_common.h" #include "ccu_pll.h" @@ -134,8 +135,26 @@ struct spacemit_ccu_clk { struct clk_hw *hw; }; =20 +struct ccu_reset_data { + u32 offset; + u32 assert_mask; + u32 deassert_mask; +}; + +struct ccu_reset_controller_data { + u32 count; + const struct ccu_reset_data *data; /* array */ +}; + struct k1_ccu_data { struct spacemit_ccu_clk *clk; /* array with sentinel */ + const struct ccu_reset_controller_data *rst_data; +}; + +struct ccu_reset_controller { + struct regmap *regmap; + const struct ccu_reset_controller_data *data; + struct reset_controller_dev rcdev; }; =20 /* APBS clocks start */ @@ -1630,6 +1649,48 @@ static const struct k1_ccu_data k1_ccu_apmu_data =3D= { .clk =3D k1_ccu_apmu_clks, }; =20 +static struct ccu_reset_controller * +rcdev_to_controller(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct ccu_reset_controller, rcdev); +} + +static int +k1_rst_update(struct reset_controller_dev *rcdev, unsigned long id, bool a= ssert) +{ + struct ccu_reset_controller *controller =3D rcdev_to_controller(rcdev); + struct regmap *regmap =3D controller->regmap; + const struct ccu_reset_data *data; + u32 val; + int ret; + + data =3D &controller->data->data[id]; + + ret =3D regmap_read(regmap, data->offset, &val); + if (ret) + return ret; + + val &=3D ~(data->assert_mask | data->deassert_mask); + val |=3D assert ? data->assert_mask : data->deassert_mask; + + return regmap_write(regmap, data->offset, val); +} + +static int k1_rst_assert(struct reset_controller_dev *rcdev, unsigned long= id) +{ + return k1_rst_update(rcdev, id, true); +} + +static int k1_rst_deassert(struct reset_controller_dev *rcdev, unsigned lo= ng id) +{ + return k1_rst_update(rcdev, id, false); +} + +static const struct reset_control_ops k1_reset_control_ops =3D { + .assert =3D k1_rst_assert, + .deassert =3D k1_rst_deassert, +}; + static int k1_ccu_register(struct device *dev, struct regmap *regmap, struct regmap *lock_regmap, struct spacemit_ccu_clk *clks) @@ -1675,6 +1736,33 @@ static int k1_ccu_register(struct device *dev, struc= t regmap *regmap, return ret; } =20 +static int +k1_reset_controller_register(struct device *dev, struct regmap *regmap, + const struct ccu_reset_controller_data *data) +{ + struct ccu_reset_controller *controller; + struct reset_controller_dev *rcdev; + + /* Resets are optional */ + if (!data) + return 0; + + controller =3D devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); + if (!controller) + return -ENOMEM; + + controller->regmap =3D regmap; + controller->data =3D data; + + rcdev =3D &controller->rcdev; + rcdev->owner =3D THIS_MODULE; + rcdev->nr_resets =3D data->count; + rcdev->ops =3D &k1_reset_control_ops; + rcdev->of_node =3D dev->of_node; + + return devm_reset_controller_register(dev, rcdev); +} + static int k1_ccu_probe(struct platform_device *pdev) { struct regmap *base_regmap, *lock_regmap =3D NULL; @@ -1710,6 +1798,11 @@ static int k1_ccu_probe(struct platform_device *pdev) if (ret) return dev_err_probe(dev, ret, "failed to register clocks\n"); =20 + ret =3D k1_reset_controller_register(dev, base_regmap, data->rst_data); + if (ret) + return dev_err_probe(dev, ret, + "failed to register reset controller\n"); + return 0; } =20 --=20 2.43.0 From nobody Wed Dec 17 08:56:01 2025 Received: from mail-io1-f54.google.com (mail-io1-f54.google.com [209.85.166.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10AF322B5A6 for ; Thu, 20 Mar 2025 19:45:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-85e2bd8c40fsm8341439f.32.2025.03.20.12.44.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Mar 2025 12:44:59 -0700 (PDT) From: Alex Elder To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] clk: spacemit: define existing syscon resets Date: Thu, 20 Mar 2025 14:44:45 -0500 Message-ID: <20250320194449.510569-5-elder@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250320194449.510569-1-elder@riscstar.com> References: <20250320194449.510569-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define reset controls associated with the MPMU, APBC, and APMU SpacemiT K1 CCUs. These already have clocks associated with them. Signed-off-by: Alex Elder --- drivers/clk/spacemit/ccu-k1.c | 132 ++++++++++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 6d879411c6c05..be8abd27753cb 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -151,6 +151,13 @@ struct k1_ccu_data { const struct ccu_reset_controller_data *rst_data; }; =20 +#define RST_DATA(_offset, _assert_mask, _deassert_mask) \ + { \ + .offset =3D (_offset), \ + .assert_mask =3D (_assert_mask), \ + .deassert_mask =3D (_deassert_mask), \ + } + struct ccu_reset_controller { struct regmap *regmap; const struct ccu_reset_controller_data *data; @@ -1428,6 +1435,7 @@ static struct spacemit_ccu_clk k1_ccu_apbs_clks[] =3D= { =20 static const struct k1_ccu_data k1_ccu_apbs_data =3D { .clk =3D k1_ccu_apbs_clks, + /* No resets in the APBS CCU */ }; =20 static struct spacemit_ccu_clk k1_ccu_mpmu_clks[] =3D { @@ -1467,8 +1475,18 @@ static struct spacemit_ccu_clk k1_ccu_mpmu_clks[] = =3D { { 0, NULL }, }; =20 +static const struct ccu_reset_data mpmu_reset_data[] =3D { + [RST_WDT] =3D RST_DATA(MPMU_WDTPCR, BIT(2), 0), +}; + +static const struct ccu_reset_controller_data mpmu_reset_controller_data = =3D { + .count =3D ARRAY_SIZE(mpmu_reset_data), + .data =3D mpmu_reset_data, +}; + static const struct k1_ccu_data k1_ccu_mpmu_data =3D { .clk =3D k1_ccu_mpmu_clks, + .rst_data =3D &mpmu_reset_controller_data, }; =20 static struct spacemit_ccu_clk k1_ccu_apbc_clks[] =3D { @@ -1575,8 +1593,68 @@ static struct spacemit_ccu_clk k1_ccu_apbc_clks[] = =3D { { 0, NULL }, }; =20 +static const struct ccu_reset_data apbc_reset_data[] =3D { + [RST_UART0] =3D RST_DATA(APBC_UART1_CLK_RST, BIT(2), 0), + [RST_UART2] =3D RST_DATA(APBC_UART2_CLK_RST, BIT(2), 0), + [RST_GPIO] =3D RST_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), + [RST_PWM0] =3D RST_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)), + [RST_PWM1] =3D RST_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)), + [RST_PWM2] =3D RST_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)), + [RST_PWM3] =3D RST_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)), + [RST_PWM4] =3D RST_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)), + [RST_PWM5] =3D RST_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)), + [RST_PWM6] =3D RST_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)), + [RST_PWM7] =3D RST_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)), + [RST_PWM8] =3D RST_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)), + [RST_PWM9] =3D RST_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_PWM10] =3D RST_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)), + [RST_PWM11] =3D RST_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)), + [RST_PWM12] =3D RST_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)), + [RST_PWM13] =3D RST_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)), + [RST_PWM14] =3D RST_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)), + [RST_PWM15] =3D RST_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)), + [RST_PWM16] =3D RST_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)), + [RST_PWM17] =3D RST_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)), + [RST_PWM18] =3D RST_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)), + [RST_PWM19] =3D RST_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)), + [RST_SSP3] =3D RST_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), + [RST_UART3] =3D RST_DATA(APBC_UART3_CLK_RST, BIT(2), 0), + [RST_RTC] =3D RST_DATA(APBC_RTC_CLK_RST, BIT(2), 0), + [RST_TWSI0] =3D RST_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), + [RST_TIMERS1] =3D RST_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), + [RST_AIB] =3D RST_DATA(APBC_AIB_CLK_RST, BIT(2), 0), + [RST_TIMERS2] =3D RST_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), + [RST_ONEWIRE] =3D RST_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), + [RST_SSPA0] =3D RST_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), + [RST_SSPA1] =3D RST_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), + [RST_DRO] =3D RST_DATA(APBC_DRO_CLK_RST, BIT(2), 0), + [RST_IR] =3D RST_DATA(APBC_IR_CLK_RST, BIT(2), 0), + [RST_TWSI1] =3D RST_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), + [RST_TSEN] =3D RST_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), + [RST_TWSI2] =3D RST_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), + [RST_TWSI4] =3D RST_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), + [RST_TWSI5] =3D RST_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), + [RST_TWSI6] =3D RST_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), + [RST_TWSI7] =3D RST_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0), + [RST_TWSI8] =3D RST_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), + [RST_IPC_AP2AUD] =3D RST_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), + [RST_UART4] =3D RST_DATA(APBC_UART4_CLK_RST, BIT(2), 0), + [RST_UART5] =3D RST_DATA(APBC_UART5_CLK_RST, BIT(2), 0), + [RST_UART6] =3D RST_DATA(APBC_UART6_CLK_RST, BIT(2), 0), + [RST_UART7] =3D RST_DATA(APBC_UART7_CLK_RST, BIT(2), 0), + [RST_UART8] =3D RST_DATA(APBC_UART8_CLK_RST, BIT(2), 0), + [RST_UART9] =3D RST_DATA(APBC_UART9_CLK_RST, BIT(2), 0), + [RST_CAN0] =3D RST_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), +}; + +static const struct ccu_reset_controller_data apbc_reset_controller_data = =3D { + .count =3D ARRAY_SIZE(apbc_reset_data), + .data =3D apbc_reset_data, +}; + static const struct k1_ccu_data k1_ccu_apbc_data =3D { .clk =3D k1_ccu_apbc_clks, + .rst_data =3D &apbc_reset_controller_data, }; =20 static struct spacemit_ccu_clk k1_ccu_apmu_clks[] =3D { @@ -1645,8 +1723,62 @@ static struct spacemit_ccu_clk k1_ccu_apmu_clks[] = =3D { { 0, NULL }, }; =20 +static const struct ccu_reset_data apmu_reset_data[] =3D { + [RST_CCIC_4X] =3D RST_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), + [RST_CCIC1_PHY] =3D RST_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), + [RST_SDH_AXI] =3D RST_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), + [RST_SDH0] =3D RST_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), + [RST_SDH1] =3D RST_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), + [RST_SDH2] =3D RST_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), + [RST_USBP1_AXI] =3D RST_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)), + [RST_USB_AXI] =3D RST_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), + [RST_USB3_0] =3D RST_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(9)|BIT(10)|BIT(11)), + [RST_QSPI] =3D RST_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), + [RST_QSPI_BUS] =3D RST_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), + [RST_DMA] =3D RST_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), + [RST_AES] =3D RST_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), + [RST_VPU] =3D RST_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), + [RST_GPU] =3D RST_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), + [RST_EMMC] =3D RST_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)), + [RST_EMMC_X] =3D RST_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)), + [RST_AUDIO] =3D RST_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, + BIT(0) | BIT(2) | BIT(3)), + [RST_HDMI] =3D RST_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)), + [RST_PCIE0] =3D RST_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8), + BIT(3) | BIT(4) | BIT(5)), + [RST_PCIE1] =3D RST_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8), + BIT(3) | BIT(4) | BIT(5)), + [RST_PCIE2] =3D RST_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8), + BIT(3) | BIT(4) | BIT(5)), + [RST_EMAC0] =3D RST_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), + [RST_EMAC1] =3D RST_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), + [RST_JPG] =3D RST_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)), + [RST_CCIC2PHY] =3D RST_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), + [RST_CCIC3PHY] =3D RST_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), + [RST_CSI] =3D RST_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), + [RST_ISP] =3D RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)), + [RST_ISP_CPP] =3D RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)), + [RST_ISP_BUS] =3D RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)), + [RST_ISP_CI] =3D RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), + [RST_DPU_MCLK] =3D RST_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), + [RST_DPU_ESC] =3D RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), + [RST_DPU_HCLK] =3D RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), + [RST_DPU_SPIBUS] =3D RST_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)), + [RST_DPU_SPI_HBUS] =3D RST_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)), + [RST_V2D] =3D RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), + [RST_MIPI] =3D RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)), + [RST_MC] =3D RST_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), +}; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-85e2bd8c40fsm8341439f.32.2025.03.20.12.45.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Mar 2025 12:45:01 -0700 (PDT) From: Alex Elder To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] clk: spacemit: make clocks optional Date: Thu, 20 Mar 2025 14:44:46 -0500 Message-ID: <20250320194449.510569-6-elder@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250320194449.510569-1-elder@riscstar.com> References: <20250320194449.510569-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are some syscon devices that support both clocks and resets, but for now only their reset functionality is required. Make defining clocks optional for a SpacemiT CCU, though at least one clock or at least one reset controller must be defined. Signed-off-by: Alex Elder --- drivers/clk/spacemit/ccu-k1.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index be8abd27753cb..17e321c25959a 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -1830,6 +1830,10 @@ static int k1_ccu_register(struct device *dev, struc= t regmap *regmap, const struct spacemit_ccu_clk *clk; int i, ret, max_id =3D 0; =20 + /* Clocks are optional */ + if (!clks) + return 0; + for (clk =3D clks; clk->hw; clk++) max_id =3D max(max_id, clk->id); =20 @@ -1903,7 +1907,7 @@ static int k1_ccu_probe(struct platform_device *pdev) int ret; =20 data =3D of_device_get_match_data(dev); - if (!data) + if (!data || !(data->clk || data->rst_data)) return -EINVAL; =20 base_regmap =3D device_node_to_regmap(dev->of_node); --=20 2.43.0 From nobody Wed Dec 17 08:56:01 2025 Received: from mail-io1-f47.google.com (mail-io1-f47.google.com [209.85.166.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05AFD22CBD9 for ; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-85e2bd8c40fsm8341439f.32.2025.03.20.12.45.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Mar 2025 12:45:02 -0700 (PDT) From: Alex Elder To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heylenay@4d2.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] clk: spacemit: define new syscons with only resets Date: Thu, 20 Mar 2025 14:44:47 -0500 Message-ID: <20250320194449.510569-7-elder@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250320194449.510569-1-elder@riscstar.com> References: <20250320194449.510569-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable support for three additional syscon CCUs which support reset controls but no clocks: ARCPU, RCPU2, and APBC2. Signed-off-by: Alex Elder --- drivers/clk/spacemit/ccu-k1.c | 106 ++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 17e321c25959a..bf5a3e2048619 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -130,6 +130,37 @@ #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 #define APMU_EMAC1_CLK_RES_CTRL 0x3ec =20 +/* RCPU register offsets */ +#define RCPU_SSP0_CLK_RST 0x0028 +#define RCPU_I2C0_CLK_RST 0x0030 +#define RCPU_UART1_CLK_RST 0x003c +#define RCPU_CAN_CLK_RST 0x0048 +#define RCPU_IR_CLK_RST 0x004c +#define RCPU_UART0_CLK_RST 0x00d8 +/* XXX Next one is part of the AUD_AUDCLOCK region @ 0xc0882000 */ +#define AUDIO_HDMI_CLK_CTRL 0x2044 + +/* RCPU2 register offsets */ +#define RCPU2_PWM0_CLK_RST 0x0000 +#define RCPU2_PWM1_CLK_RST 0x0004 +#define RCPU2_PWM2_CLK_RST 0x0008 +#define RCPU2_PWM3_CLK_RST 0x000c +#define RCPU2_PWM4_CLK_RST 0x0010 +#define RCPU2_PWM5_CLK_RST 0x0014 +#define RCPU2_PWM6_CLK_RST 0x0018 +#define RCPU2_PWM7_CLK_RST 0x001c +#define RCPU2_PWM8_CLK_RST 0x0020 +#define RCPU2_PWM9_CLK_RST 0x0024 + +/* APBC2 register offsets */ +#define APBC2_UART1_CLK_RST 0x0000 +#define APBC2_SSP2_CLK_RST 0x0004 +#define APBC2_TWSI3_CLK_RST 0x0008 +#define APBC2_RTC_CLK_RST 0x000c +#define APBC2_TIMERS0_CLK_RST 0x0010 +#define APBC2_KPC_CLK_RST 0x0014 +#define APBC2_GPIO_CLK_RST 0x001c + struct spacemit_ccu_clk { int id; struct clk_hw *hw; @@ -1781,6 +1812,69 @@ static const struct k1_ccu_data k1_ccu_apmu_data =3D= { .rst_data =3D &apmu_reset_controller_data, }; =20 +static const struct ccu_reset_data rcpu_reset_data[] =3D { + [RST_RCPU_SSP0] =3D RST_DATA(RCPU_SSP0_CLK_RST, 0, BIT(0)), + [RST_RCPU_I2C0] =3D RST_DATA(RCPU_I2C0_CLK_RST, 0, BIT(0)), + [RST_RCPU_UART1] =3D RST_DATA(RCPU_UART1_CLK_RST, 0, BIT(0)), + [RST_RCPU_IR] =3D RST_DATA(RCPU_CAN_CLK_RST, 0, BIT(0)), + [RST_RCPU_CAN] =3D RST_DATA(RCPU_IR_CLK_RST, 0, BIT(0)), + [RST_RCPU_UART0] =3D RST_DATA(RCPU_UART0_CLK_RST, 0, BIT(0)), + [RST_RCPU_HDMI_AUDIO] =3D RST_DATA(AUDIO_HDMI_CLK_CTRL, 0, BIT(0)), +}; + +static const struct ccu_reset_controller_data rcpu_reset_controller_data = =3D { + .count =3D ARRAY_SIZE(rcpu_reset_data), + .data =3D rcpu_reset_data, +}; + +static struct k1_ccu_data k1_ccu_rcpu_data =3D { + /* No clocks in the RCPU CCU */ + .rst_data =3D &rcpu_reset_controller_data, +}; + +static const struct ccu_reset_data rcpu2_reset_data[] =3D { + [RST_RCPU2_PWM0] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM1] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM2] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM3] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM4] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM5] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM6] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM7] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM8] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM9] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), +}; + +static const struct ccu_reset_controller_data rcpu2_reset_controller_data = =3D { + .count =3D ARRAY_SIZE(rcpu2_reset_data), + .data =3D rcpu2_reset_data, +}; + +static struct k1_ccu_data k1_ccu_rcpu2_data =3D { + /* No clocks in the RCPU2 CCU */ + .rst_data =3D &rcpu2_reset_controller_data, +}; + +static const struct ccu_reset_data apbc2_reset_data[] =3D { + [RST_APBC2_UART1] =3D RST_DATA(APBC2_UART1_CLK_RST, BIT(2), (0)), + [RST_APBC2_SSP2] =3D RST_DATA(APBC2_SSP2_CLK_RST, BIT(2), (0)), + [RST_APBC2_TWSI3] =3D RST_DATA(APBC2_TWSI3_CLK_RST, BIT(2), (0)), + [RST_APBC2_RTC] =3D RST_DATA(APBC2_RTC_CLK_RST, BIT(2), (0)), + [RST_APBC2_TIMERS0] =3D RST_DATA(APBC2_TIMERS0_CLK_RST, BIT(2), (0)), + [RST_APBC2_KPC] =3D RST_DATA(APBC2_KPC_CLK_RST, BIT(2), (0)), + [RST_APBC2_GPIO] =3D RST_DATA(APBC2_GPIO_CLK_RST, BIT(2), (0)), +}; + +static const struct ccu_reset_controller_data apbc2_reset_controller_data = =3D { + .count =3D ARRAY_SIZE(apbc2_reset_data), + .data =3D apbc2_reset_data, +}; + +static struct k1_ccu_data k1_ccu_apbc2_data =3D { + /* No clocks in the RCPU2 CCU */ + .rst_data =3D &apbc2_reset_controller_data, +}; + static struct ccu_reset_controller * rcdev_to_controller(struct reset_controller_dev *rcdev) { @@ -1959,6 +2053,18 @@ static const struct of_device_id of_k1_ccu_match[] = =3D { .compatible =3D "spacemit,k1-syscon-apmu", .data =3D &k1_ccu_apmu_data, }, + { + .compatible =3D "spacemit,k1-syscon-rcpu", + .data =3D &k1_ccu_rcpu_data, + }, + { + .compatible =3D "spacemit,k1-syscon-rcpu2", + .data =3D &k1_ccu_rcpu2_data, + }, + { + .compatible =3D "spacemit,k1-syscon-apbc2", + .data =3D &k1_ccu_apbc2_data, + }, { } }; MODULE_DEVICE_TABLE(of, of_k1_ccu_match); --=20 2.43.0 From nobody Wed Dec 17 08:56:01 2025 Received: from mail-io1-f42.google.com (mail-io1-f42.google.com [209.85.166.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 626FF22CBFD for ; Thu, 20 Mar 2025 19:45:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.42 ARC-Seal: i=1; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-85e2bd8c40fsm8341439f.32.2025.03.20.12.45.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Mar 2025 12:45:04 -0700 (PDT) From: Alex Elder To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] riscv: dts: spacemit: add reset support for the K1 SoC Date: Thu, 20 Mar 2025 14:44:48 -0500 Message-ID: <20250320194449.510569-8-elder@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250320194449.510569-1-elder@riscstar.com> References: <20250320194449.510569-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define syscon nodes for the RCPU, RCPU2, and APBC2 SpacemiT CCUS, which currently support resets but not clocks in the SpacemiT K1. Signed-off-by: Alex Elder --- arch/riscv/boot/dts/spacemit/k1.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index 09a9100986b19..f86d1b58c6d35 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -350,6 +350,18 @@ soc { dma-noncoherent; ranges; =20 + syscon_rcpu: system-controller@c0880000 { + compatible =3D "spacemit,k1-syscon-rcpu"; + reg =3D <0x0 0xc0880000 0x0 0x2048>; + #reset-cells =3D <1>; + }; + + syscon_rcpu2: system-controller@c0888000 { + compatible =3D "spacemit,k1-syscon-rcpu2"; + reg =3D <0x0 0xc0888000 0x0 0x28>; + #reset-cells =3D <1>; + }; + syscon_apbc: system-control@d4015000 { compatible =3D "spacemit,k1-syscon-apbc"; reg =3D <0x0 0xd4015000 0x0 0x1000>; @@ -518,6 +530,12 @@ clint: timer@e4000000 { <&cpu7_intc 3>, <&cpu7_intc 7>; }; =20 + syscon_apbc2: system-controller@f0610000 { + compatible =3D "spacemit,k1-syscon-apbc2"; + reg =3D <0x0 0xf0610000 0x0 0x20>; + #reset-cells =3D <1>; + }; + sec_uart1: serial@f0612000 { compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; reg =3D <0x0 0xf0612000 0x0 0x100>; --=20 2.43.0