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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Mar 2025 11:18:07.5137 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac9c9133-ebc2-445e-9154-08dd67a0e41b X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF00000195.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB7795 Content-Type: text/plain; charset="utf-8" This patch updates Panthor to use the new 64-bit accessors and poll functions. Signed-off-by: Karunika Choo --- drivers/gpu/drm/panthor/panthor_fw.c | 9 +- drivers/gpu/drm/panthor/panthor_gpu.c | 142 +++++++------------------- drivers/gpu/drm/panthor/panthor_mmu.c | 34 ++---- 3 files changed, 53 insertions(+), 132 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor= /panthor_fw.c index 0f52766a3120..ecfbe0456f89 100644 --- a/drivers/gpu/drm/panthor/panthor_fw.c +++ b/drivers/gpu/drm/panthor/panthor_fw.c @@ -1059,8 +1059,8 @@ static void panthor_fw_stop(struct panthor_device *pt= dev) u32 status; =20 gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_DISABLE); - if (readl_poll_timeout(ptdev->iomem + MCU_STATUS, status, - status =3D=3D MCU_STATUS_DISABLED, 10, 100000)) + if (gpu_read_poll_timeout(ptdev, MCU_STATUS, status, + status =3D=3D MCU_STATUS_DISABLED, 10, 100000)) drm_err(&ptdev->base, "Failed to stop MCU"); } =20 @@ -1085,8 +1085,9 @@ void panthor_fw_pre_reset(struct panthor_device *ptde= v, bool on_hang) =20 panthor_fw_update_reqs(glb_iface, req, GLB_HALT, GLB_HALT); gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); - if (!readl_poll_timeout(ptdev->iomem + MCU_STATUS, status, - status =3D=3D MCU_STATUS_HALT, 10, 100000)) { + if (!gpu_read_poll_timeout(ptdev, MCU_STATUS, status, + status =3D=3D MCU_STATUS_HALT, 10, + 100000)) { ptdev->reset.fast =3D true; } else { drm_warn(&ptdev->base, "Failed to cleanly suspend MCU"); diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/pantho= r/panthor_gpu.c index 671049020afa..0dee011fe2e9 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.c +++ b/drivers/gpu/drm/panthor/panthor_gpu.c @@ -108,14 +108,9 @@ static void panthor_gpu_init_info(struct panthor_devic= e *ptdev) =20 ptdev->gpu_info.as_present =3D gpu_read(ptdev, GPU_AS_PRESENT); =20 - ptdev->gpu_info.shader_present =3D gpu_read(ptdev, GPU_SHADER_PRESENT_LO); - ptdev->gpu_info.shader_present |=3D (u64)gpu_read(ptdev, GPU_SHADER_PRESE= NT_HI) << 32; - - ptdev->gpu_info.tiler_present =3D gpu_read(ptdev, GPU_TILER_PRESENT_LO); - ptdev->gpu_info.tiler_present |=3D (u64)gpu_read(ptdev, GPU_TILER_PRESENT= _HI) << 32; - - ptdev->gpu_info.l2_present =3D gpu_read(ptdev, GPU_L2_PRESENT_LO); - ptdev->gpu_info.l2_present |=3D (u64)gpu_read(ptdev, GPU_L2_PRESENT_HI) <= < 32; + ptdev->gpu_info.shader_present =3D gpu_read64(ptdev, GPU_SHADER_PRESENT_L= O); + ptdev->gpu_info.tiler_present =3D gpu_read64(ptdev, GPU_TILER_PRESENT_LO); + ptdev->gpu_info.l2_present =3D gpu_read64(ptdev, GPU_L2_PRESENT_LO); =20 arch_major =3D GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id); product_major =3D GPU_PROD_MAJOR(ptdev->gpu_info.gpu_id); @@ -152,8 +147,7 @@ static void panthor_gpu_irq_handler(struct panthor_devi= ce *ptdev, u32 status) { if (status & GPU_IRQ_FAULT) { u32 fault_status =3D gpu_read(ptdev, GPU_FAULT_STATUS); - u64 address =3D ((u64)gpu_read(ptdev, GPU_FAULT_ADDR_HI) << 32) | - gpu_read(ptdev, GPU_FAULT_ADDR_LO); + u64 address =3D gpu_read64(ptdev, GPU_FAULT_ADDR_LO); =20 drm_warn(&ptdev->base, "GPU Fault 0x%08x (%s) at 0x%016llx\n", fault_status, panthor_exception_name(ptdev, fault_status & 0xFF), @@ -244,45 +238,27 @@ int panthor_gpu_block_power_off(struct panthor_device= *ptdev, u32 pwroff_reg, u32 pwrtrans_reg, u64 mask, u32 timeout_us) { - u32 val, i; + u32 val; int ret; =20 - for (i =3D 0; i < 2; i++) { - u32 mask32 =3D mask >> (i * 32); - - if (!mask32) - continue; - - ret =3D readl_relaxed_poll_timeout(ptdev->iomem + pwrtrans_reg + (i * 4), - val, !(mask32 & val), - 100, timeout_us); - if (ret) { - drm_err(&ptdev->base, "timeout waiting on %s:%llx power transition", - blk_name, mask); - return ret; - } + ret =3D gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val, !val, + 100, timeout_us); + if (ret) { + drm_err(&ptdev->base, + "timeout waiting on %s:%llx power transition", blk_name, + mask); + return ret; } =20 - if (mask & GENMASK(31, 0)) - gpu_write(ptdev, pwroff_reg, mask); - - if (mask >> 32) - gpu_write(ptdev, pwroff_reg + 4, mask >> 32); - - for (i =3D 0; i < 2; i++) { - u32 mask32 =3D mask >> (i * 32); + gpu_write64(ptdev, pwroff_reg, mask); =20 - if (!mask32) - continue; - - ret =3D readl_relaxed_poll_timeout(ptdev->iomem + pwrtrans_reg + (i * 4), - val, !(mask32 & val), - 100, timeout_us); - if (ret) { - drm_err(&ptdev->base, "timeout waiting on %s:%llx power transition", - blk_name, mask); - return ret; - } + ret =3D gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val, !val, + 100, timeout_us); + if (ret) { + drm_err(&ptdev->base, + "timeout waiting on %s:%llx power transition", blk_name, + mask); + return ret; } =20 return 0; @@ -305,45 +281,26 @@ int panthor_gpu_block_power_on(struct panthor_device = *ptdev, u32 pwron_reg, u32 pwrtrans_reg, u32 rdy_reg, u64 mask, u32 timeout_us) { - u32 val, i; + u32 val; int ret; =20 - for (i =3D 0; i < 2; i++) { - u32 mask32 =3D mask >> (i * 32); - - if (!mask32) - continue; - - ret =3D readl_relaxed_poll_timeout(ptdev->iomem + pwrtrans_reg + (i * 4), - val, !(mask32 & val), - 100, timeout_us); - if (ret) { - drm_err(&ptdev->base, "timeout waiting on %s:%llx power transition", - blk_name, mask); - return ret; - } + ret =3D gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val, !val, + 100, timeout_us); + if (ret) { + drm_err(&ptdev->base, + "timeout waiting on %s:%llx power transition", blk_name, + mask); + return ret; } =20 - if (mask & GENMASK(31, 0)) - gpu_write(ptdev, pwron_reg, mask); - - if (mask >> 32) - gpu_write(ptdev, pwron_reg + 4, mask >> 32); - - for (i =3D 0; i < 2; i++) { - u32 mask32 =3D mask >> (i * 32); + gpu_write64(ptdev, pwron_reg, mask); =20 - if (!mask32) - continue; - - ret =3D readl_relaxed_poll_timeout(ptdev->iomem + rdy_reg + (i * 4), - val, (mask32 & val) =3D=3D mask32, - 100, timeout_us); - if (ret) { - drm_err(&ptdev->base, "timeout waiting on %s:%llx readiness", - blk_name, mask); - return ret; - } + ret =3D gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val, !val, + 100, timeout_us); + if (ret) { + drm_err(&ptdev->base, "timeout waiting on %s:%llx readiness", + blk_name, mask); + return ret; } =20 return 0; @@ -492,26 +449,6 @@ void panthor_gpu_resume(struct panthor_device *ptdev) panthor_gpu_l2_power_on(ptdev); } =20 -/** - * panthor_gpu_read_64bit_counter() - Read a 64-bit counter at a given off= set. - * @ptdev: Device. - * @reg: The offset of the register to read. - * - * Return: The counter value. - */ -static u64 -panthor_gpu_read_64bit_counter(struct panthor_device *ptdev, u32 reg) -{ - u32 hi, lo; - - do { - hi =3D gpu_read(ptdev, reg + 0x4); - lo =3D gpu_read(ptdev, reg); - } while (hi !=3D gpu_read(ptdev, reg + 0x4)); - - return ((u64)hi << 32) | lo; -} - /** * panthor_gpu_read_timestamp() - Read the timestamp register. * @ptdev: Device. @@ -520,7 +457,7 @@ panthor_gpu_read_64bit_counter(struct panthor_device *p= tdev, u32 reg) */ u64 panthor_gpu_read_timestamp(struct panthor_device *ptdev) { - return panthor_gpu_read_64bit_counter(ptdev, GPU_TIMESTAMP_LO); + return gpu_read64_sync(ptdev, GPU_TIMESTAMP_LO); } =20 /** @@ -531,10 +468,5 @@ u64 panthor_gpu_read_timestamp(struct panthor_device *= ptdev) */ u64 panthor_gpu_read_timestamp_offset(struct panthor_device *ptdev) { - u32 hi, lo; - - hi =3D gpu_read(ptdev, GPU_TIMESTAMP_OFFSET_HI); - lo =3D gpu_read(ptdev, GPU_TIMESTAMP_OFFSET_LO); - - return ((u64)hi << 32) | lo; + return gpu_read64(ptdev, GPU_TIMESTAMP_OFFSET_LO); } diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c b/drivers/gpu/drm/pantho= r/panthor_mmu.c index 12a02e28f50f..a0a79f19bdea 100644 --- a/drivers/gpu/drm/panthor/panthor_mmu.c +++ b/drivers/gpu/drm/panthor/panthor_mmu.c @@ -510,9 +510,9 @@ static int wait_ready(struct panthor_device *ptdev, u32= as_nr) /* Wait for the MMU status to indicate there is no active command, in * case one is pending. */ - ret =3D readl_relaxed_poll_timeout_atomic(ptdev->iomem + AS_STATUS(as_nr), - val, !(val & AS_STATUS_AS_ACTIVE), - 10, 100000); + ret =3D gpu_read_relaxed_poll_timeout_atomic(ptdev, AS_STATUS(as_nr), val, + !(val & AS_STATUS_AS_ACTIVE), + 10, 100000); =20 if (ret) { panthor_device_schedule_reset(ptdev); @@ -564,8 +564,7 @@ static void lock_region(struct panthor_device *ptdev, u= 32 as_nr, region =3D region_width | region_start; =20 /* Lock the region that needs to be updated */ - gpu_write(ptdev, AS_LOCKADDR_LO(as_nr), lower_32_bits(region)); - gpu_write(ptdev, AS_LOCKADDR_HI(as_nr), upper_32_bits(region)); + gpu_write64(ptdev, AS_LOCKADDR_LO(as_nr), region); write_cmd(ptdev, as_nr, AS_COMMAND_LOCK); } =20 @@ -615,14 +614,9 @@ static int panthor_mmu_as_enable(struct panthor_device= *ptdev, u32 as_nr, if (ret) return ret; =20 - gpu_write(ptdev, AS_TRANSTAB_LO(as_nr), lower_32_bits(transtab)); - gpu_write(ptdev, AS_TRANSTAB_HI(as_nr), upper_32_bits(transtab)); - - gpu_write(ptdev, AS_MEMATTR_LO(as_nr), lower_32_bits(memattr)); - gpu_write(ptdev, AS_MEMATTR_HI(as_nr), upper_32_bits(memattr)); - - gpu_write(ptdev, AS_TRANSCFG_LO(as_nr), lower_32_bits(transcfg)); - gpu_write(ptdev, AS_TRANSCFG_HI(as_nr), upper_32_bits(transcfg)); + gpu_write64(ptdev, AS_TRANSTAB_LO(as_nr), transtab); + gpu_write64(ptdev, AS_MEMATTR_LO(as_nr), memattr); + gpu_write64(ptdev, AS_TRANSCFG_LO(as_nr), transcfg); =20 return write_cmd(ptdev, as_nr, AS_COMMAND_UPDATE); } @@ -635,14 +629,9 @@ static int panthor_mmu_as_disable(struct panthor_devic= e *ptdev, u32 as_nr) if (ret) return ret; =20 - gpu_write(ptdev, AS_TRANSTAB_LO(as_nr), 0); - gpu_write(ptdev, AS_TRANSTAB_HI(as_nr), 0); - - gpu_write(ptdev, AS_MEMATTR_LO(as_nr), 0); - gpu_write(ptdev, AS_MEMATTR_HI(as_nr), 0); - - gpu_write(ptdev, AS_TRANSCFG_LO(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED); - gpu_write(ptdev, AS_TRANSCFG_HI(as_nr), 0); + gpu_write64(ptdev, AS_TRANSTAB_LO(as_nr), 0); + gpu_write64(ptdev, AS_MEMATTR_LO(as_nr), 0); + gpu_write64(ptdev, AS_TRANSCFG_LO(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED); =20 return write_cmd(ptdev, as_nr, AS_COMMAND_UPDATE); } @@ -1680,8 +1669,7 @@ static void panthor_mmu_irq_handler(struct panthor_de= vice *ptdev, u32 status) u32 source_id; =20 fault_status =3D gpu_read(ptdev, AS_FAULTSTATUS(as)); - addr =3D gpu_read(ptdev, AS_FAULTADDRESS_LO(as)); - addr |=3D (u64)gpu_read(ptdev, AS_FAULTADDRESS_HI(as)) << 32; + addr =3D gpu_read64(ptdev, AS_FAULTADDRESS_LO(as)); =20 /* decode the fault status */ exception_type =3D fault_status & 0xFF; --=20 2.47.1