From nobody Tue Feb 10 00:01:36 2026 Received: from naesa04.arrow.com (naesa04.arrow.com [216.150.161.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 291242080D9; Thu, 20 Mar 2025 10:54:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.150.161.24 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742468101; cv=none; b=f209xR0eDMwLg8ycg8KtsAJ+0fh3pYOUghgeAS2iVRTT+KKriPlRYtiVZo0fcthN0ZoIEb4eC1pnKD8YRBsnU6YHybAQMaCS0tw03SOfnfs8c5hHZZPUpkpoEhriq5bjNiF7pYNmKaXo1qs4cekDC1v2kbCWmqVBhy7197ESRWM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742468101; c=relaxed/simple; bh=H3wnlGqXSSS/oiZRRPE2KJNofPHwThcoVMkEwdUNQ7I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Iv7jR2mlFnTQ9TVmY4vAZNHIh+ffi6uJb6Bm3IPBGPDHl/icHpBO07W5B/jI70Omx6OVPy5onT42BUc16Mlz69JGUnfIjtRGyt+XwNitUWkhL9YI/njmMRKPwN1QGL20C835xzJX1mNW0QnzTG4Q+X3glYY2JUy8iTUxqAE29xU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com; spf=pass smtp.mailfrom=einfochips.com; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b=sgealLsZ; arc=none smtp.client-ip=216.150.161.24 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=einfochips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b="sgealLsZ" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=einfochips.com; i=@einfochips.com; l=2708; q=dns/txt; s=NAESA-Selector1; t=1742468099; x=1774004099; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=H3wnlGqXSSS/oiZRRPE2KJNofPHwThcoVMkEwdUNQ7I=; b=sgealLsZ0kzhVyd4DTkeiERkjmZ/JLSA/4PxowSsJMHSYu+irXWKOCyh IGlMW/Ij/e65ZknKrL2+p+jRaiMT2rpEvR0LfNXYDpGIMpdQd0DzVJm9T idw1FF3tRLjEv2rhM6lO8iHGFJyhJcO1AvCNPRAOZ+XNwpIQP91ZK9Kxa 7j/qbOnWgMqR3r/0JnOxdlKGF7GzTOtMv7jxuiVKFPuO0JP3fq2l0f+wy pz56xb+IOGXn6XVMED2w4Nr2AY4Qyt9LRBsNNRiA4O7nHhaVHn1anZA8Y xE61Kk72+5e1Id4dc6QRooK8jEjH5VYYT8fBHZ9O97w2mQHVbQIK41Qkn w==; X-CSE-ConnectionGUID: JOlNPfBESO+lmtvRbbIzyA== X-CSE-MsgGUID: m3A5hBjFRaCAlw9BfkjPpw== X-IronPort-AV: E=Sophos;i="6.14,261,1736838000"; d="scan'208";a="80263111" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa04out.arrow.com with ESMTP; 20 Mar 2025 04:54:57 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.14393.4169); Thu, 20 Mar 2025 16:24:49 +0530 From: Pinkesh Vaghela To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner Cc: Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Min Lin , Pinkesh Vaghela , Pritesh Patel , Yangyu Chen , Lad Prabhakar , Yu Chien Peter Lin , Charlie Jenkins , Kanak Shilledar , Darshan Prajapati , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , rafal@milecki.pl, Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 05/10] dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility Date: Thu, 20 Mar 2025 16:24:44 +0530 Message-Id: <20250320105449.2094192-6-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> References: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 20 Mar 2025 10:54:49.0944 (UTC) FILETIME=[80946D80:01DB9986] Content-Type: text/plain; charset="utf-8" From: Pritesh Patel This cache controller is also used on the ESWIN EIC7700 SoC. However, it have 256KB private L2 Cache and shared L3 Cache of 4MB. So add dedicated compatible string for it. Signed-off-by: Pritesh Patel Reviewed-by: Samuel Holland Signed-off-by: Pinkesh Vaghela --- .../bindings/cache/sifive,ccache0.yaml | 44 +++++++++++++++++-- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/= Documentation/devicetree/bindings/cache/sifive,ccache0.yaml index 7e8cebe21584..579bacb66f34 100644 --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml @@ -39,6 +39,7 @@ properties: - const: cache - items: - enum: + - eswin,eic7700-l3-cache - starfive,jh7100-ccache - starfive,jh7110-ccache - const: sifive,ccache0 @@ -55,10 +56,10 @@ properties: enum: [2, 3] =20 cache-sets: - enum: [1024, 2048] + enum: [1024, 2048, 4096] =20 cache-size: - const: 2097152 + enum: [2097152, 4194304] =20 cache-unified: true =20 @@ -89,6 +90,7 @@ allOf: compatible: contains: enum: + - eswin,eic7700-l3-cache - sifive,fu740-c000-ccache - starfive,jh7100-ccache - starfive,jh7110-ccache @@ -108,6 +110,22 @@ allOf: Must contain entries for DirError, DataError and DataFail sign= als. maxItems: 3 =20 + - if: + properties: + compatible: + contains: + const: eswin,eic7700-l3-cache + + then: + properties: + cache-size: + const: 4194304 + + else: + properties: + cache-size: + const: 2097152 + - if: properties: compatible: @@ -122,11 +140,31 @@ allOf: cache-sets: const: 2048 =20 - else: + - if: + properties: + compatible: + contains: + enum: + - microchip,mpfs-ccache + - sifive,fu540-c000-ccache + + then: properties: cache-sets: const: 1024 =20 + - if: + properties: + compatible: + contains: + enum: + - eswin,eic7700-l3-cache + + then: + properties: + cache-sets: + const: 4096 + - if: properties: compatible: --=20 2.25.1