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Thu, 20 Mar 2025 01:44:57 -0700 (PDT) From: Yunhui Cui To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, anshuman.khandual@arm.com, akpm@linux-foundation.org, mingo@kernel.org, cuiyunhui@bytedance.com, catalin.marinas@arm.com, ryan.roberts@arm.com, kirill.shutemov@linux.intel.com, namcao@linutronix.de, bjorn@rivosinc.com, arnd@arndb.de, stuart.menefy@codasip.com, luxu.kernel@bytedance.com, vincenzo.frascino@arm.com, samuel.holland@sifive.com, christophe.leroy@csgroup.eu, dawei.li@shingroup.cn, rppt@kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] riscv: introduce the ioremap_prot() function Date: Thu, 20 Mar 2025 16:44:28 +0800 Message-Id: <20250320084428.51151-1-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It's advisable to avoid mapping memory with the non-cache attribute. This is because issues may arise when the same physical address is mapped as both cacheable and non-cacheable simultaneously, such as in the case of hardware prefetching. Signed-off-by: Yunhui Cui --- arch/riscv/include/asm/io.h | 2 ++ arch/riscv/include/asm/page.h | 2 ++ arch/riscv/mm/Makefile | 1 + arch/riscv/mm/init.c | 12 ++++++++++++ arch/riscv/mm/ioremap.c | 15 +++++++++++++++ 5 files changed, 32 insertions(+) create mode 100644 arch/riscv/mm/ioremap.c diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index a0e51840b9db..736c5557bd06 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -133,6 +133,8 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) #define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, co= unt) #endif =20 +#define ioremap_prot ioremap_prot + #include =20 #ifdef CONFIG_MMU diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h index 125f5ecd9565..181d2d3a0922 100644 --- a/arch/riscv/include/asm/page.h +++ b/arch/riscv/include/asm/page.h @@ -202,6 +202,8 @@ static __always_inline void *pfn_to_kaddr(unsigned long= pfn) return __va(pfn << PAGE_SHIFT); } =20 +int pfn_is_map_memory(unsigned long pfn); + #endif /* __ASSEMBLY__ */ =20 #define virt_addr_valid(vaddr) ({ \ diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index b916a68d324a..58a75f7d66e9 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_MMU) +=3D extable.o fault.o pageattr.o pgtab= le.o tlbflush.o obj-y +=3D cacheflush.o obj-y +=3D context.o obj-y +=3D pmem.o +obj-y +=3D ioremap.o =20 obj-$(CONFIG_HUGETLB_PAGE) +=3D hugetlbpage.o obj-$(CONFIG_PTDUMP) +=3D ptdump.o diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 3ec9bfaa088a..74ad96e973a4 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -92,6 +92,18 @@ static void __init zone_sizes_init(void) free_area_init(max_zone_pfns); } =20 +int pfn_is_map_memory(unsigned long pfn) +{ + phys_addr_t addr =3D PFN_PHYS(pfn); + + /* avoid false positives for bogus PFNs, see comment in pfn_valid() */ + if (PHYS_PFN(addr) !=3D pfn) + return 0; + + return memblock_is_map_memory(addr); +} +EXPORT_SYMBOL(pfn_is_map_memory); + #if defined(CONFIG_MMU) && defined(CONFIG_DEBUG_VM) =20 #define LOG2_SZ_1K ilog2(SZ_1K) diff --git a/arch/riscv/mm/ioremap.c b/arch/riscv/mm/ioremap.c new file mode 100644 index 000000000000..037f87dfe88d --- /dev/null +++ b/arch/riscv/mm/ioremap.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include + +void __iomem *ioremap_prot(phys_addr_t phys_addr, size_t size, + pgprot_t pgprot) +{ + /* Don't allow RAM to be mapped. */ + if (WARN_ON(pfn_is_map_memory(__phys_to_pfn(phys_addr)))) + return NULL; + + return generic_ioremap_prot(phys_addr, size, pgprot); +} +EXPORT_SYMBOL(ioremap_prot); --=20 2.39.2