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The device consists of 3 buck regulators able to connect to high input voltages of up to 18V with no preregulators. Signed-off-by: Alexis Czezar Torreno --- .../bindings/regulator/adi,adp5055-regulator.yaml | 161 +++++++++++++++++= ++++ MAINTAINERS | 6 + 2 files changed, 167 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/adi,adp5055-regula= tor.yaml b/Documentation/devicetree/bindings/regulator/adi,adp5055-regulato= r.yaml new file mode 100644 index 0000000000000000000000000000000000000000..fc8f1e61ba321f8b4c6f8c1e3d0= e91d570fb4953 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/adi,adp5055-regulator.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/adi,adp5055-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADP5055 Triple Buck Regulator + +maintainers: + - Alexis Czezar Torreno + +description: | + The ADP5055 combines three high performance buck regulators. + The device enables direct connection to high input voltages + up to 18 V with no preregulators. + https://www.analog.com/media/en/technical-documentation/data-sheets/adp5= 055.pdf + +properties: + compatible: + enum: + - adi,adp5055 + + reg: + enum: + - 0x70 + - 0x71 + + adi,tset-us: + description: + Setting time used by the device. This is changed via soldering + specific resistor values on the CFG2 pin. + enum: [2600, 20800] + default: 2600 + + adi,hw-en-array-gpios: + description: + Asserted during driver probe. Each array entry acts as the + hardware enable for channels 0-2. Should be marked 0 for active + low. Requires all three channels to be initialized. Not adding + the property turns the system to a software only enable mode. + minItems: 3 + maxItems: 3 + + adi,ocp-blanking: + description: + If present, the over current protection + blanking (OCP) for all channels is on. + type: boolean + + adi,delay-power-good: + description: + Configures delay timer of the power good (PWRGD) pin. + Delay is based on Tset which can be 2.6 ms or 20.8 ms. + type: boolean + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^channel@([0-2])$": + type: object + additionalProperties: false + + properties: + reg: + description: The channel number representing each buck converter. + maximum: 2 + + adi,dvs-limit-upper-microvolt: + description: + Configure the allowable upper side limit of the + voltage output of each channel in microvolt. + Voltages are in 12mV steps, value is autoadjusted. + Vout_high =3D Vout + DVS_upper_limit. + minimum: 12000 + maximum: 192000 + default: 192000 + + adi,dvs-limit-lower-microvolt: + description: + Configure the allowable lower side limit of the + voltage output of each channel in microvolt. + Voltages are in 12mV steps, value is autoadjusted. + Vout_low =3D Vout + DVS_lower_limit. + minimum: -190500 + maximum: -10500 + default: -190500 + + adi,fast-transient: + description: + Configures the fast transient sensitivity for each channel. + "none" - No fast transient. + "3G_1.5%" - 1.5% window with 3*350uA/V + "5G_1.5%" - 1.5% window with 5*350uA/V + "5G_2.5%" - 2.5% window with 5*350uA/V + enum: [none, 3G_1.5%, 5G_1.5%, 5G_2.5%] + default: 5G_2.5% + + adi,mask-power-good: + description: + If present, masks individual channels to the external + PWRGD hardware pin. + type: boolean + + required: + - regulator-name + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + regulator@70 { + compatible =3D "adi,adp5055"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + adi,tset-us =3D <2600>; + adi,hw-en-array-gpios =3D <&gpio 17 0>, + <&gpio 18 0>, + <&gpio 19 0>; + + adi,ocp-blanking; + adi,delay-power-good; + + DCDC0 { + regulator-name =3D "DCDC0"; + adi,dvs-limit-upper-microvolt =3D <192000>; + adi,dvs-limit-lower-microvolt =3D <(-190500)>; + adi,fast-transient =3D "5G_2.5%"; + adi,mask-power-good; + }; + + DCDC1 { + regulator-name =3D "DCDC1"; + adi,dvs-limit-upper-microvolt =3D <192000>; + adi,dvs-limit-lower-microvolt =3D <(-190500)>; + adi,fast-transient =3D "5G_2.5%"; + adi,mask-power-good; + }; + + DCDC2 { + regulator-name =3D "DCDC2"; + adi,dvs-limit-upper-microvolt =3D <192000>; + adi,dvs-limit-lower-microvolt =3D <(-190500)>; + adi,fast-transient =3D "5G_2.5%"; + adi,mask-power-good; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 896a307fa06545e2861abe46ea7029f9b4d3628e..b2ec43f84d84765c319d8403fb5= 650afa273db83 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1525,6 +1525,12 @@ W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml F: drivers/iio/filter/admv8818.c =20 +ANALOG DEVICES INC ADP5055 DRIVER +M: Alexis Czezar Torreno +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/regulator/adi,adp5055-regulator.yaml + ANALOG DEVICES INC ADP5061 DRIVER M: Michael Hennerich L: linux-pm@vger.kernel.org --=20 2.34.1 From nobody Wed Dec 17 08:56:20 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DF261EE034; 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The device consists of 3 buck regulators able to connect to high input voltages of up to 18V with no preregulators. Signed-off-by: Alexis Czezar Torreno --- MAINTAINERS | 1 + drivers/regulator/Kconfig | 11 + drivers/regulator/Makefile | 1 + drivers/regulator/adp5055-regulator.c | 480 ++++++++++++++++++++++++++++++= ++++ 4 files changed, 493 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b2ec43f84d84765c319d8403fb5650afa273db83..7ac35d895b4c8297c6de70cd2bf= aec516ff5b100 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1530,6 +1530,7 @@ M: Alexis Czezar Torreno S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/regulator/adi,adp5055-regulator.yaml +F: drivers/regulator/adp5055-regulator.c =20 ANALOG DEVICES INC ADP5061 DRIVER M: Michael Hennerich diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 39297f7d8177193e51c99bc2b360c6d9936e62fe..4c08cf755d88e5f5bc6431192fa= d5f27786caea8 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -122,6 +122,17 @@ config REGULATOR_AD5398 This driver supports AD5398 and AD5821 current regulator chips. If building into module, its name is ad5398.ko. =20 +config REGULATOR_ADP5055 + tristate "Analog Devices ADP5055 Triple Buck Regulator" + depends on I2C + select REGMAP_I2C + help + This driver controls an Analog Devices ADP5055 with triple buck + regulators using an I2C interface. + + Say M here if you want to include support for the regulator as a + module. + config REGULATOR_ANATOP tristate "Freescale i.MX on-chip ANATOP LDO regulators" depends on ARCH_MXC || COMPILE_TEST diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 3d5a803dce8a0556ba9557fa069c6e37593b3c69..71f45d9317d24e7081ac919eb31= efff6652edf3f 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_REGULATOR_AB8500) +=3D ab8500-ext.o ab8500.o obj-$(CONFIG_REGULATOR_ACT8865) +=3D act8865-regulator.o obj-$(CONFIG_REGULATOR_ACT8945A) +=3D act8945a-regulator.o obj-$(CONFIG_REGULATOR_AD5398) +=3D ad5398.o +obj-$(CONFIG_REGULATOR_ADP5055) +=3D adp5055-regulator.o obj-$(CONFIG_REGULATOR_ANATOP) +=3D anatop-regulator.o obj-$(CONFIG_REGULATOR_ARIZONA_LDO1) +=3D arizona-ldo1.o obj-$(CONFIG_REGULATOR_ARIZONA_MICSUPP) +=3D arizona-micsupp.o diff --git a/drivers/regulator/adp5055-regulator.c b/drivers/regulator/adp5= 055-regulator.c new file mode 100644 index 0000000000000000000000000000000000000000..08c03a31e8e12afad57e87454bd= 18be3717e8739 --- /dev/null +++ b/drivers/regulator/adp5055-regulator.c @@ -0,0 +1,480 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Regulator driver for Analog Devices ADP5055 +// +// Copyright (C) 2025 Analog Devices, Inc. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// ADP5055 Register Map. + +#define ADP5055_CTRL123 0xD1 +#define ADP5055_CTRL_MODE1 0xD3 +#define ADP5055_CTRL_MODE2 0xD4 +#define ADP5055_DLY0 0xD5 +#define ADP5055_DLY1 0xD6 +#define ADP5055_DLY2 0xD7 +#define ADP5055_VID0 0xD8 +#define ADP5055_VID1 0xD9 +#define ADP5055_VID2 0xDA +#define ADP5055_DVS_LIM0 0xDC +#define ADP5055_DVS_LIM1 0xDD +#define ADP5055_DVS_LIM2 0xDE +#define ADP5055_FT_CFG 0xDF +#define ADP5055_PG_CFG 0xE0 + +// ADP5055 Field Masks. + +#define ADP5055_MASK_EN_MODE BIT(0) +#define ADP5055_MASK_OCP_BLANKING BIT(7) +#define ADP5055_MASK_PSM BIT(4) +#define ADP5055_MASK_DIS2 BIT(2) +#define ADP5055_MASK_DIS1 BIT(1) +#define ADP5055_MASK_DIS0 BIT(0) +#define ADP5055_MASK_DIS_DLY GENMASK(6, 4) +#define ADP5055_MASK_EN_DLY GENMASK(2, 0) +#define ADP5055_MASK_DVS_LIM_UPPER GENMASK(7, 4) +#define ADP5055_MASK_DVS_LIM_LOWER GENMASK(3, 0) +#define ADP5055_MASK_FAST_TRANSIENT2 GENMASK(5, 4) +#define ADP5055_MASK_FAST_TRANSIENT1 GENMASK(3, 2) +#define ADP5055_MASK_FAST_TRANSIENT0 GENMASK(1, 0) +#define ADP5055_MASK_DLY_PWRGD BIT(4) +#define ADP5055_MASK_PWRGD2 BIT(2) +#define ADP5055_MASK_PWRGD1 BIT(1) +#define ADP5055_MASK_PWRGD0 BIT(0) + +#define ADP5055_MIN_VOUT 408000 +#define ADP5055_NUM_CH 3 + +struct adp5055 { + struct regmap *regmap; + u32 tset; + struct gpio_descs *hw_en_array_gpios; + int dvs_limit_upper[ADP5055_NUM_CH]; + int dvs_limit_lower[ADP5055_NUM_CH]; + u32 fast_transient[ADP5055_NUM_CH]; + bool mask_power_good[ADP5055_NUM_CH]; +}; + +static const unsigned int adp5055_tset_vals[] =3D { + 2600, + 20800, +}; + +static const unsigned int adp5055_enable_delay_vals_2_6[] =3D { + 0, + 2600, + 5200, + 7800, + 10400, + 13000, + 15600, + 18200, +}; + +static const unsigned int adp5055_enable_delay_vals_20_8[] =3D { + 0, + 20800, + 41600, + 62400, + 83200, + 104000, + 124800, + 145600, +}; + +static const char * const adp5055_fast_transient_vals[] =3D { + "none", + "3G_1.5%", + "5G_1.5%", + "5G_2.5%", +}; + +static int adp5055_get_prop_index(const u32 *table, size_t table_size, + u32 value) +{ + int i; + + for (i =3D 0; i < table_size; i++) + if (table[i] =3D=3D value) + return i; + + return -EINVAL; +} + +static const struct regmap_range adp5055_reg_ranges[] =3D { + regmap_reg_range(0xD1, 0xE0), +}; + +static const struct regmap_access_table adp5055_access_ranges_table =3D { + .yes_ranges =3D adp5055_reg_ranges, + .n_yes_ranges =3D ARRAY_SIZE(adp5055_reg_ranges), +}; + +static const struct regmap_config adp5055_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D 0xE0, + .wr_table =3D &adp5055_access_ranges_table, + .rd_table =3D &adp5055_access_ranges_table, +}; + +static const struct linear_range adp5055_voltage_ranges[] =3D { + REGULATOR_LINEAR_RANGE(ADP5055_MIN_VOUT, 0, 255, 1500), +}; + +static int adp5055_parse_fw(struct device *dev, struct adp5055 *adp5055) +{ + int i, ret; + struct regmap *regmap =3D adp5055->regmap; + int val; + bool ocp_blanking; + bool delay_power_good; + + adp5055->tset =3D 2600; + + adp5055->hw_en_array_gpios =3D devm_gpiod_get_array_optional(dev, + "adi,hw-en-array", GPIOD_OUT_LOW); + if (IS_ERR(adp5055->hw_en_array_gpios)) + return dev_err_probe(dev, PTR_ERR(adp5055->hw_en_array_gpios), + "Failed to get hw_en_array GPIOs\n"); + + if (!adp5055->hw_en_array_gpios) + if (adp5055->hw_en_array_gpios->ndescs !=3D ADP5055_NUM_CH) + return dev_err_probe(dev, -EINVAL, + "Invalid amount of channels described\n"); + + ret =3D device_property_read_u32(dev, "adi,tset-us", &adp5055->tset); + if (!ret) { + ret =3D adp5055_get_prop_index(adp5055_tset_vals, + ARRAY_SIZE(adp5055_tset_vals), adp5055->tset); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to initialize tset."); + adp5055->tset =3D adp5055_tset_vals[ret]; + } + + ocp_blanking =3D device_property_read_bool(dev, "adi,ocp-blanking"); + + delay_power_good =3D device_property_read_bool(dev, + "adi,delay-power-good"); + + for (i =3D 0; i < ADP5055_NUM_CH; i++) { + val =3D FIELD_PREP(ADP5055_MASK_DVS_LIM_UPPER, + DIV_ROUND_CLOSEST_ULL(192000 - adp5055->dvs_limit_upper[i], 12000)); + val |=3D FIELD_PREP(ADP5055_MASK_DVS_LIM_LOWER, + DIV_ROUND_CLOSEST_ULL(adp5055->dvs_limit_lower[i] + 190500, 12000)); + ret =3D regmap_write(regmap, ADP5055_DVS_LIM0 + i, val); + if (ret) + return ret; + + i++; + }; + + if (!adp5055->hw_en_array_gpios) + val =3D FIELD_PREP(ADP5055_MASK_EN_MODE, 1); + else + val =3D FIELD_PREP(ADP5055_MASK_EN_MODE, 0); + ret =3D regmap_write(regmap, ADP5055_CTRL_MODE1, val); + if (ret) + return ret; + + val =3D FIELD_PREP(ADP5055_MASK_OCP_BLANKING, ocp_blanking); + ret =3D regmap_write(regmap, ADP5055_CTRL_MODE2, val); + if (ret) + return ret; + + val =3D FIELD_PREP(ADP5055_MASK_FAST_TRANSIENT2, adp5055->fast_transient[= 2]); + val |=3D FIELD_PREP(ADP5055_MASK_FAST_TRANSIENT1, adp5055->fast_transient= [1]); + val |=3D FIELD_PREP(ADP5055_MASK_FAST_TRANSIENT0, adp5055->fast_transient= [0]); + ret =3D regmap_write(regmap, ADP5055_FT_CFG, val); + if (ret) + return ret; + + val =3D FIELD_PREP(ADP5055_MASK_DLY_PWRGD, delay_power_good); + val |=3D FIELD_PREP(ADP5055_MASK_PWRGD2, adp5055->mask_power_good[2]); + val |=3D FIELD_PREP(ADP5055_MASK_PWRGD1, adp5055->mask_power_good[1]); + val |=3D FIELD_PREP(ADP5055_MASK_PWRGD0, adp5055->mask_power_good[0]); + ret =3D regmap_write(regmap, ADP5055_PG_CFG, val); + if (ret) + return ret; + + return 0; +} + +static int adp5055_of_parse_cb(struct device_node *np, + const struct regulator_desc *desc, + struct regulator_config *config) +{ + struct adp5055 *adp5055 =3D config->driver_data; + int id, ret, pval, i; + + id =3D desc->id; + + ret =3D of_property_read_u32(np, "adi,dvs-limit-upper-microvolt", &pval); + if (ret) + adp5055->dvs_limit_upper[id] =3D 192000; + else + adp5055->dvs_limit_upper[id] =3D pval; + + if (adp5055->dvs_limit_upper[id] > 192000 || adp5055->dvs_limit_upper[id]= < 12000) + return dev_err_probe(config->dev, adp5055->dvs_limit_upper[id], + "Out of range - dvs-limit-upper-microvolt value."); + + ret =3D of_property_read_u32(np, "adi,dvs-limit-lower-microvolt", &pval); + if (ret) + adp5055->dvs_limit_lower[id] =3D -190500; + else + adp5055->dvs_limit_lower[id] =3D pval; + + if (adp5055->dvs_limit_lower[id] > -10500 || adp5055->dvs_limit_lower[id]= < -190500) + return dev_err_probe(config->dev, adp5055->dvs_limit_lower[id], + "Out of range - dvs-limit-lower-microvolt value."); + + for (i =3D 0; i < 4; i++) { + ret =3D of_property_match_string(np, "adi,fast-transient", + adp5055_fast_transient_vals[i]); + if (!ret) + break; + } + + if (ret < 0) + adp5055->fast_transient[id] =3D 3; + else + adp5055->fast_transient[id] =3D i; + + ret =3D of_property_read_bool(np, "adi,mask-power-good"); + adp5055->mask_power_good[id] =3D ret; + + return 0; +} + +static int adp5055_is_enabled(struct regulator_dev *dev) +{ + struct adp5055 *adp5055 =3D rdev_get_drvdata(dev); + int id, ret; + int mask; + int val_sw, val_hw; + + id =3D rdev_get_id(dev); + mask =3D BIT(id); + ret =3D regmap_read(adp5055->regmap, ADP5055_CTRL123, &val_sw); + if (ret) + return ret; + + if (!adp5055->hw_en_array_gpios) + return (val_sw & mask) !=3D 0; + + val_hw =3D gpiod_get_value_cansleep(adp5055->hw_en_array_gpios->desc[id]); + + return val_hw; +}; + +static int adp5055_enable(struct regulator_dev *dev) +{ + struct adp5055 *adp5055 =3D rdev_get_drvdata(dev); + int id =3D rdev_get_id(dev); + + if (!adp5055->hw_en_array_gpios) + return regulator_enable_regmap(dev); + + gpiod_set_value_cansleep(adp5055->hw_en_array_gpios->desc[id], 1); + + return 0; +} + +static int adp5055_disable(struct regulator_dev *dev) +{ + struct adp5055 *adp5055 =3D rdev_get_drvdata(dev); + int id =3D rdev_get_id(dev); + + if (!adp5055->hw_en_array_gpios) + return regulator_disable_regmap(dev); + + gpiod_set_value_cansleep(adp5055->hw_en_array_gpios->desc[id], 0); + + return 0; +} + +static int adp5055_set_mode(struct regulator_dev *rdev, u32 mode) +{ + struct adp5055 *adp5055 =3D rdev_get_drvdata(rdev); + int id, ret; + + id =3D rdev_get_id(rdev); + + switch (mode) { + case REGULATOR_MODE_NORMAL: + ret =3D regmap_update_bits(adp5055->regmap, ADP5055_CTRL_MODE2, + ADP5055_MASK_PSM << id, 0); + break; + case REGULATOR_MODE_IDLE: + ret =3D regmap_update_bits(adp5055->regmap, ADP5055_CTRL_MODE2, + ADP5055_MASK_PSM << id, 1); + break; + default: + return dev_err_probe(&rdev->dev, -EINVAL, + "Unsupported mode: %d\n", mode); + } + + return ret; +} + +static unsigned int adp5055_get_mode(struct regulator_dev *rdev) +{ + struct adp5055 *adp5055 =3D rdev_get_drvdata(rdev); + int id, ret, regval; + + id =3D rdev_get_id(rdev); + + ret =3D regmap_read(adp5055->regmap, ADP5055_CTRL_MODE2, ®val); + if (ret) + return ret; + + if (regval & (ADP5055_MASK_PSM << id)) + return REGULATOR_MODE_IDLE; + else + return REGULATOR_MODE_NORMAL; +} + +static const struct regulator_ops adp5055_ops =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_active_discharge =3D regulator_set_active_discharge_regmap, + .enable =3D adp5055_enable, + .disable =3D adp5055_disable, + .is_enabled =3D adp5055_is_enabled, + .set_mode =3D adp5055_set_mode, + .get_mode =3D adp5055_get_mode, + .set_ramp_delay =3D regulator_set_ramp_delay_regmap, +}; + +#define ADP5055_REG_(_name, _id, _ch, _ops) \ + [_id] =3D { \ + .name =3D _name, \ + .of_match =3D of_match_ptr(_name), \ + .of_parse_cb =3D adp5055_of_parse_cb, \ + .id =3D _id, \ + .ops =3D _ops, \ + .linear_ranges =3D adp5055_voltage_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(adp5055_voltage_ranges), \ + .vsel_reg =3D ADP5055_VID##_ch, \ + .vsel_mask =3D GENMASK(7, 0), \ + .enable_reg =3D ADP5055_CTRL123, \ + .enable_mask =3D BIT(_ch), \ + .active_discharge_on =3D ADP5055_MASK_DIS##_id, \ + .active_discharge_off =3D 0, \ + .active_discharge_mask =3D ADP5055_MASK_DIS##_id, \ + .active_discharge_reg =3D ADP5055_CTRL_MODE2, \ + .ramp_reg =3D ADP5055_DLY##_ch, \ + .ramp_mask =3D ADP5055_MASK_EN_DLY, \ + .n_ramp_values =3D ARRAY_SIZE(adp5055_enable_delay_vals_2_6), \ + .type =3D REGULATOR_VOLTAGE, \ + .owner =3D THIS_MODULE, \ + } + +#define ADP5055_REG(_name, _id, _ch) \ + ADP5055_REG_(_name, _id, _ch, &adp5055_ops) + +static struct regulator_desc adp5055_regulators[] =3D { + ADP5055_REG("DCDC0", 0, 0), + ADP5055_REG("DCDC1", 1, 1), + ADP5055_REG("DCDC2", 2, 2), +}; + +static const struct of_device_id adp5055_dt_ids[] =3D { + { .compatible =3D "adi,adp5055"}, + { } +}; +MODULE_DEVICE_TABLE(of, adp5055_dt_ids); + +static int adp5055_probe(struct i2c_client *client) +{ + struct regulator_init_data *init_data; + struct device *dev =3D &client->dev; + struct adp5055 *adp5055; + int i, ret; + + init_data =3D of_get_regulator_init_data(dev, client->dev.of_node, + &adp5055_regulators[0]); + if (!init_data) + return -EINVAL; + + adp5055 =3D devm_kzalloc(dev, sizeof(struct adp5055), GFP_KERNEL); + if (!adp5055) + return -ENOMEM; + + adp5055->regmap =3D devm_regmap_init_i2c(client, &adp5055_regmap_config); + if (IS_ERR(adp5055->regmap)) + return dev_err_probe(dev, PTR_ERR(adp5055->regmap), "Failed to allocate = reg map"); + + for (i =3D 0; i < ADP5055_NUM_CH; i++) { + const struct regulator_desc *desc; + struct regulator_config config =3D { }; + struct regulator_dev *rdev; + + if (adp5055->tset =3D=3D 2600) + adp5055_regulators[i].ramp_delay_table =3D adp5055_enable_delay_vals_2_= 6; + else + adp5055_regulators[i].ramp_delay_table =3D adp5055_enable_delay_vals_20= _8; + + desc =3D &adp5055_regulators[i]; + + config.dev =3D dev; + config.driver_data =3D adp5055; + config.regmap =3D adp5055->regmap; + config.init_data =3D init_data; + + if (adp5055->hw_en_array_gpios) + config.ena_gpiod =3D adp5055->hw_en_array_gpios->desc[i]; + + rdev =3D devm_regulator_register(dev, desc, &config); + if (IS_ERR(rdev)) { + return dev_err_probe(dev, PTR_ERR(rdev), + "Failed to register %s\n", desc->name); + } + } + + ret =3D adp5055_parse_fw(dev, adp5055); + if (ret < 0) + return ret; + + return 0; +} + +static const struct of_device_id adp5055_of_match[] =3D { + { .compatible =3D "adi,adp5055", }, + { } +}; +MODULE_DEVICE_TABLE(of, adp5055_of_match); + +static const struct i2c_device_id adp5055_ids[] =3D { + { .name =3D "adp5055"}, + { }, +}; +MODULE_DEVICE_TABLE(i2c, adp5055_ids); + +static struct i2c_driver adp5055_driver =3D { + .driver =3D { + .name =3D "adp5055", + .of_match_table =3D adp5055_of_match, + }, + .probe =3D adp5055_probe, + .id_table =3D adp5055_ids, +}; +module_i2c_driver(adp5055_driver); + +MODULE_DESCRIPTION("ADP5055 Voltage Regulator Driver"); +MODULE_AUTHOR("Alexis Czezar Torreno "); +MODULE_LICENSE("GPL"); --=20 2.34.1