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Thu, 20 Mar 2025 11:32:30 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.0.133) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 20 Mar 2025 11:32:29 +0000 From: Matt Coster Date: Thu, 20 Mar 2025 11:32:19 +0000 Subject: [PATCH v4 09/18] drm/imagination: Rename event_mask -> status_mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250320-sets-bxs-4-64-patch-v1-v4-9-d987cf4ca439@imgtec.com> References: <20250320-sets-bxs-4-64-patch-v1-v4-0-d987cf4ca439@imgtec.com> In-Reply-To: <20250320-sets-bxs-4-64-patch-v1-v4-0-d987cf4ca439@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge , "Michal Wilczynski" , Alessio Belle , Alexandru Dadu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3243; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=u1casUeI9Ls0Pb7TwvXEMa3nKlI9a1VHQ9Flv7MTick=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaTf/nOUcX/QrXe3qxdrO/pceZXtM2nDnY1KHEGVvl7hM 5Mvtn/b11HKwiDGwSArpsiyY4XlCrU/aloSN34Vw8xhZQIZwsDFKQATeXyJkeFBeLBK0oUzbn8K 17w5p/dmi6FSxO9O7UMVhqo6VxZUmGxk+F/Gyp2/p8sxaov9F8m7ngYte7Xs7u1ab+BoveVOyfv sq/wA X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-GUID: B-fId4-PgKhpJlqDBbIbz7wYN48LS0U9 X-Proofpoint-ORIG-GUID: B-fId4-PgKhpJlqDBbIbz7wYN48LS0U9 X-Authority-Analysis: v=2.4 cv=V8Z90fni c=1 sm=1 tr=0 ts=67dbfcce cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=ETbM1kImDFEA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=eQCmySvtvC0styh21agA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 Now that enable_reg isn't used, rename the previously shared event_mask to status_mask since it's only used with status_reg. Signed-off-by: Matt Coster --- Changes in v4: - None - Link to v3: https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-= 9-143b3dbef02f@imgtec.com Changes in v3: - None - Link to v2: https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-= 11-3fd45d9fb0cf@imgtec.com Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 11-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_fw.h | 6 +++--- drivers/gpu/drm/imagination/pvr_fw_meta.c | 2 +- drivers/gpu/drm/imagination/pvr_fw_mips.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagina= tion/pvr_fw.h index 29bae4bc244a243a6a95bcf838d924060cc043e2..eead744835726712622d5aba9b3= 480fe264a089f 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -199,8 +199,8 @@ struct pvr_fw_defs { */ u32 clear_reg; =20 - /** @event_mask: Bitmask of events to listen for in the status_reg. */ - u32 event_mask; + /** @status_mask: Bitmask of events to listen for in the status_reg. */ + u32 status_mask; =20 /** @clear_mask: Value to write to the clear_reg in order to clear FW IR= Qs. */ u32 clear_mask; @@ -404,7 +404,7 @@ struct pvr_fw_device { pvr_cr_write32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg, value) =20 #define pvr_fw_irq_pending(pvr_dev) \ - (pvr_fw_irq_read_reg(pvr_dev, status) & (pvr_dev)->fw_dev.defs->irq.event= _mask) + (pvr_fw_irq_read_reg(pvr_dev, status) & (pvr_dev)->fw_dev.defs->irq.statu= s_mask) =20 #define pvr_fw_irq_clear(pvr_dev) \ pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_ma= sk) diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/im= agination/pvr_fw_meta.c index a51eec867884b24767f23b3b34cd7029cb660f48..6786e0153970691fa51ba3a0e62= c00a46244a3a3 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -550,7 +550,7 @@ const struct pvr_fw_defs pvr_fw_defs_meta =3D { .irq =3D { .status_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, .clear_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, - .event_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, + .status_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, .clear_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK, }, }; diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/im= agination/pvr_fw_mips.c index c810a67eeecf1016064e76baf534e31a44c859b5..f195c602bb112066e88210d0106= cb5ffc0a9abc6 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -245,7 +245,7 @@ const struct pvr_fw_defs pvr_fw_defs_mips =3D { .irq =3D { .status_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS, .clear_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, - .event_mask =3D ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN, + .status_mask =3D ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN, .clear_mask =3D ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN, }, }; --=20 2.49.0