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Conversely, it is also common to split a u64 into two u32s to write them into registers. Add an extension trait for u64 that implement these methods in a new `num` module. It is expected that this trait will be extended with other useful operations, and similar extension traits implemented for other types. Reviewed-by: Sergio Gonz=C3=A1lez Collado Signed-off-by: Alexandre Courbot --- rust/kernel/lib.rs | 1 + rust/kernel/num.rs | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++= ++ 2 files changed, 53 insertions(+) diff --git a/rust/kernel/lib.rs b/rust/kernel/lib.rs index 2fe10df9a45ccd5fa24330f927abdf9dfb874d44..a9499597ed9650f8fae9b2f53fa= 9abeea05071f4 100644 --- a/rust/kernel/lib.rs +++ b/rust/kernel/lib.rs @@ -62,6 +62,7 @@ pub mod miscdevice; #[cfg(CONFIG_NET)] pub mod net; +pub mod num; pub mod of; pub mod page; #[cfg(CONFIG_PCI)] diff --git a/rust/kernel/num.rs b/rust/kernel/num.rs new file mode 100644 index 0000000000000000000000000000000000000000..9b93db6528eef131fb74c1289f1= e152cc2a13168 --- /dev/null +++ b/rust/kernel/num.rs @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Numerical and binary utilities for primitive types. + +/// Useful operations for `u64`. +pub trait U64Ext { + /// Build a `u64` by combining its `high` and `low` parts. + /// + /// ``` + /// use kernel::num::U64Ext; + /// assert_eq!(u64::from_u32s(0x01234567, 0x89abcdef), 0x01234567_89ab= cdef); + /// ``` + fn from_u32s(high: u32, low: u32) -> Self; + + /// Returns the upper 32 bits of `self`. + fn upper_32_bits(self) -> u32; + + /// Returns the lower 32 bits of `self`. + fn lower_32_bits(self) -> u32; +} + +impl U64Ext for u64 { + fn from_u32s(high: u32, low: u32) -> Self { + ((high as u64) << u32::BITS) | low as u64 + } + + fn upper_32_bits(self) -> u32 { + (self >> u32::BITS) as u32 + } + + fn lower_32_bits(self) -> u32 { + self as u32 + } +} + +/// Same as [`U64Ext::upper_32_bits`], but defined outside of the trait so= it can be used in a +/// `const` context. +pub const fn upper_32_bits(v: u64) -> u32 { + (v >> u32::BITS) as u32 +} + +/// Same as [`U64Ext::lower_32_bits`], but defined outside of the trait so= it can be used in a +/// `const` context. +pub const fn lower_32_bits(v: u64) -> u32 { + v as u32 +} + +/// Same as [`U64Ext::from_u32s`], but defined outside of the trait so it = can be used in a `const` +/// context. +pub const fn u64_from_u32s(high: u32, low: u32) -> u64 { + ((high as u64) << u32::BITS) | low as u64 +} --=20 2.48.1 From nobody Wed Dec 17 08:54:04 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2077.outbound.protection.outlook.com [40.107.243.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83A4E221725; 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Also derive Copy and Clone since Chipsets are as cheap as an integer. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/gpu.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 17c9660da45034762edaa78e372d8821144cdeb7..4de67a2dc16302c00530026156d= 7264cbc7e5b32 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -13,7 +13,7 @@ macro_rules! define_chipset { ({ $($variant:ident =3D $value:expr),* $(,)* }) =3D> { /// Enum representation of the GPU chipset. - #[derive(fmt::Debug)] + #[derive(fmt::Debug, Copy, Clone, PartialOrd, Ord, PartialEq, Eq)] pub(crate) enum Chipset { $($variant =3D $value),*, } --=20 2.48.1 From nobody Wed Dec 17 08:54:04 2025 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2070.outbound.protection.outlook.com [40.107.244.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC72D22332B; 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Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/gpu.rs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 4de67a2dc16302c00530026156d7264cbc7e5b32..9fe6aedaa9563799c2624d461d4= e37ee9b094909 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -54,6 +54,7 @@ fn try_from(value: u32) -> Result { TU117 =3D 0x167, TU116 =3D 0x168, // Ampere + GA100 =3D 0x170, GA102 =3D 0x172, GA103 =3D 0x173, GA104 =3D 0x174, @@ -73,7 +74,7 @@ pub(crate) fn arch(&self) -> Architecture { Self::TU102 | Self::TU104 | Self::TU106 | Self::TU117 | Self::= TU116 =3D> { Architecture::Turing } - Self::GA102 | Self::GA103 | Self::GA104 | Self::GA106 | Self::= GA107 =3D> { + Self::GA100 | Self::GA102 | Self::GA103 | Self::GA104 | Self::= GA106 | Self::GA107 =3D> { Architecture::Ampere } Self::AD102 | Self::AD103 | Self::AD104 | Self::AD106 | Self::= AD107 =3D> { --=20 2.48.1 From nobody Wed Dec 17 08:54:04 2025 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2065.outbound.protection.outlook.com [40.107.244.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4976F2236EB; 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Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/gpu.rs | 5 ++-- drivers/gpu/nova-core/nova_core.rs | 12 ++++++++ drivers/gpu/nova-core/regs.rs | 60 ++++++----------------------------= ---- 3 files changed, 23 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 9fe6aedaa9563799c2624d461d4e37ee9b094909..d96901e5c8eace1e7c57c77da7d= ef209e8149cd3 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -135,11 +135,10 @@ pub(crate) struct Spec { =20 impl Spec { fn new(bar: &Devres) -> Result { - let bar =3D bar.try_access().ok_or(ENXIO)?; - let boot0 =3D regs::Boot0::read(&bar); + let boot0 =3D with_bar!(bar, |b| regs::Boot0::read(b))?; =20 Ok(Self { - chipset: boot0.chipset().try_into()?, + chipset: boot0.chipset()?, revision: Revision::from_boot0(boot0), }) } diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index a91cd924054b49966937a8db6aab9cd0614f10de..94f4778c16f6a4d046c2f799129= ed0cc68df6fd4 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -2,6 +2,18 @@ =20 //! Nova Core GPU Driver =20 +#[macro_use] +mod macros { + /// Convenience macro to run a closure while holding [`crate::driver::= Bar0`]. + /// + /// If the bar cannot be acquired, then `ENXIO` is returned. + macro_rules! with_bar { + ($bar:expr, $closure:expr) =3D> { + $bar.try_access_with($closure).ok_or(ENXIO) + }; + } +} + mod driver; mod firmware; mod gpu; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 50aefb150b0b1c9b73f07fca3b7a070885785485..7bfd2b575fe2184565d495012e5= 5cd0829b0b1ad 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -1,55 +1,13 @@ // SPDX-License-Identifier: GPL-2.0 =20 -use crate::driver::Bar0; +use core::ops::Deref; +use kernel::io::Io; +use kernel::register; =20 -// TODO -// -// Create register definitions via generic macros. See task "Generic regis= ter -// abstraction" in Documentation/gpu/nova/core/todo.rst. +use crate::gpu::Chipset; =20 -const BOOT0_OFFSET: usize =3D 0x00000000; - -// 3:0 - chipset minor revision -const BOOT0_MINOR_REV_SHIFT: u8 =3D 0; -const BOOT0_MINOR_REV_MASK: u32 =3D 0x0000000f; - -// 7:4 - chipset major revision -const BOOT0_MAJOR_REV_SHIFT: u8 =3D 4; -const BOOT0_MAJOR_REV_MASK: u32 =3D 0x000000f0; - -// 23:20 - chipset implementation Identifier (depends on architecture) -const BOOT0_IMPL_SHIFT: u8 =3D 20; -const BOOT0_IMPL_MASK: u32 =3D 0x00f00000; - -// 28:24 - chipset architecture identifier -const BOOT0_ARCH_MASK: u32 =3D 0x1f000000; - -// 28:20 - chipset identifier (virtual register field combining BOOT0_IMPL= and -// BOOT0_ARCH) -const BOOT0_CHIPSET_SHIFT: u8 =3D BOOT0_IMPL_SHIFT; -const BOOT0_CHIPSET_MASK: u32 =3D BOOT0_IMPL_MASK | BOOT0_ARCH_MASK; - -#[derive(Copy, Clone)] -pub(crate) struct Boot0(u32); - -impl Boot0 { - #[inline] - pub(crate) fn read(bar: &Bar0) -> Self { - Self(bar.readl(BOOT0_OFFSET)) - } - - #[inline] - pub(crate) fn chipset(&self) -> u32 { - (self.0 & BOOT0_CHIPSET_MASK) >> BOOT0_CHIPSET_SHIFT - } - - #[inline] - pub(crate) fn minor_rev(&self) -> u8 { - ((self.0 & BOOT0_MINOR_REV_MASK) >> BOOT0_MINOR_REV_SHIFT) as u8 - } - - #[inline] - pub(crate) fn major_rev(&self) -> u8 { - ((self.0 & BOOT0_MAJOR_REV_MASK) >> BOOT0_MAJOR_REV_SHIFT) as u8 - } -} +register!(Boot0@0x00000000, "Basic revision information about the GPU"; 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This first draft is probably very questionable. One point in particular which should IMHO receive attention: the generic wait_on() method aims at providing similar functionality to Nouveau's nvkm_[num]sec() macros. Since this method will be heavily used with different conditions to test, I'd like to avoid monomorphizing it entirely with each instance ; that's something that is achieved in nvkm_xsec() using functions that the macros invoke. I have tried achieving the same result in Rust using closures (kept as-is in the current code), but they seem to be monomorphized as well. Calling extra functions could work better, but looks also less elegant to me, so I am really open to suggestions here. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/driver.rs | 4 +- drivers/gpu/nova-core/gpu.rs | 55 +++++++++++++++- drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/regs.rs | 11 ++++ drivers/gpu/nova-core/timer.rs | 132 +++++++++++++++++++++++++++++++++= ++++ 5 files changed, 201 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index 63c19f140fbdd65d8fccf81669ac590807cc120f..0cd23aa306e4082405f480afc05= 30a41131485e7 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -10,7 +10,7 @@ pub(crate) struct NovaCore { pub(crate) gpu: Gpu, } =20 -const BAR0_SIZE: usize =3D 8; +const BAR0_SIZE: usize =3D 0x9500; pub(crate) type Bar0 =3D pci::Bar; =20 kernel::pci_device_table!( @@ -42,6 +42,8 @@ fn probe(pdev: &mut pci::Device, _info: &Self::IdInfo) ->= Result> GFP_KERNEL, )?; =20 + let _ =3D this.gpu.test_timer(); + Ok(this) } } diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index d96901e5c8eace1e7c57c77da7def209e8149cd3..f010d3152530b1cec032ca620e5= 9de51a2fc1a13 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -6,8 +6,10 @@ =20 use crate::driver::Bar0; use crate::regs; +use crate::timer::Timer; use crate::util; use core::fmt; +use core::time::Duration; =20 macro_rules! define_chipset { ({ $($variant:ident =3D $value:expr),* $(,)* }) =3D> @@ -179,6 +181,7 @@ pub(crate) struct Gpu { /// MMIO mapping of PCI BAR 0 bar: Devres, fw: Firmware, + timer: Timer, } =20 impl Gpu { @@ -194,6 +197,56 @@ pub(crate) fn new(pdev: &pci::Device, bar: Devres) -> Result Result<()> { + pr_info!("testing timer subdev\n"); + with_bar!(self.bar, |b| { + pr_info!("current timestamp: {}\n", self.timer.read(b)) + })?; + + if !matches!( + self.timer + .wait_on(&self.bar, Duration::from_millis(10), || Some(())= ), + Ok(()) + ) { + pr_crit!("timer test failure\n"); + } + + let t1 =3D with_bar!(self.bar, |b| { + pr_info!("timestamp after immediate exit: {}\n", self.timer.re= ad(b)); + self.timer.read(b) + })?; + + if self + .timer + .wait_on(&self.bar, Duration::from_millis(10), || Option::<()>= ::None) + !=3D Err(ETIMEDOUT) + { + pr_crit!("timer test 2 failure\n"); + } + + let t2 =3D with_bar!(self.bar, |b| self.timer.read(b))?; + if t2 - t1 < Duration::from_millis(10) { + pr_crit!("timer test 3 failure\n"); + } + + with_bar!(self.bar, |b| { + pr_info!( + "timestamp after timeout: {} ({:?})\n", + self.timer.read(b), + t2 - t1 + ); + })?; + + Ok(()) } } diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index 94f4778c16f6a4d046c2f799129ed0cc68df6fd4..f54dcfc66490cb6b10090ef944a= c14feca9f6972 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -18,6 +18,7 @@ macro_rules! with_bar { mod firmware; mod gpu; mod regs; +mod timer; mod util; =20 kernel::module_pci_driver! { diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 7bfd2b575fe2184565d495012e55cd0829b0b1ad..0d06e09b1ba62d55688c633500f= 37d3fe1aeb30e 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -11,3 +11,14 @@ 7:4 major_rev =3D> as u8, "major revision of the chip"; 28:20 chipset =3D> try_into Chipset, "chipset model" ); + +/* PTIMER */ + +register!(PtimerTime0@0x00009400; + 31:0 lo =3D> as u32, "low 32-bits of the timer" +); + +register!(PtimerTime1@0x00009410; + 31:0 hi =3D> as u32, "high 32 bits of the timer" +); + diff --git a/drivers/gpu/nova-core/timer.rs b/drivers/gpu/nova-core/timer.rs new file mode 100644 index 0000000000000000000000000000000000000000..1361e4ad10d923ce114972889cd= fcfa6e58a691b --- /dev/null +++ b/drivers/gpu/nova-core/timer.rs @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Nova Core Timer subdevice + +use core::fmt::Display; +use core::ops::{Add, Sub}; +use core::time::Duration; + +use kernel::devres::Devres; +use kernel::num::U64Ext; +use kernel::prelude::*; + +use crate::driver::Bar0; +use crate::regs; + +/// A timestamp with nanosecond granularity obtained from the GPU timer. +/// +/// A timestamp can also be substracted to another in order to obtain a [`= Duration`]. +/// +/// TODO: add Kunit tests! +#[derive(Debug, Copy, Clone, PartialEq, Eq, PartialOrd, Ord)] +pub(crate) struct Timestamp(u64); + +impl Display for Timestamp { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "{}", self.0) + } +} + +impl Add for Timestamp { + type Output =3D Self; + + fn add(mut self, rhs: Duration) -> Self::Output { + let mut nanos =3D rhs.as_nanos(); + while nanos > u64::MAX as u128 { + self.0 =3D self.0.wrapping_add(nanos as u64); + nanos -=3D u64::MAX as u128; + } + + Timestamp(self.0.wrapping_add(nanos as u64)) + } +} + +impl Sub for Timestamp { + type Output =3D Duration; + + fn sub(self, rhs: Self) -> Self::Output { + Duration::from_nanos(self.0.wrapping_sub(rhs.0)) + } +} + +pub(crate) struct Timer {} + +impl Timer { + pub(crate) fn new() -> Self { + Self {} + } + + /// Read the current timer timestamp. + pub(crate) fn read(&self, bar: &Bar0) -> Timestamp { + loop { + let hi =3D regs::PtimerTime1::read(bar); + let lo =3D regs::PtimerTime0::read(bar); + + if hi.hi() =3D=3D regs::PtimerTime1::read(bar).hi() { + return Timestamp(u64::from_u32s(hi.hi(), lo.lo())); + } + } + } + + #[allow(dead_code)] + pub(crate) fn time(bar: &Bar0, time: u64) { + regs::PtimerTime1::default() + .set_hi(time.upper_32_bits()) + .write(bar); + regs::PtimerTime0::default() + .set_lo(time.lower_32_bits()) + .write(bar); + } + + /// Wait until `cond` is true or `timeout` elapsed, based on GPU time. + /// + /// When `cond` evaluates to `Some`, its return value is returned. + /// + /// `Err(ETIMEDOUT)` is returned if `timeout` has been reached without= `cond` evaluating to + /// `Some`, or if the timer device is stuck for some reason. + pub(crate) fn wait_on Option>( + &self, + bar: &Devres, + timeout: Duration, + cond: F, + ) -> Result { + // Number of consecutive time reads after which we consider the ti= mer frozen if it hasn't + // moved forward. + const MAX_STALLED_READS: usize =3D 16; + + let (mut cur_time, mut prev_time, deadline) =3D { + let cur_time =3D with_bar!(bar, |b| self.read(b))?; + let deadline =3D cur_time + timeout; + + (cur_time, cur_time, deadline) + }; + let mut num_reads =3D 0; + + loop { + if let Some(ret) =3D cond() { + return Ok(ret); + } + + (|| { + cur_time =3D with_bar!(bar, |b| self.read(b))?; + + /* Check if the timer is frozen for some reason. */ + if cur_time =3D=3D prev_time { + if num_reads >=3D MAX_STALLED_READS { + return Err(ETIMEDOUT); + } + num_reads +=3D 1; + } else { + if cur_time >=3D deadline { + return Err(ETIMEDOUT); + } + + num_reads =3D 0; + prev_time =3D cur_time; + } + + Ok(()) + })()?; + } + } +} --=20 2.48.1 From nobody Wed Dec 17 08:54:04 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2073.outbound.protection.outlook.com [40.107.243.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CEFD224AF7; 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Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/driver.rs | 2 +- drivers/gpu/nova-core/falcon.rs | 618 +++++++++++++++++++++++++++++++++= ++++ drivers/gpu/nova-core/gpu.rs | 13 + drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/regs.rs | 188 ++++++++++- 5 files changed, 820 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index 0cd23aa306e4082405f480afc0530a41131485e7..dee5fd22eecb2ce1f4ea765338b= 0c1b68853b2d3 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -10,7 +10,7 @@ pub(crate) struct NovaCore { pub(crate) gpu: Gpu, } =20 -const BAR0_SIZE: usize =3D 0x9500; +const BAR0_SIZE: usize =3D 0x1000000; pub(crate) type Bar0 =3D pci::Bar; =20 kernel::pci_device_table!( diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs new file mode 100644 index 0000000000000000000000000000000000000000..0dd4b45abbe0a62238efe24d899= c55d5db348586 --- /dev/null +++ b/drivers/gpu/nova-core/falcon.rs @@ -0,0 +1,618 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Falcon microprocessor base support + +// TODO: remove this once this module is actively used. +#![allow(dead_code)] + +use core::hint::unreachable_unchecked; +use core::marker::PhantomData; +use core::time::Duration; +use kernel::bindings; +use kernel::devres::Devres; +use kernel::{pci, prelude::*}; + +use crate::driver::Bar0; +use crate::gpu::Chipset; +use crate::regs; +use crate::timer::Timer; + +#[repr(u8)] +#[derive(Debug, Default, Copy, Clone, PartialEq, Eq, PartialOrd, Ord)] +pub(crate) enum FalconCoreRev { + #[default] + Rev1 =3D 1, + Rev2 =3D 2, + Rev3 =3D 3, + Rev4 =3D 4, + Rev5 =3D 5, + Rev6 =3D 6, + Rev7 =3D 7, +} + +impl TryFrom for FalconCoreRev { + type Error =3D Error; + + fn try_from(value: u32) -> core::result::Result { + use FalconCoreRev::*; + + let rev =3D match value { + 1 =3D> Rev1, + 2 =3D> Rev2, + 3 =3D> Rev3, + 4 =3D> Rev4, + 5 =3D> Rev5, + 6 =3D> Rev6, + 7 =3D> Rev7, + _ =3D> return Err(EINVAL), + }; + + Ok(rev) + } +} + +#[repr(u8)] +#[derive(Debug, Default, Copy, Clone)] +pub(crate) enum FalconSecurityModel { + #[default] + None =3D 0, + Light =3D 2, + Heavy =3D 3, +} + +impl TryFrom for FalconSecurityModel { + type Error =3D Error; + + fn try_from(value: u32) -> core::result::Result { + use FalconSecurityModel::*; + + let sec_model =3D match value { + 0 =3D> None, + 2 =3D> Light, + 3 =3D> Heavy, + _ =3D> return Err(EINVAL), + }; + + Ok(sec_model) + } +} + +#[repr(u8)] +#[derive(Debug, Default, Copy, Clone, PartialEq, Eq, PartialOrd, Ord)] +pub(crate) enum FalconCoreRevSubversion { + #[default] + Subversion0 =3D 0, + Subversion1 =3D 1, + Subversion2 =3D 2, + Subversion3 =3D 3, +} + +impl From for FalconCoreRevSubversion { + fn from(value: u32) -> Self { + use FalconCoreRevSubversion::*; + + match value & 0b11 { + 0 =3D> Subversion0, + 1 =3D> Subversion1, + 2 =3D> Subversion2, + 3 =3D> Subversion3, + // SAFETY: the `0b11` mask limits the possible values to `0..= =3D3`. + 4..=3Du32::MAX =3D> unsafe { unreachable_unchecked() }, + } + } +} + +#[repr(u8)] +#[derive(Debug, Default, Copy, Clone, PartialEq, Eq)] +pub(crate) enum FalconModSelAlgo { + #[default] + Rsa3k =3D 1, +} + +impl TryFrom for FalconModSelAlgo { + type Error =3D Error; + + fn try_from(value: u32) -> core::result::Result { + match value { + 1 =3D> Ok(FalconModSelAlgo::Rsa3k), + _ =3D> Err(EINVAL), + } + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub(crate) enum RiscvCoreSelect { + Falcon =3D 0, + Riscv =3D 1, +} + +impl From for RiscvCoreSelect { + fn from(value: bool) -> Self { + match value { + false =3D> RiscvCoreSelect::Falcon, + true =3D> RiscvCoreSelect::Riscv, + } + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub(crate) enum FalconMem { + Imem, + Dmem, +} + +#[repr(C)] +#[derive(Debug, Clone, Copy)] +pub(crate) struct FalconUCodeDescV3 { + pub(crate) hdr: u32, + pub(crate) stored_size: u32, + pub(crate) pkc_data_offset: u32, + pub(crate) interface_offset: u32, + pub(crate) imem_phys_base: u32, + pub(crate) imem_load_size: u32, + pub(crate) imem_virt_base: u32, + pub(crate) dmem_phys_base: u32, + pub(crate) dmem_load_size: u32, + pub(crate) engine_id_mask: u16, + pub(crate) ucode_id: u8, + pub(crate) signature_count: u8, + pub(crate) signature_versions: u16, + _reserved: u16, +} + +impl FalconUCodeDescV3 { + pub(crate) fn ver(&self) -> u8 { + ((self.hdr & 0xff00) >> 8) as u8 + } + + pub(crate) fn size(&self) -> usize { + ((self.hdr & 0xffff0000) >> 16) as usize + } +} + +/// Trait defining the parameters of a given Falcon instance. +pub(crate) trait FalconInstance { + /// Base I/O address for the falcon, relative from which its registers= are accessed. + const BASE: usize; +} + +pub(crate) struct Gsp; +impl FalconInstance for Gsp { + const BASE: usize =3D 0x00110000; +} +pub(crate) type GspFalcon =3D Falcon; + +pub(crate) struct Sec2; +impl FalconInstance for Sec2 { + const BASE: usize =3D 0x00840000; +} +pub(crate) type Sec2Falcon =3D Falcon; + +/// Contains the base parameters common to all Falcon instances. +#[derive(Debug)] +pub(crate) struct Falcon { + /// Chipset this falcon belongs to. + chipset: Chipset, + /// Whether this falcon is part of a dual falcon/riscv engine. + has_riscv: bool, + _instance: PhantomData, +} + +impl Falcon { + pub(crate) fn new( + pdev: &pci::Device, + chipset: Chipset, + bar: &Devres, + need_riscv: bool, + ) -> Result { + let hwcfg1 =3D with_bar!(bar, |b| regs::FalconHwcfg1::read(b, I::B= ASE))?; + let rev =3D hwcfg1.core_rev()?; + let subver =3D hwcfg1.core_rev_subversion(); + let sec_model =3D hwcfg1.security_model()?; + + if need_riscv { + let hwcfg2 =3D with_bar!(bar, |b| regs::FalconHwcfg2::read(b, = I::BASE))?; + if !hwcfg2.riscv() { + dev_err!( + pdev.as_ref(), + "riscv support requested on falcon that does not suppo= rt it\n" + ); + return Err(EINVAL); + } + } + + dev_info!( + pdev.as_ref(), + "new falcon: {:?} {:?} {:?}", + rev, + subver, + sec_model + ); + + Ok(Self { + chipset, + has_riscv: need_riscv, + _instance: PhantomData, + }) + } + + fn select_falcon_core(&self, bar: &Devres, timer: &Timer) -> Res= ult<()> { + if self.has_riscv { + let bcr_ctrl =3D with_bar!(bar, |b| regs::RiscvBcrCtrl::read(b= , I::BASE))?; + if bcr_ctrl.core_select() !=3D RiscvCoreSelect::Falcon { + with_bar!(bar, |b| regs::RiscvBcrCtrl::default() + .set_core_select(RiscvCoreSelect::Falcon) + .write(b, I::BASE))?; + + timer.wait_on(bar, Duration::from_millis(10), || { + bar.try_access_with(|b| regs::RiscvBcrCtrl::read(b, I:= :BASE)) + .and_then(|v| if v.valid() { Some(()) } else { Non= e }) + })?; + } + } + + Ok(()) + } + + fn reset_wait_mem_scrubbing(&self, bar: &Devres, timer: &Timer) = -> Result<()> { + /* TODO: is this needed? */ + with_bar!(bar, |b| regs::FalconMailbox0::alter(b, I::BASE, |v| v))= ?; + + timer.wait_on(bar, Duration::from_millis(20), || { + bar.try_access_with(|b| regs::FalconHwcfg2::read(b, I::BASE)) + .and_then(|r| if r.mem_scrubbing() { Some(()) } else { Non= e }) + }) + } + + fn reset_prep(&self, bar: &Devres, timer: &Timer) -> Result<()> { + let _ =3D with_bar!(bar, |b| regs::FalconHwcfg2::read(b, I::BASE))= ?; + + // Expected to timeout apparently? + // TODO: check why with OpenRM. + let _ =3D timer.wait_on(bar, Duration::from_micros(150), || { + bar.try_access_with(|b| regs::FalconHwcfg2::read(b, I::BASE)) + .and_then(|r| if r.unk_31() { Some(()) } else { None }) + }); + + Ok(()) + } + + fn reset_eng(&self, bar: &Devres, timer: &Timer) -> Result<()> { + self.reset_prep(bar, timer)?; + + with_bar!(bar, |b| regs::RiscvUnk3c0::alter(b, I::BASE, |v| v + .set_unk0(true)))?; + + let _: Result<()> =3D timer.wait_on(bar, Duration::from_micros(10)= , || None); + + with_bar!(bar, |b| regs::RiscvUnk3c0::alter(b, I::BASE, |v| v + .set_unk0(false)))?; + + self.reset_wait_mem_scrubbing(bar, timer)?; + + Ok(()) + } + + fn disable(&self, bar: &Devres, timer: &Timer) -> Result<()> { + self.select_falcon_core(bar, timer)?; + + with_bar!(bar, |b| { + regs::FalconUnk0048::alter(b, I::BASE, |r| r.set_val0(0)); + + regs::FalconIrqmclr::default() + .set_val(u32::MAX) + .write(b, I::BASE) + })?; + + self.reset_eng(bar, timer) + } + + fn enable(&self, bar: &Devres, timer: &Timer) -> Result<()> { + self.reset_eng(bar, timer)?; + self.select_falcon_core(bar, timer)?; + self.reset_wait_mem_scrubbing(bar, timer)?; + + with_bar!(bar, |b| { + // We write Boot0 into FalconRm, for some reason... + regs::FalconRm::default() + .set_val(regs::Boot0::read(b).into()) + .write(b, I::BASE) + }) + } + + pub(crate) fn reset(&self, bar: &Devres, timer: &Timer) -> Resul= t<()> { + self.disable(bar, timer)?; + self.enable(bar, timer) + } + + fn dma_init( + &self, + bar: &Devres, + dma_handle: bindings::dma_addr_t, + mem: FalconMem, + xfer_len: u32, + sec: bool, + ) -> Result { + with_bar!(bar, |b| { + regs::FalconDmaTrfBase::default() + .set_base((dma_handle >> 8) as u32) + .write(b, I::BASE); + regs::FalconDmaTrfBase1::default() + .set_base((dma_handle >> 40) as u16) + .write(b, I::BASE) + })?; + + Ok(regs::FalconDmaTrfCmd::default() + .set_size((xfer_len.ilog2() - 2) as u8) + .set_imem(mem =3D=3D FalconMem::Imem) + .set_sec(if sec { 1 } else { 0 })) + } + + fn dma_xfer( + &self, + bar: &Devres, + mem_base: u32, + dma_base: u32, + cmd: regs::FalconDmaTrfCmd, + ) -> Result<()> { + with_bar!(bar, |b| { + regs::FalconDmaTrfMOffs::default() + .set_offs(mem_base) + .write(b, I::BASE); + regs::FalconDmaTrfBOffs::default() + .set_offs(dma_base) + .write(b, I::BASE); + + cmd.write(b, I::BASE) + }) + } + + fn dma_done(&self, bar: &Devres, timer: &Timer) -> Result<()> { + timer.wait_on(bar, Duration::from_millis(2000), || { + bar.try_access_with(|b| regs::FalconDmaTrfCmd::read(b, I::BASE= )) + .and_then(|v| if v.idle() { Some(()) } else { None }) + }) + } + + fn dma_wr( + &self, + bar: &Devres, + timer: &Timer, + dma_handle: bindings::dma_addr_t, + dma_base: u32, + mem: FalconMem, + mem_base: u32, + len: u32, + sec: bool, + ) -> Result<()> { + const DMA_LEN: u32 =3D 256; + + let (dma_start, dma_addr) =3D match mem { + FalconMem::Imem =3D> (0, dma_handle), + FalconMem::Dmem =3D> (dma_base, dma_handle + dma_base as bindi= ngs::dma_addr_t), + }; + + pr_info!( + "dma write {:?}: dma_handle {:x} dma_start {:x} dma_addr {:x} = len {:x}\n", + mem, + dma_handle, + dma_start, + dma_addr, + len + ); + + let cmd =3D self.dma_init(bar, dma_addr, mem, DMA_LEN, sec)?; + + let mut dst =3D mem_base; + let mut src =3D dma_base; + let mut remain =3D len; + + while remain >=3D DMA_LEN { + self.dma_xfer(bar, dst, src - dma_start, cmd)?; + self.dma_done(bar, timer)?; + + src +=3D DMA_LEN; + dst +=3D DMA_LEN; + remain -=3D DMA_LEN; + } + + pr_info!("dma write remain: {} bytes\n", remain); + + Ok(()) + } + + pub(crate) fn dma_load( + &self, + bar: &Devres, + timer: &Timer, + dma_handle: bindings::dma_addr_t, + imem_params: (u32, u32, u32), + dmem_params: (u32, u32, u32), + ) -> Result<()> { + pr_info!("dma_load: {:?} {:?}\n", imem_params, dmem_params); + + with_bar!(bar, |b| { + regs::FalconUnk624::alter(b, I::BASE, |v| v.set_unk7(true)); + regs::FalconDmaCtl::default().write(b, I::BASE); + regs::FalconUnk600::alter(b, I::BASE, |v| v.set_unk16(false).s= et_unk2((1 << 2) | 1)); + })?; + + self.dma_wr( + bar, + timer, + dma_handle, + imem_params.0, + FalconMem::Imem, + imem_params.1, + imem_params.2, + true, + )?; + self.dma_wr( + bar, + timer, + dma_handle, + dmem_params.0, + FalconMem::Dmem, + dmem_params.1, + dmem_params.2, + true, + )?; + + Ok(()) + } + + pub(crate) fn boot( + &self, + bar: &Devres, + timer: &Timer, + v3_desc: &FalconUCodeDescV3, + mbox0: Option, + mbox1: Option, + ) -> Result<(u32, u32)> { + pr_info!("boot 0\n"); + + // Program BROM registers for PKC signature validation. + if self.chipset >=3D Chipset::GA102 { + let pkc_data_offset =3D v3_desc.pkc_data_offset; + let engine_id_mask =3D v3_desc.engine_id_mask; + let ucode_id =3D v3_desc.ucode_id; + + pr_info!( + "dmem_sign: {:#x}, engine_id: {:#x}, ucode_id: {:#x}", + pkc_data_offset, + engine_id_mask, + ucode_id + ); + + with_bar!(bar, |b| { + regs::FalconBromParaaddr0::default() + .set_addr(pkc_data_offset) + .write(b, I::BASE); + regs::FalconBromEngidmask::default() + .set_mask(engine_id_mask as u32) + .write(b, I::BASE); + regs::FalconBromCurrUcodeId::default() + .set_ucode_id(ucode_id as u32) + .write(b, I::BASE); + regs::FalconModSel::default() + .set_algo(FalconModSelAlgo::Rsa3k) + .write(b, I::BASE); + })?; + } + + pr_info!("boot 1\n"); + + with_bar!(bar, |b| { + if let Some(mbox0) =3D mbox0 { + regs::FalconMailbox0::default() + .set_mailbox0(mbox0) + .write(b, I::BASE); + } + + if let Some(mbox1) =3D mbox1 { + regs::FalconMailbox1::default() + .set_mailbox1(mbox1) + .write(b, I::BASE); + } + + // Set `BootVec` to start of non-secure code. + // TODO: use boot vector variable - apparently this is 0 on v3= hdr? + regs::FalconBootVec::default() + .set_boot_vec(0) + .write(b, I::BASE); + + regs::FalconCpuCtl::default() + .set_start_cpu(true) + .write(b, I::BASE); + })?; + + pr_info!("booted!\n"); + timer.wait_on(bar, Duration::from_secs(2), || { + bar.try_access() + .map(|b| regs::FalconCpuCtl::read(&*b, I::BASE)) + .and_then(|v| if v.halted() { Some(()) } else { None }) + })?; + + let (mbox0, mbox1) =3D with_bar!(bar, |b| { + let mbox0 =3D regs::FalconMailbox0::read(b, I::BASE).mailbox0(= ); + let mbox1 =3D regs::FalconMailbox1::read(b, I::BASE).mailbox1(= ); + + (mbox0, mbox1) + })?; + + pr_info!("successfully returned {} {}\n", mbox0, mbox1); + + Ok((mbox0, mbox1)) + } +} + +#[repr(C)] +#[derive(Debug)] +struct FalconAppifHdrV1 { + ver: u8, + hdr: u8, + len: u8, + cnt: u8, +} + +#[repr(C)] +#[derive(Debug)] +struct FalconAppifV1 { + id: u32, + dmem_base: u32, +} + +const NVFW_FALCON_APPIF_ID_DMEMMAPPER: u32 =3D 0x4; + +#[repr(C)] +#[derive(Debug)] +struct FalconAppifDmemmapperV3 { + signature: u32, + version: u16, + size: u16, + cmd_in_buffer_offset: u32, + cmd_in_buffer_size: u32, + cmd_out_buffer_offset: u32, + cmd_out_buffer_size: u32, + nvf_img_data_buffer_offset: u32, + nvf_img_data_buffer_size: u32, + printf_buffer_hdr: u32, + ucode_build_time_stamp: u32, + ucode_signature: u32, + init_cmd: u32, + ucode_feature: u32, + ucode_cmd_mask0: u32, + ucode_cmd_mask1: u32, + multi_tgt_tbl: u32, +} + +pub(crate) const NVFW_FALCON_APPIF_DMEMMAPPER_CMD_FRTS: u32 =3D 0x15; + +#[derive(Debug)] +#[repr(C)] +struct ReadVbios { + ver: u32, + hdr: u32, + addr: u64, + size: u32, + flags: u32, +} + +#[derive(Debug)] +#[repr(C)] +struct FrtsRegion { + ver: u32, + hdr: u32, + addr: u32, + size: u32, + ftype: u32, +} + +const NVFW_FRTS_CMD_REGION_TYPE_FB: u32 =3D 2; + +#[derive(Debug)] +#[repr(C)] +struct FrtsCmd { + read_vbios: ReadVbios, + frts_region: FrtsRegion, +} diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index f010d3152530b1cec032ca620e59de51a2fc1a13..ec745dd8175bd3164ed1b865293= a526b09c59ab3 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -5,6 +5,7 @@ }; =20 use crate::driver::Bar0; +use crate::falcon::{GspFalcon, Sec2Falcon}; use crate::regs; use crate::timer::Timer; use crate::util; @@ -198,6 +199,18 @@ pub(crate) fn new(pdev: &pci::Device, bar: Devres) -> Result Chipset::GA100 { + true + } else { + false + }, + )?; + + let _sec2_falcon =3D Sec2Falcon::new(pdev, spec.chipset, &bar, fal= se)?; =20 Ok(pin_init!(Self { spec, diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index f54dcfc66490cb6b10090ef944ac14feca9f6972..35c030485532633a5dd59a8a4a1= f6d385cb46c98 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -15,6 +15,7 @@ macro_rules! with_bar { } =20 mod driver; +mod falcon; mod firmware; mod gpu; mod regs; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 0d06e09b1ba62d55688c633500f37d3fe1aeb30e..2952fa7f84c274f122bc12e5506= b0b2ac0fbb82d 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -2,8 +2,11 @@ =20 use core::ops::Deref; use kernel::io::Io; -use kernel::register; +use kernel::{register, register_rel}; =20 +use crate::falcon::{ + FalconCoreRev, FalconCoreRevSubversion, FalconModSelAlgo, FalconSecuri= tyModel, RiscvCoreSelect, +}; use crate::gpu::Chipset; =20 register!(Boot0@0x00000000, "Basic revision information about the GPU"; @@ -22,3 +25,186 @@ 31:0 hi =3D> as u32, "high 32 bits of the timer" ); =20 +/* PFALCON */ + +register_rel!(FalconIrqsclr@0x00000004; + 4:4 halt =3D> as_bit bool; + 6:6 swgen0 =3D> as_bit bool; +); + +register_rel!(FalconIrqstat@0x00000008; + 4:4 halt =3D> as_bit bool; + 6:6 swgen0 =3D> as_bit bool; +); + +register_rel!(FalconIrqmclr@0x00000014; + 31:0 val =3D> as u32 +); + +register_rel!(FalconIrqmask@0x00000018; + 31:0 val =3D> as u32 +); + +register_rel!(FalconRm@0x00000084; + 31:0 val =3D> as u32 +); + +register_rel!(FalconIrqdest@0x0000001c; + 31:0 val =3D> as u32 +); + +register_rel!(FalconMailbox0@0x00000040; + 31:0 mailbox0 =3D> as u32 +); +register_rel!(FalconMailbox1@0x00000044; + 31:0 mailbox1 =3D> as u32 +); + +register_rel!(FalconUnk0048@0x00000048; + 1:0 val0 =3D> as u32 +); + +register_rel!(FalconHwcfg2@0x000000f4; + 10:10 riscv =3D> as_bit bool; + 12:12 mem_scrubbing =3D> as_bit bool; + 31:31 unk_31 =3D> as_bit bool; +); + +register_rel!(FalconCpuCtl@0x00000100; + 1:1 start_cpu =3D> as_bit bool; + 4:4 halted =3D> as_bit bool; + 6:6 alias_en =3D> as_bit bool; +); +register_rel!(FalconBootVec@0x00000104; + 31:0 boot_vec =3D> as u32 +); + +register_rel!(FalconHwCfg@0x00000108; + 8:0 imem_size =3D> as u32; + 17:9 dmem_size =3D> as u32; +); + +register_rel!(FalconDmaCtl@0x0000010c; + 0:0 require_ctx =3D> as_bit bool; + 1:1 dmem_scrubbing =3D> as_bit bool; + 2:2 imem_scrubbing =3D> as_bit bool; + 6:3 dmaq_num =3D> as_bit u8; + 7:7 secure_stat =3D> as_bit bool; +); + +register_rel!(FalconDmaTrfBase@0x00000110; + 31:0 base =3D> as u32; +); + +register_rel!(FalconDmaTrfMOffs@0x00000114; + 23:0 offs =3D> as u32; +); + +register_rel!(FalconDmaTrfCmd@0x00000118; + 0:0 full =3D> as_bit bool; + 1:1 idle =3D> as_bit bool; + 3:2 sec =3D> as_bit u8; + 4:4 imem =3D> as_bit bool; + 5:5 is_write =3D> as_bit bool; + 10:8 size =3D> as u8; + 14:12 ctxdma =3D> as u8; + 16:16 set_dmtag =3D> as u8; +); + +register_rel!(FalconDmaTrfBOffs@0x0000011c; + 31:0 offs =3D> as u32; +); + +register_rel!(FalconDmaTrfBase1@0x00000128; + 8:0 base =3D> as u16; +); + +register_rel!(FalconHwcfg1@0x0000012c; + 3:0 core_rev =3D> try_into FalconCoreRev, "core revision of the fa= lcon"; + 5:4 security_model =3D> try_into FalconSecurityModel, "security mo= del of the falcon"; + 7:6 core_rev_subversion =3D> into FalconCoreRevSubversion; + 11:8 imem_ports =3D> as u8; + 15:12 dmem_ports =3D> as u8; +); + +// TODO: This should be able to take an index, like +0x180[16; 8]? Then th= e constructor or read +// method take the port we want to address as argument. +register_rel!(FalconImemC@0x00000180; + 7:2 offs =3D> as u8; + 23:8 blk =3D> as u8; + 24:24 aincw =3D> as_bit bool; + 25:25 aincr =3D> as_bit bool; + 28:28 secure =3D> as_bit bool; + 29:29 sec_atomic =3D> as_bit bool; +); + +register_rel!(FalconImemD@0x00000184; + 31:0 data =3D> as u32; +); + +register_rel!(FalconImemT@0x00000188; + 15:0 data =3D> as u16; +); + +register_rel!(FalconDmemC@0x000001c0; + 23:0 addr =3D> as u32; + 7:2 offs =3D> as u8; + 23:8 blk =3D> as u8; + 24:24 aincw =3D> as_bit bool; + 25:25 aincr =3D> as_bit bool; + 26:26 settag =3D> as_bit bool; + 27:27 setlvl =3D> as_bit bool; + 28:28 va =3D> as_bit bool; + 29:29 miss =3D> as_bit bool; +); + +register_rel!(FalconDmemD@0x000001c4; + 31:0 data =3D> as u32; +); + +register_rel!(FalconModSel@0x00001180; + 7:0 algo =3D> try_into FalconModSelAlgo; +); +register_rel!(FalconBromCurrUcodeId@0x00001198; + 31:0 ucode_id =3D> as u32; +); +register_rel!(FalconBromEngidmask@0x0000119c; + 31:0 mask =3D> as u32; +); +register_rel!(FalconBromParaaddr0@0x00001210; + 31:0 addr =3D> as u32; +); + +register_rel!(RiscvCpuCtl@0x00000388; + 0:0 startcpu =3D> as_bit bool; + 4:4 halted =3D> as_bit bool; + 5:5 stopped =3D> as_bit bool; + 7:7 active_stat =3D> as_bit bool; +); + +register_rel!(RiscvUnk3c0@0x000003c0; + 0:0 unk0 =3D> as_bit bool; +); + +register_rel!(RiscvIrqmask@0x00000528; + 31:0 mask =3D> as u32; +); + +register_rel!(RiscvIrqdest@0x0000052c; + 31:0 dest =3D> as u32; +); + +register_rel!(FalconUnk600@0x00000600; + 16:16 unk16 =3D> as_bit bool; + 2:0 unk2 =3D> as u8; +); + +register_rel!(FalconUnk624@0x00000624; + 7:7 unk7 =3D> as_bit bool; +); + +register_rel!(RiscvBcrCtrl@0x00001668; + 0:0 valid =3D> as_bit bool; + 4:4 core_select =3D> as_bit RiscvCoreSelect; + 8:8 br_fetch =3D> as_bit bool; +); --=20 2.48.1