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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v3 03/29] x86/cpu: Introduce and use leaf 0x2 parsing helpers Date: Wed, 19 Mar 2025 13:21:11 +0100 Message-ID: <20250319122137.4004-4-darwi@linutronix.de> In-Reply-To: <20250319122137.4004-1-darwi@linutronix.de> References: <20250319122137.4004-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce CPUID leaf 0x2 parsing helpers at . This allows sharing the leaf 0x2's output validation and iteration logic across both x86/cpu intel.c and cacheinfo.c. Start by converting intel.c to the new API. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid.h | 1 + arch/x86/include/asm/cpuid/leaf_0x2_api.h | 65 +++++++++++++++++++++++ arch/x86/include/asm/cpuid/types.h | 16 ++++++ arch/x86/kernel/cpu/intel.c | 23 +++----- 4 files changed, 88 insertions(+), 17 deletions(-) create mode 100644 arch/x86/include/asm/cpuid/leaf_0x2_api.h diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h index d5749b25fa10..585819331dc6 100644 --- a/arch/x86/include/asm/cpuid.h +++ b/arch/x86/include/asm/cpuid.h @@ -4,5 +4,6 @@ #define _ASM_X86_CPUID_H =20 #include +#include =20 #endif /* _ASM_X86_CPUID_H */ diff --git a/arch/x86/include/asm/cpuid/leaf_0x2_api.h b/arch/x86/include/a= sm/cpuid/leaf_0x2_api.h new file mode 100644 index 000000000000..4c845fc96716 --- /dev/null +++ b/arch/x86/include/asm/cpuid/leaf_0x2_api.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_CPUID_LEAF_0x2_API_H +#define _ASM_X86_CPUID_LEAF_0x2_API_H + +#include +#include + +/** + * cpuid_get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output + * @regs: Output parameter + * + * Query CPUID leaf 0x2 and store its output in @regs. Force set any + * invalid 1-byte descriptor returned by the hardware to zero (the NULL + * cache/TLB descriptor) before returning it to the caller. + * + * Use for_each_leaf_0x2_desc() to iterate over the returned output. + */ +static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs) +{ + cpuid_leaf(0x2, regs); + + /* + * All Intel CPUs must report an iteration count of 1. In case + * of bogus hardware, treat all returned descriptors as NULL. + */ + if (regs->desc[0] !=3D 0x01) { + for (int i =3D 0; i < 4; i++) + regs->regv[i] =3D 0; + return; + } + + /* + * The most significant bit (MSB) of each register must be clear. + * If a register is invalid, replace its descriptors with NULL. + */ + for (int i =3D 0; i < 4; i++) { + if (regs->reg[i].invalid) + regs->regv[i] =3D 0; + } +} + +/** + * for_each_leaf_0x2_desc() - Iterator for CPUID leaf 0x2 descriptors + * @regs: Leaf 0x2 output, as returned by cpuid_get_leaf_0x2_regs() + * @desc: Pointer to the returned descriptor for each iteration + * + * Loop over the 1-byte descriptors in the passed leaf 0x2 output registers + * @regs. Provide each descriptor through @desc. + * + * Note that the first byte is skipped as it is not a descriptor. + * + * Sample usage:: + * + * union leaf_0x2_regs regs; + * u8 *desc; + * + * cpuid_get_leaf_0x2_regs(®s); + * for_each_leaf_0x2_desc(regs, desc) { + * // Handle *desc value + * } + */ +#define for_each_leaf_0x2_desc(regs, desc) \ + for (desc =3D &(regs).desc[1]; desc < &(regs).desc[16]; desc++) + +#endif /* _ASM_X86_CPUID_LEAF_0x2_API_H */ diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 8582e27e836d..753f6c4514f4 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -29,4 +29,20 @@ enum cpuid_regs_idx { #define CPUID_LEAF_FREQ 0x16 #define CPUID_LEAF_TILE 0x1d =20 +/* + * Types for CPUID(0x2) parsing + * Check + */ + +struct leaf_0x2_reg { + u32 : 31, + invalid : 1; +}; + +union leaf_0x2_regs { + struct leaf_0x2_reg reg[4]; + u32 regv[4]; + u8 desc[16]; +}; + #endif /* _ASM_X86_CPUID_TYPES_H */ diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 0570d4d86006..aeb7d6d48379 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -778,27 +779,15 @@ static void intel_tlb_lookup(const unsigned char desc) =20 static void intel_detect_tlb(struct cpuinfo_x86 *c) { - u32 regs[4]; - u8 *desc =3D (u8 *)regs; + union leaf_0x2_regs regs; + u8 *desc; =20 if (c->cpuid_level < 2) return; =20 - cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); - - /* Intel CPUs must report an iteration count of 1 */ - if (desc[0] !=3D 0x01) - return; - - /* If a register's bit 31 is set, it is an unknown format */ - for (int i =3D 0; i < 4; i++) { - if (regs[i] & (1 << 31)) - regs[i] =3D 0; - } - - /* Skip the first byte as it is not a descriptor */ - for (int i =3D 1; i < 16; i++) - intel_tlb_lookup(desc[i]); + cpuid_get_leaf_0x2_regs(®s); + for_each_leaf_0x2_desc(regs, desc) + intel_tlb_lookup(*desc); } =20 static const struct cpu_dev intel_cpu_dev =3D { --=20 2.48.1