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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v3 19/29] x86/cpu: Use enums for TLB descriptor types Date: Wed, 19 Mar 2025 13:21:27 +0100 Message-ID: <20250319122137.4004-20-darwi@linutronix.de> In-Reply-To: <20250319122137.4004-1-darwi@linutronix.de> References: <20250319122137.4004-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The leaf 0x2 one-byte TLB descriptor types: TLB_INST_4K TLB_INST_4M TLB_INST_2M_4M ... are just discriminators to be used within the intel_tlb_table[] mapping. Their specific values are irrelevant. Use enums for such types. Make the enum packed and static assert that its values remain within a single byte so that the intel_tlb_table[] size do not go out of hand. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 29 +++++++++++++++++++++++++++++ arch/x86/kernel/cpu/intel.c | 28 +++------------------------- 2 files changed, 32 insertions(+), 25 deletions(-) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index bbbd0bccfce5..0c07df192749 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -58,4 +58,33 @@ enum _cache_table_type { } __packed; static_assert(sizeof(enum _cache_table_type) =3D=3D 1); =20 +/* + * Leaf 0x2 1-byte descriptors' TLB types + * To be used for their mappings at intel_tlb_table[] + * + * Start at 1 since type 0 is reserved for HW byte descriptors which are + * not recognized by the kernel; i.e., those without an explicit mapping. + */ +enum _tlb_table_type { + TLB_INST_4K =3D 1, + TLB_INST_4M, + TLB_INST_2M_4M, + TLB_INST_ALL, + + TLB_DATA_4K, + TLB_DATA_4M, + TLB_DATA_2M_4M, + TLB_DATA_4K_4M, + TLB_DATA_1G, + TLB_DATA_1G_2M_4M, + + TLB_DATA0_4K, + TLB_DATA0_4M, + TLB_DATA0_2M_4M, + + STLB_4K, + STLB_4K_2M, +} __packed; +static_assert(sizeof(enum _tlb_table_type) =3D=3D 1); + #endif /* _ASM_X86_CPUID_TYPES_H */ diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index aeb7d6d48379..def433e0081f 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -626,28 +626,6 @@ static unsigned int intel_size_cache(struct cpuinfo_x8= 6 *c, unsigned int size) } #endif =20 -#define TLB_INST_4K 0x01 -#define TLB_INST_4M 0x02 -#define TLB_INST_2M_4M 0x03 - -#define TLB_INST_ALL 0x05 -#define TLB_INST_1G 0x06 - -#define TLB_DATA_4K 0x11 -#define TLB_DATA_4M 0x12 -#define TLB_DATA_2M_4M 0x13 -#define TLB_DATA_4K_4M 0x14 - -#define TLB_DATA_1G 0x16 -#define TLB_DATA_1G_2M_4M 0x17 - -#define TLB_DATA0_4K 0x21 -#define TLB_DATA0_4M 0x22 -#define TLB_DATA0_2M_4M 0x23 - -#define STLB_4K 0x41 -#define STLB_4K_2M 0x42 - /* * All of leaf 0x2's one-byte TLB descriptors implies the same number of * entries for their respective TLB types. The 0x63 descriptor is an @@ -660,7 +638,7 @@ static unsigned int intel_size_cache(struct cpuinfo_x86= *c, unsigned int size) =20 struct _tlb_table { unsigned char descriptor; - char tlb_type; + enum _tlb_table_type type; unsigned int entries; }; =20 @@ -718,11 +696,11 @@ static void intel_tlb_lookup(const unsigned char desc) intel_tlb_table[k].descriptor !=3D 0; k++) ; =20 - if (intel_tlb_table[k].tlb_type =3D=3D 0) + if (intel_tlb_table[k].type =3D=3D 0) return; =20 entries =3D intel_tlb_table[k].entries; - switch (intel_tlb_table[k].tlb_type) { + switch (intel_tlb_table[k].type) { case STLB_4K: tlb_lli_4k =3D max(tlb_lli_4k, entries); tlb_lld_4k =3D max(tlb_lld_4k, entries); --=20 2.48.1