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charset="utf-8" From: Qiang Yu Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the whole PHY (hardware and register), no_csr reset only resets PHY hardware but retains register values, which means PHY setting can be skipped during PHY init if PCIe link is enabled in bootloader and only no_csr is toggled after that. Hence, determine whether the PHY has been enabled in bootloader by verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is available, skip BCR reset and PHY register setting to establish the PCIe link with bootloader - programmed PHY settings. Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao Reviewed-by: Manivannan Sadhasivam Tested-by: Aleksandrs Vinarskis --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 69 ++++++++++++++++++++---- 1 file changed, 59 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 38dbe690f2d5..23a57152e8fd 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2981,6 +2981,7 @@ struct qmp_pcie { =20 const struct qmp_phy_cfg *cfg; bool tcsr_4ln_config; + bool skip_init; =20 void __iomem *serdes; void __iomem *pcs; @@ -4229,18 +4230,38 @@ static int qmp_pcie_init(struct phy *phy) { struct qmp_pcie *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; + void __iomem *pcs =3D qmp->pcs; + bool phy_initialized =3D !!(readl(pcs + cfg->regs[QPHY_START_CTRL])); int ret; =20 + qmp->skip_init =3D qmp->nocsr_reset && phy_initialized; + /* + * We need to check the existence of init sequences in two cases: + * 1. The PHY doesn't support no_csr reset. + * 2. The PHY supports no_csr reset but isn't initialized by bootloader. + * As we can't skip init in these two cases. + */ + if (!qmp->skip_init && !cfg->tbls.serdes_num) { + dev_err(qmp->dev, "Init sequence not available\n"); + return -ENODATA; + } + ret =3D regulator_bulk_enable(cfg->num_vregs, qmp->vregs); if (ret) { dev_err(qmp->dev, "failed to enable regulators, err=3D%d\n", ret); return ret; } =20 - ret =3D reset_control_bulk_assert(cfg->num_resets, qmp->resets); - if (ret) { - dev_err(qmp->dev, "reset assert failed\n"); - goto err_disable_regulators; + /* + * Toggle BCR reset for PHY that doesn't support no_csr reset or has not + * been initialized. + */ + if (!qmp->skip_init) { + ret =3D reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset assert failed\n"); + goto err_disable_regulators; + } } =20 ret =3D reset_control_assert(qmp->nocsr_reset); @@ -4251,10 +4272,12 @@ static int qmp_pcie_init(struct phy *phy) =20 usleep_range(200, 300); =20 - ret =3D reset_control_bulk_deassert(cfg->num_resets, qmp->resets); - if (ret) { - dev_err(qmp->dev, "reset deassert failed\n"); - goto err_assert_reset; + if (!qmp->skip_init) { + ret =3D reset_control_bulk_deassert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset deassert failed\n"); + goto err_assert_reset; + } } =20 ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); @@ -4264,7 +4287,8 @@ static int qmp_pcie_init(struct phy *phy) return 0; =20 err_assert_reset: - reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (!qmp->skip_init) + reset_control_bulk_assert(cfg->num_resets, qmp->resets); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); =20 @@ -4276,7 +4300,10 @@ static int qmp_pcie_exit(struct phy *phy) struct qmp_pcie *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; =20 - reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (qmp->nocsr_reset) + reset_control_assert(qmp->nocsr_reset); + else + reset_control_bulk_assert(cfg->num_resets, qmp->resets); =20 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); =20 @@ -4295,6 +4322,13 @@ static int qmp_pcie_power_on(struct phy *phy) unsigned int mask, val; int ret; =20 + /* + * Write CSR register for PHY that doesn't support no_csr reset or has not + * been initialized. + */ + if (qmp->skip_init) + goto skip_tbls_init; + qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); =20 @@ -4306,6 +4340,7 @@ static int qmp_pcie_power_on(struct phy *phy) qmp_pcie_init_registers(qmp, &cfg->tbls); qmp_pcie_init_registers(qmp, mode_tbls); =20 +skip_tbls_init: ret =3D clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); if (ret) return ret; @@ -4316,6 +4351,9 @@ static int qmp_pcie_power_on(struct phy *phy) goto err_disable_pipe_clk; } =20 + if (qmp->skip_init) + goto skip_serdes_start; + /* Pull PHY out of reset state */ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); =20 @@ -4325,6 +4363,7 @@ static int qmp_pcie_power_on(struct phy *phy) if (!cfg->skip_start_delay) usleep_range(1000, 1200); =20 +skip_serdes_start: status =3D pcs + cfg->regs[QPHY_PCS_STATUS]; mask =3D cfg->phy_status; ret =3D readl_poll_timeout(status, val, !(val & mask), 200, @@ -4349,6 +4388,15 @@ static int qmp_pcie_power_off(struct phy *phy) =20 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); =20 + /* + * While powering off the PHY, only qmp->nocsr_reset needs to be checked.= In + * this way, no matter whether the PHY settings were initially programmed= by + * bootloader or PHY driver itself, we can reuse them when PHY is powered= on + * next time. + */ + if (qmp->nocsr_reset) + goto skip_phy_deinit; + /* PHY reset */ qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); =20 @@ -4360,6 +4408,7 @@ static int qmp_pcie_power_off(struct phy *phy) qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); =20 +skip_phy_deinit: return 0; } =20 --=20 2.34.1