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charset="utf-8" From: Konrad Dybcio Decide the in-driver logic based on whether the nocsr reset is present and defer checking the appropriateness of that to dt-bindings to save on boilerplate. Reset controller APIs are fine consuming a nullptr, so no additional checks are necessary there. Signed-off-by: Konrad Dybcio Signed-off-by: Wenbin Yao Reviewed-by: Abel Vesa Reviewed-by: Manivannan Sadhasivam Reviewed-by: Philipp Zabel Tested-by: Aleksandrs Vinarskis --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 018bbb300830..38dbe690f2d5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2969,8 +2969,6 @@ struct qmp_phy_cfg { =20 bool skip_start_delay; =20 - bool has_nocsr_reset; - /* QMP PHY pipe clock interface rate */ unsigned long pipe_clock_rate; =20 @@ -3934,7 +3932,6 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pci= ephy_cfg =3D { =20 .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, .phy_status =3D PHYSTATUS_4_20, - .has_nocsr_reset =3D true, =20 /* 20MHz PHY AUX Clock */ .aux_clock_rate =3D 20000000, @@ -3967,7 +3964,6 @@ static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pci= ephy_cfg =3D { =20 .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, .phy_status =3D PHYSTATUS_4_20, - .has_nocsr_reset =3D true, =20 /* 20MHz PHY AUX Clock */ .aux_clock_rate =3D 20000000, @@ -4087,7 +4083,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_p= ciephy_cfg =3D { =20 .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, .phy_status =3D PHYSTATUS_4_20, - .has_nocsr_reset =3D true, }; =20 static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg =3D { @@ -4121,7 +4116,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_p= ciephy_cfg =3D { =20 .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, .phy_status =3D PHYSTATUS_4_20, - .has_nocsr_reset =3D true, }; =20 static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg =3D { @@ -4153,7 +4147,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_p= ciephy_cfg =3D { =20 .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, .phy_status =3D PHYSTATUS_4_20, - .has_nocsr_reset =3D true, }; =20 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_ph= y_cfg_tbls *tbls) @@ -4456,12 +4449,10 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp) if (ret) return dev_err_probe(dev, ret, "failed to get resets\n"); =20 - if (cfg->has_nocsr_reset) { - qmp->nocsr_reset =3D devm_reset_control_get_exclusive(dev, "phy_nocsr"); - if (IS_ERR(qmp->nocsr_reset)) - return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), - "failed to get no-csr reset\n"); - } + qmp->nocsr_reset =3D devm_reset_control_get_optional_exclusive(dev, "phy_= nocsr"); + if (IS_ERR(qmp->nocsr_reset)) + return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), + "failed to get no-csr reset\n"); =20 return 0; } --=20 2.34.1