From nobody Thu Dec 18 05:05:41 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A387254AE3; Wed, 19 Mar 2025 09:46:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742377570; cv=none; b=ZWbjlNNRc4rof/axt+HXm7Lo3Sz70N9gs91oPb7LYPl2k8HJrxXEGrB+hHCvCFtT7kfSBnFJYviTi6EPWd6Oqtoi0rRzPVXEpUbUTb6n/e/Q9Jjw95FmKQkUbEWuGRXjOI4/G+6ZMIgTGiq87xXVOUaUFbAeUaS3/VIiVtJynCY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742377570; c=relaxed/simple; bh=/xXKZhE9+J9fAIVasZrRXQSlyhPaJzX7SyRBOzgBURM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=K7vEVXbhjyvj5VZ8rEFJz2LHN8UXKwtWBJA50Nf2icgAfQ7XKRBtF72Vhz/UolwkuwijqBWedTWwLyWgc+u5tcFype4Dk/fq9oVcMG835UmL2X5QWB+v58UmtjrW+0QYvC5xd21/m7EM1uCccZLsEzar0yOYIB2EYLFXevUbA30= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=DI16SVqY; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="DI16SVqY" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52J4lnrq009949; Wed, 19 Mar 2025 09:45:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=YMWtAde+AIA TtoQu1c0JTXd5aufiwi0uF9FLFZ9OE1Y=; b=DI16SVqYKe46DGHfznatIC21Og2 53kF7I3cj4TPbwBgQNM6OsW+AJX0OzOQZ5wWBi+RiuX2WPzPbItGYK0Va1BhGOLe fJvqLxsAypSUB3mKOgrTOl3OT868Z5zO3kVfQttvXPcYM8FEYVYpUjX2xFxks9xN N//xFDZa3iivyJFCZINt/fmEvC+mp6uE6kAY2wGWWfxFCAzCRY8HWG8MW1Ea+bxv y1Bmzrz36+FyfAZ1GYBkvDY4Lq9gn9GTiQwVXF3d9ix3BhLnu6XfP9iUX0OGbY2d VQcrKEljHKgZzH3gjJSO0DU648IsvCiKRHdT49Fg6q9vua/alMfKa2h4tUw== Received: from aptaippmta01.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com [103.229.16.4]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45fdvxhya9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Mar 2025 09:45:54 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 52J9jp3N009819; Wed, 19 Mar 2025 09:45:51 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 45dk522xm0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Mar 2025 09:45:51 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 52J9jol6009812; Wed, 19 Mar 2025 09:45:51 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 52J9jo6A009811 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Mar 2025 09:45:50 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 4635958) id D10DD410A8; Wed, 19 Mar 2025 17:45:49 +0800 (CST) From: Wenbin Yao To: vkoul@kernel.org, kishon@kernel.org, p.zabel@pengutronix.de, dmitry.baryshkov@linaro.org, abel.vesa@linaro.org, quic_qianyu@quicinc.com, neil.armstrong@linaro.org, manivannan.sadhasivam@linaro.org, quic_devipriy@quicinc.com, konrad.dybcio@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org Cc: quic_wenbyao@quicinc.com Subject: [PATCH v6 1/2] phy: qcom: pcie: Determine has_nocsr_reset dynamically Date: Wed, 19 Mar 2025 17:45:43 +0800 Message-Id: <20250319094544.3980357-2-quic_wenbyao@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250319094544.3980357-1-quic_wenbyao@quicinc.com> References: <20250319094544.3980357-1-quic_wenbyao@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=SKhCVPvH c=1 sm=1 tr=0 ts=67da9252 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=M454jrZF5vaoT4nqUzEA:9 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 85CkeNxBL0xDMloLnO2dTnJlr_fVOEjb X-Proofpoint-GUID: 85CkeNxBL0xDMloLnO2dTnJlr_fVOEjb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-19_03,2025-03-17_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 spamscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 mlxscore=0 suspectscore=0 phishscore=0 impostorscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503190067 Content-Type: text/plain; charset="utf-8" From: Konrad Dybcio Decide the in-driver logic based on whether the nocsr reset is present and defer checking the appropriateness of that to dt-bindings to save on boilerplate. Reset controller APIs are fine consuming a nullptr, so no additional checks are necessary there. Signed-off-by: Konrad Dybcio Signed-off-by: Wenbin Yao Reviewed-by: Abel Vesa Reviewed-by: Manivannan Sadhasivam Reviewed-by: Philipp Zabel Tested-by: Aleksandrs Vinarskis --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 018bbb300830..38dbe690f2d5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2969,8 +2969,6 @@ struct qmp_phy_cfg { =20 bool skip_start_delay; =20 - bool has_nocsr_reset; - /* QMP PHY pipe clock interface rate */ unsigned long pipe_clock_rate; =20 @@ -3934,7 +3932,6 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pci= ephy_cfg =3D { =20 .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, .phy_status =3D PHYSTATUS_4_20, - .has_nocsr_reset =3D true, =20 /* 20MHz PHY AUX Clock */ .aux_clock_rate =3D 20000000, @@ -3967,7 +3964,6 @@ static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pci= ephy_cfg =3D { =20 .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, .phy_status =3D PHYSTATUS_4_20, - .has_nocsr_reset =3D true, =20 /* 20MHz PHY AUX Clock */ .aux_clock_rate =3D 20000000, @@ -4087,7 +4083,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_p= ciephy_cfg =3D { =20 .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, .phy_status =3D PHYSTATUS_4_20, - .has_nocsr_reset =3D true, }; =20 static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg =3D { @@ -4121,7 +4116,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_p= ciephy_cfg =3D { =20 .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, .phy_status =3D PHYSTATUS_4_20, - .has_nocsr_reset =3D true, }; =20 static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg =3D { @@ -4153,7 +4147,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_p= ciephy_cfg =3D { =20 .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, .phy_status =3D PHYSTATUS_4_20, - .has_nocsr_reset =3D true, }; =20 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_ph= y_cfg_tbls *tbls) @@ -4456,12 +4449,10 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp) if (ret) return dev_err_probe(dev, ret, "failed to get resets\n"); =20 - if (cfg->has_nocsr_reset) { - qmp->nocsr_reset =3D devm_reset_control_get_exclusive(dev, "phy_nocsr"); - if (IS_ERR(qmp->nocsr_reset)) - return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), - "failed to get no-csr reset\n"); - } + qmp->nocsr_reset =3D devm_reset_control_get_optional_exclusive(dev, "phy_= nocsr"); + if (IS_ERR(qmp->nocsr_reset)) + return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), + "failed to get no-csr reset\n"); =20 return 0; } --=20 2.34.1 From nobody Thu Dec 18 05:05:41 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 010932512E1; Wed, 19 Mar 2025 09:46:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742377568; cv=none; b=o9I87HowiIqPr9AjrjY4na5Y6lITer5o4jPlqWYTnt1pX2Iydta6KaRnbr+6dgNHzSyrlTwUcKc8jBw+RhHiwVmzo+0LMyQeF7S1yr+MHgb9FUkabtwltSfs4T60R388hi1JiqdsFF8B86UyXNKoWjNKU/OzyKs91iHf0BJ39mg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742377568; c=relaxed/simple; bh=bJra1Ygjo81KJO4dt1ppm/X8owAKMBepXSgDkSdtGaI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XE6I9Yga0wpxpkKx2QrtZe52gSRCgbeiPtfxC5h/b/cbqMGAP3KJePhdLg0XObL0xskscKgsB29rOoMpHVUIPHWlOAt+eDIDVp/A7rG8GfD4bGjyZWpwc8vwTqZaGR41jr/ovDzZEBioSEhT2H4C9QFgjMq11IfXEoE4Dejj6gs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=HWhTYyFU; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="HWhTYyFU" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52J4lhKD020628; Wed, 19 Mar 2025 09:45:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=SjbrJ+4y1th uhBq6GFJC4JU0gjub7Z7SSpdjeSiPx9Q=; b=HWhTYyFUFdT5F8r2MRWYKs058Np xiAaQnLqOH3FcFMw3C/W5sU+yeGATrbk0wtHNQ9A1YazaRTu+7yn+A2BIcB/x0vm 6HqBukNCyTcuFMcOaW3hL52cdTpXHQKXtJXwnNcCZJ8/A9PUvVzmxl0LXtc+nEEA 0GIQOSWaYvQq/MoccxvbsDYM3rNKJnQE7ZPU+iyfGN9XMZwVPcWagONGIjVwjDil yDWMpaOmPCuVdTifOt569pvyNbyYvG+9yaM3waIVNgqG68A7yoqNyBXz34PXdFOG 1iAo7vOYxiTRrmx0iZlzqbJc6hKM3oQS6QN3p6uIqdCVTRepicnipnfhJ/Q== Received: from aptaippmta02.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com [103.229.16.4]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45exx34v42-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Mar 2025 09:45:54 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 52J9jqmH031618; Wed, 19 Mar 2025 09:45:52 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 45dk9w2rd9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Mar 2025 09:45:52 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 52J9jqJm031606; Wed, 19 Mar 2025 09:45:52 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 52J9jqpn031605 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Mar 2025 09:45:52 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 4635958) id 4EB48410A5; Wed, 19 Mar 2025 17:45:51 +0800 (CST) From: Wenbin Yao To: vkoul@kernel.org, kishon@kernel.org, p.zabel@pengutronix.de, dmitry.baryshkov@linaro.org, abel.vesa@linaro.org, quic_qianyu@quicinc.com, neil.armstrong@linaro.org, manivannan.sadhasivam@linaro.org, quic_devipriy@quicinc.com, konrad.dybcio@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org Cc: quic_wenbyao@quicinc.com Subject: [PATCH v6 2/2] phy: qcom: qmp-pcie: Add PHY register retention support Date: Wed, 19 Mar 2025 17:45:44 +0800 Message-Id: <20250319094544.3980357-3-quic_wenbyao@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250319094544.3980357-1-quic_wenbyao@quicinc.com> References: <20250319094544.3980357-1-quic_wenbyao@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=b+uy4sGx c=1 sm=1 tr=0 ts=67da9252 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=tqIfmRrofTIwFCb1_2sA:9 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: bEGVUJTuPfgto-LHrKsapo7ZdXDx-p38 X-Proofpoint-GUID: bEGVUJTuPfgto-LHrKsapo7ZdXDx-p38 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-19_03,2025-03-17_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 priorityscore=1501 mlxscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 adultscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503190067 Content-Type: text/plain; charset="utf-8" From: Qiang Yu Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the whole PHY (hardware and register), no_csr reset only resets PHY hardware but retains register values, which means PHY setting can be skipped during PHY init if PCIe link is enabled in bootloader and only no_csr is toggled after that. Hence, determine whether the PHY has been enabled in bootloader by verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is available, skip BCR reset and PHY register setting to establish the PCIe link with bootloader - programmed PHY settings. Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao Reviewed-by: Manivannan Sadhasivam Tested-by: Aleksandrs Vinarskis --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 69 ++++++++++++++++++++---- 1 file changed, 59 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 38dbe690f2d5..23a57152e8fd 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2981,6 +2981,7 @@ struct qmp_pcie { =20 const struct qmp_phy_cfg *cfg; bool tcsr_4ln_config; + bool skip_init; =20 void __iomem *serdes; void __iomem *pcs; @@ -4229,18 +4230,38 @@ static int qmp_pcie_init(struct phy *phy) { struct qmp_pcie *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; + void __iomem *pcs =3D qmp->pcs; + bool phy_initialized =3D !!(readl(pcs + cfg->regs[QPHY_START_CTRL])); int ret; =20 + qmp->skip_init =3D qmp->nocsr_reset && phy_initialized; + /* + * We need to check the existence of init sequences in two cases: + * 1. The PHY doesn't support no_csr reset. + * 2. The PHY supports no_csr reset but isn't initialized by bootloader. + * As we can't skip init in these two cases. + */ + if (!qmp->skip_init && !cfg->tbls.serdes_num) { + dev_err(qmp->dev, "Init sequence not available\n"); + return -ENODATA; + } + ret =3D regulator_bulk_enable(cfg->num_vregs, qmp->vregs); if (ret) { dev_err(qmp->dev, "failed to enable regulators, err=3D%d\n", ret); return ret; } =20 - ret =3D reset_control_bulk_assert(cfg->num_resets, qmp->resets); - if (ret) { - dev_err(qmp->dev, "reset assert failed\n"); - goto err_disable_regulators; + /* + * Toggle BCR reset for PHY that doesn't support no_csr reset or has not + * been initialized. + */ + if (!qmp->skip_init) { + ret =3D reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset assert failed\n"); + goto err_disable_regulators; + } } =20 ret =3D reset_control_assert(qmp->nocsr_reset); @@ -4251,10 +4272,12 @@ static int qmp_pcie_init(struct phy *phy) =20 usleep_range(200, 300); =20 - ret =3D reset_control_bulk_deassert(cfg->num_resets, qmp->resets); - if (ret) { - dev_err(qmp->dev, "reset deassert failed\n"); - goto err_assert_reset; + if (!qmp->skip_init) { + ret =3D reset_control_bulk_deassert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset deassert failed\n"); + goto err_assert_reset; + } } =20 ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); @@ -4264,7 +4287,8 @@ static int qmp_pcie_init(struct phy *phy) return 0; =20 err_assert_reset: - reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (!qmp->skip_init) + reset_control_bulk_assert(cfg->num_resets, qmp->resets); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); =20 @@ -4276,7 +4300,10 @@ static int qmp_pcie_exit(struct phy *phy) struct qmp_pcie *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; =20 - reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (qmp->nocsr_reset) + reset_control_assert(qmp->nocsr_reset); + else + reset_control_bulk_assert(cfg->num_resets, qmp->resets); =20 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); =20 @@ -4295,6 +4322,13 @@ static int qmp_pcie_power_on(struct phy *phy) unsigned int mask, val; int ret; =20 + /* + * Write CSR register for PHY that doesn't support no_csr reset or has not + * been initialized. + */ + if (qmp->skip_init) + goto skip_tbls_init; + qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); =20 @@ -4306,6 +4340,7 @@ static int qmp_pcie_power_on(struct phy *phy) qmp_pcie_init_registers(qmp, &cfg->tbls); qmp_pcie_init_registers(qmp, mode_tbls); =20 +skip_tbls_init: ret =3D clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); if (ret) return ret; @@ -4316,6 +4351,9 @@ static int qmp_pcie_power_on(struct phy *phy) goto err_disable_pipe_clk; } =20 + if (qmp->skip_init) + goto skip_serdes_start; + /* Pull PHY out of reset state */ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); =20 @@ -4325,6 +4363,7 @@ static int qmp_pcie_power_on(struct phy *phy) if (!cfg->skip_start_delay) usleep_range(1000, 1200); =20 +skip_serdes_start: status =3D pcs + cfg->regs[QPHY_PCS_STATUS]; mask =3D cfg->phy_status; ret =3D readl_poll_timeout(status, val, !(val & mask), 200, @@ -4349,6 +4388,15 @@ static int qmp_pcie_power_off(struct phy *phy) =20 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); =20 + /* + * While powering off the PHY, only qmp->nocsr_reset needs to be checked.= In + * this way, no matter whether the PHY settings were initially programmed= by + * bootloader or PHY driver itself, we can reuse them when PHY is powered= on + * next time. + */ + if (qmp->nocsr_reset) + goto skip_phy_deinit; + /* PHY reset */ qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); =20 @@ -4360,6 +4408,7 @@ static int qmp_pcie_power_off(struct phy *phy) qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); =20 +skip_phy_deinit: return 0; } =20 --=20 2.34.1