From nobody Wed Dec 17 10:46:16 2025 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3DB2250C01 for ; Wed, 19 Mar 2025 03:32:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742355163; cv=none; b=g20JxvXHBXda67+6lnMXK+DeZq7jSYO3jAvwhYvhzg/C7v4NA5Las/TETSc2UpThhcKSvVaLmFax/dbVtZMNhXmc8LBXJyKS+kX0dioeg/VU+Me+2AIINOIr1nlSj3/+m9psE5aKscsa6aH2wQX7MTDH6xR8p62/GGK3TyEXF+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742355163; c=relaxed/simple; bh=AuhnF22lBIPI4J8+aDvGKlxpt8YZz4FYBxTZj4hFY/4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=H444NUpvTnkUvjFeGARPL4zYhchDeJaBDblKRt4B9tepUwfIBa3OZN/3tdovEb/zJ+ALzRuT1vmdl5LK8Nm49EzUmiijRnXESbPxC0Ro8GdHYuBU4Z7PWfOZhJ4GVrGB0LcI/wZEU5d4AnBvV9sS56BwJZnaMPkYJEhPHTT/W2w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.254]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4ZHZ1M1jMgzvWr9; Wed, 19 Mar 2025 11:28:39 +0800 (CST) Received: from kwepemd500013.china.huawei.com (unknown [7.221.188.12]) by mail.maildlp.com (Postfix) with ESMTPS id C64D01800B3; Wed, 19 Mar 2025 11:32:32 +0800 (CST) Received: from localhost.huawei.com (10.169.71.169) by kwepemd500013.china.huawei.com (7.221.188.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 19 Mar 2025 11:32:31 +0800 From: Yongbang Shi To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v7 drm-dp 8/9] drm/hisilicon/hibmc: Add MSI irq getting and requesting for HPD Date: Wed, 19 Mar 2025 11:24:34 +0800 Message-ID: <20250319032435.1119469-9-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250319032435.1119469-1-shiyongbang@huawei.com> References: <20250319032435.1119469-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemd500013.china.huawei.com (7.221.188.12) Content-Type: text/plain; charset="utf-8" From: Baihan Li To realize HPD feature, request irq for HPD , add its handler function. We use pci_alloc_irq_vectors() to get our msi irq, because we have two interrupts now. Signed-off-by: Baihan Li Signed-off-by: Yongbang Shi Reviewed-by: Dmitry Baryshkov --- ChangeLog: v4 -> v5: - remove pci_disable_msi() in hibmc_unload() --- drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h | 3 + .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 74 +++++++++++++++---- .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h | 3 + 3 files changed, 66 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h b/drivers/gpu/drm/= hisilicon/hibmc/dp/dp_reg.h index 5614b727a710..394b1e933c3a 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h @@ -99,6 +99,9 @@ =20 #define HIBMC_DP_TIMING_SYNC_CTRL 0xFF0 =20 +#define HIBMC_DP_INTSTAT 0x1e0724 +#define HIBMC_DP_INTCLR 0x1e0728 + /* dp serdes reg */ #define HIBMC_DP_HOST_OFFSET 0x10000 #define HIBMC_DP_LANE0_RATE_OFFSET 0x4 diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c b/drivers/gpu/= drm/hisilicon/hibmc/hibmc_drm_drv.c index 98b01c8aee8e..768b97f9e74a 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c @@ -32,6 +32,8 @@ =20 DEFINE_DRM_GEM_FOPS(hibmc_fops); =20 +static const char *g_irqs_names_map[HIBMC_MAX_VECTORS] =3D { "vblank", "hp= d" }; + static irqreturn_t hibmc_interrupt(int irq, void *arg) { struct drm_device *dev =3D (struct drm_device *)arg; @@ -49,6 +51,22 @@ static irqreturn_t hibmc_interrupt(int irq, void *arg) return IRQ_HANDLED; } =20 +static irqreturn_t hibmc_dp_interrupt(int irq, void *arg) +{ + struct drm_device *dev =3D (struct drm_device *)arg; + struct hibmc_drm_private *priv =3D to_hibmc_drm_private(dev); + u32 status; + + status =3D readl(priv->mmio + HIBMC_DP_INTSTAT); + if (status) { + priv->dp.irq_status =3D status; + writel(status, priv->mmio + HIBMC_DP_INTCLR); + return IRQ_WAKE_THREAD; + } + + return IRQ_HANDLED; +} + static int hibmc_dumb_create(struct drm_file *file, struct drm_device *dev, struct drm_mode_create_dumb *args) { @@ -251,15 +269,48 @@ static int hibmc_hw_init(struct hibmc_drm_private *pr= iv) return 0; } =20 -static int hibmc_unload(struct drm_device *dev) +static void hibmc_unload(struct drm_device *dev) { - struct pci_dev *pdev =3D to_pci_dev(dev->dev); - drm_atomic_helper_shutdown(dev); +} =20 - free_irq(pdev->irq, dev); +static int hibmc_msi_init(struct drm_device *dev) +{ + struct pci_dev *pdev =3D to_pci_dev(dev->dev); + char name[32] =3D {0}; + int valid_irq_num; + int irq; + int ret; =20 - pci_disable_msi(to_pci_dev(dev->dev)); + ret =3D pci_alloc_irq_vectors(pdev, HIBMC_MIN_VECTORS, + HIBMC_MAX_VECTORS, PCI_IRQ_MSI); + if (ret < 0) { + drm_err(dev, "enabling MSI failed: %d\n", ret); + return ret; + } + + valid_irq_num =3D ret; + + for (int i =3D 0; i < valid_irq_num; i++) { + snprintf(name, ARRAY_SIZE(name) - 1, "%s-%s-%s", + dev->driver->name, pci_name(pdev), g_irqs_names_map[i]); + + irq =3D pci_irq_vector(pdev, i); + + if (i) + /* PCI devices require shared interrupts. */ + ret =3D devm_request_threaded_irq(&pdev->dev, irq, + hibmc_dp_interrupt, + hibmc_dp_hpd_isr, + IRQF_SHARED, name, dev); + else + ret =3D devm_request_irq(&pdev->dev, irq, hibmc_interrupt, + IRQF_SHARED, name, dev); + if (ret) { + drm_err(dev, "install irq failed: %d\n", ret); + return ret; + } + } =20 return 0; } @@ -291,15 +342,10 @@ static int hibmc_load(struct drm_device *dev) goto err; } =20 - ret =3D pci_enable_msi(pdev); + ret =3D hibmc_msi_init(dev); if (ret) { - drm_warn(dev, "enabling MSI failed: %d\n", ret); - } else { - /* PCI devices require shared interrupts. */ - ret =3D request_irq(pdev->irq, hibmc_interrupt, IRQF_SHARED, - dev->driver->name, dev); - if (ret) - drm_warn(dev, "install irq failed: %d\n", ret); + drm_err(dev, "hibmc msi init failed, ret:%d\n", ret); + goto err; } =20 /* reset all the states of crtc/plane/encoder/connector */ @@ -375,7 +421,7 @@ static void hibmc_pci_remove(struct pci_dev *pdev) =20 static void hibmc_pci_shutdown(struct pci_dev *pdev) { - drm_atomic_helper_shutdown(pci_get_drvdata(pdev)); + hibmc_pci_remove(pdev); } =20 static const struct pci_device_id hibmc_pci_table[] =3D { diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h b/drivers/gpu/= drm/hisilicon/hibmc/hibmc_drm_drv.h index daed1330b961..274feabe7df0 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h @@ -22,6 +22,9 @@ =20 #include "dp/dp_hw.h" =20 +#define HIBMC_MIN_VECTORS 1 +#define HIBMC_MAX_VECTORS 2 + struct hibmc_vdac { struct drm_device *dev; struct drm_encoder encoder; --=20 2.33.0