From nobody Wed Dec 17 10:46:20 2025 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AB8924FC1F for ; Wed, 19 Mar 2025 03:32:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.191 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742355156; cv=none; b=BAn1KhxbOcgvIYShKQlqqASy9fIVYueGYH9Fdg4i1I0Rk2Z1nohi41l9AIkse34O6lH1gB14hUlxXGYxkU/LQVKUij7PmSMrayMu+uiVNkxp5X6CxaTgNtsvDBveBVcHucbz5A81dW7SuxyGfA2yCLQGG1bLnCYiSL6m+oSno/0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742355156; c=relaxed/simple; bh=GjKHDcfX1WzS5Nq9LTHvFc33LaA3kUg5zC7FEi8Gh74=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VzLFsEKAM7zyHNCA3Txd9+HgzxN8AHq2LTqGLmtsCGtK0gx9eSYgALBKZlXlXr4LC627W2tjES6ohQXrn610b1eE8aGsoBxWq9dzAS0ttR3jZa5Gnv1z0HC4vy3TYf2Wv7kyEUgS7LTzKIpxJmICFYWYCZzp8lUW4iWzpxh+y/o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.191 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.214]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4ZHZ0d4yxdz1g2F8; Wed, 19 Mar 2025 11:28:01 +0800 (CST) Received: from kwepemd500013.china.huawei.com (unknown [7.221.188.12]) by mail.maildlp.com (Postfix) with ESMTPS id 975441A016C; Wed, 19 Mar 2025 11:32:31 +0800 (CST) Received: from localhost.huawei.com (10.169.71.169) by kwepemd500013.china.huawei.com (7.221.188.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 19 Mar 2025 11:32:30 +0800 From: Yongbang Shi To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v7 drm-dp 7/9] drm/hisilicon/hibmc: Enable this hot plug detect of irq feature Date: Wed, 19 Mar 2025 11:24:33 +0800 Message-ID: <20250319032435.1119469-8-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250319032435.1119469-1-shiyongbang@huawei.com> References: <20250319032435.1119469-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemd500013.china.huawei.com (7.221.188.12) Content-Type: text/plain; charset="utf-8" From: Baihan Li Add HPD interrupt enable functions in drm framework, and also add detect_ctx functions. Because of the debouncing when HPD pulled out, add 200 ms delay in detect. Add link reset process to reset link status when a new connector pulgged in. Signed-off-by: Baihan Li Signed-off-by: Yongbang Shi Reviewed-by: Dmitry Baryshkov --- ChangeLog: v5 -> v6: - add detect_ctx with 200ms delay, suggested by Dmitry Baryshkov. v4 -> v5: - separate the vga part commit, suggested by Dmitry Baryshkov. v3 -> v4: - add link reset of rates and lanes in pre link training process, suggest= ed by Dmitry Baryshkov. - add vdac detect and connected/disconnected status to enable HPD process= , suggested by Dmitry Baryshkov. - remove a drm_client, suggested by Dmitry Baryshkov. - fix build errors reported by kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202502231304.BCzV4Y8D-lkp= @intel.com/ v2 -> v3: - remove mdelay(100) hpd function in ISR, suggested by Dmitry Baryshkov. - remove enble_display in ISR, suggested by Dmitry Baryshkov. - change drm_kms_helper_connector_hotplug_event() to drm_connector_helper_hpd_irq_event(), suggested by Dmitry Baryshkov. - move macros to dp_reg.h, suggested by Dmitry Baryshkov. - remove struct irqs, suggested by Dmitry Baryshkov. - split this patch into two parts, suggested by Dmitry Baryshkov. - add a drm client dev to handle HPD event. v1 -> v2: - optimizing the description in commit message, suggested by Dmitry Barys= hkov. - add mdelay(100) comments, suggested by Dmitry Baryshkov. - deleting display enable in hpd event, suggested by Dmitry Baryshkov. --- .../gpu/drm/hisilicon/hibmc/dp/dp_config.h | 1 + drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 36 ++++++++++++++++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h | 5 +++ .../gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c | 42 +++++++++++++++++++ .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h | 2 + 5 files changed, 86 insertions(+) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h b/drivers/gpu/d= rm/hisilicon/hibmc/dp/dp_config.h index c5feef8dc27d..08f9e1caf7fc 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h @@ -16,5 +16,6 @@ #define HIBMC_DP_SYNC_EN_MASK 0x3 #define HIBMC_DP_LINK_RATE_CAL 27 #define HIBMC_DP_SYNC_DELAY(lanes) ((lanes) =3D=3D 0x2 ? 86 : 46) +#define HIBMC_DP_INT_ENABLE 0xc =20 #endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.c index ce7cb07815b2..8f0daec7d174 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -189,6 +189,36 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) return 0; } =20 +void hibmc_dp_enable_int(struct hibmc_dp *dp) +{ + struct hibmc_dp_dev *dp_dev =3D dp->dp_dev; + + writel(HIBMC_DP_INT_ENABLE, dp_dev->base + HIBMC_DP_INTR_ENABLE); +} + +void hibmc_dp_disable_int(struct hibmc_dp *dp) +{ + struct hibmc_dp_dev *dp_dev =3D dp->dp_dev; + + writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE); + writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS); +} + +void hibmc_dp_hpd_cfg(struct hibmc_dp *dp) +{ + struct hibmc_dp_dev *dp_dev =3D dp->dp_dev; + + hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_SYNC_= LEN_SEL, 0x0); + hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_TIMER= _TIMEOUT, 0x1); + hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_M= IN_PULSE_NUM, 0x9); + writel(HIBMC_DP_HDCP, dp_dev->base + HIBMC_DP_HDCP_CFG); + writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE); + writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS); + writel(HIBMC_DP_INT_ENABLE, dp_dev->base + HIBMC_DP_INTR_ENABLE); + writel(HIBMC_DP_DPTX_RST, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL); + writel(HIBMC_DP_CLK_EN, dp_dev->base + HIBMC_DP_DPTX_CLK_CTRL); +} + void hibmc_dp_display_en(struct hibmc_dp *dp, bool enable) { struct hibmc_dp_dev *dp_dev =3D dp->dp_dev; @@ -227,6 +257,12 @@ int hibmc_dp_mode_set(struct hibmc_dp *dp, struct drm_= display_mode *mode) return 0; } =20 +void hibmc_dp_reset_link(struct hibmc_dp *dp) +{ + dp->dp_dev->link.status.clock_recovered =3D false; + dp->dp_dev->link.status.channel_equalized =3D false; +} + static const struct hibmc_dp_color_raw g_rgb_raw[] =3D { {CBAR_COLOR_BAR, 0x000, 0x000, 0x000}, {CBAR_WHITE, 0xfff, 0xfff, 0xfff}, diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.h index 83a53dae8012..665f5b166dfb 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h @@ -49,11 +49,16 @@ struct hibmc_dp { void __iomem *mmio; struct drm_dp_aux aux; struct hibmc_dp_cbar_cfg cfg; + u32 irq_status; }; =20 int hibmc_dp_hw_init(struct hibmc_dp *dp); int hibmc_dp_mode_set(struct hibmc_dp *dp, struct drm_display_mode *mode); void hibmc_dp_display_en(struct hibmc_dp *dp, bool enable); void hibmc_dp_set_cbar(struct hibmc_dp *dp, const struct hibmc_dp_cbar_cfg= *cfg); +void hibmc_dp_reset_link(struct hibmc_dp *dp); +void hibmc_dp_hpd_cfg(struct hibmc_dp *dp); +void hibmc_dp_enable_int(struct hibmc_dp *dp); +void hibmc_dp_disable_int(struct hibmc_dp *dp); =20 #endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c b/drivers/gpu/d= rm/hisilicon/hibmc/hibmc_drm_dp.c index 8d3c67dcb5b3..881066c1221a 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c @@ -13,6 +13,8 @@ #include "hibmc_drm_drv.h" #include "dp/dp_hw.h" =20 +#define DP_MASKED_SINK_HPD_PLUG_INT BIT(2) + static int hibmc_dp_connector_get_modes(struct drm_connector *connector) { struct hibmc_dp *dp =3D to_hibmc_dp(connector); @@ -33,14 +35,25 @@ static int hibmc_dp_connector_get_modes(struct drm_conn= ector *connector) return count; } =20 +static int hibmc_dp_detect(struct drm_connector *connector, + struct drm_modeset_acquire_ctx *ctx, bool force) +{ + mdelay(200); + + return drm_connector_helper_detect_from_ddc(connector, ctx, force); +} + static const struct drm_connector_helper_funcs hibmc_dp_conn_helper_funcs = =3D { .get_modes =3D hibmc_dp_connector_get_modes, + .detect_ctx =3D hibmc_dp_detect, }; =20 static int hibmc_dp_late_register(struct drm_connector *connector) { struct hibmc_dp *dp =3D to_hibmc_dp(connector); =20 + hibmc_dp_enable_int(dp); + return drm_dp_aux_register(&dp->aux); } =20 @@ -49,6 +62,8 @@ static void hibmc_dp_early_unregister(struct drm_connecto= r *connector) struct hibmc_dp *dp =3D to_hibmc_dp(connector); =20 drm_dp_aux_unregister(&dp->aux); + + hibmc_dp_disable_int(dp); } =20 static const struct drm_connector_funcs hibmc_dp_conn_funcs =3D { @@ -100,6 +115,31 @@ static const struct drm_encoder_helper_funcs hibmc_dp_= encoder_helper_funcs =3D { .atomic_disable =3D hibmc_dp_encoder_disable, }; =20 +irqreturn_t hibmc_dp_hpd_isr(int irq, void *arg) +{ + struct drm_device *dev =3D (struct drm_device *)arg; + struct hibmc_drm_private *priv =3D to_hibmc_drm_private(dev); + int idx; + + if (!drm_dev_enter(dev, &idx)) + return -ENODEV; + + if (priv->dp.irq_status & DP_MASKED_SINK_HPD_PLUG_INT) { + drm_dbg_dp(&priv->dev, "HPD IN isr occur!\n"); + hibmc_dp_hpd_cfg(&priv->dp); + } else { + drm_dbg_dp(&priv->dev, "HPD OUT isr occur!\n"); + hibmc_dp_reset_link(&priv->dp); + } + + if (dev->registered) + drm_connector_helper_hpd_irq_event(&priv->dp.connector); + + drm_dev_exit(idx); + + return IRQ_HANDLED; +} + int hibmc_dp_init(struct hibmc_drm_private *priv) { struct drm_device *dev =3D &priv->dev; @@ -140,5 +180,7 @@ int hibmc_dp_init(struct hibmc_drm_private *priv) =20 drm_connector_attach_encoder(connector, encoder); =20 + connector->polled =3D DRM_CONNECTOR_POLL_HPD; + return 0; } diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h b/drivers/gpu/= drm/hisilicon/hibmc/hibmc_drm_drv.h index bc89e4b9f4e3..daed1330b961 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h @@ -71,4 +71,6 @@ int hibmc_dp_init(struct hibmc_drm_private *priv); =20 void hibmc_debugfs_init(struct drm_connector *connector, struct dentry *ro= ot); =20 +irqreturn_t hibmc_dp_hpd_isr(int irq, void *arg); + #endif --=20 2.33.0