From nobody Wed Dec 17 10:46:19 2025 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A12824EF65 for ; Wed, 19 Mar 2025 03:32:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742355153; cv=none; b=tgKoEP9yEto52+9R/vqGqJHOzizLdRYnQrknqDzIopQ2DPRGckTZGJ5XdWHECAIUh877gkEUcekoExhEzoXv4hVgZZv21JObs4HukSm/8bTdzNi3vgHj3IVWeqnyPb4CwRgKFs7JGhPZvh1Ndk0ePfm2nm7CVx4+Z7XOlB1sDXY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742355153; c=relaxed/simple; bh=EJ1YPbiyHJndb+gi8uKI2tOqwTPmsGlwPm+hYsdfY4s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MuRT3pOrNG76KkPrcFGUHz6tuZB2Ua+ZG0uzCdUeJL7f9T+xC65qgo/InW2crbaj0ac5ikCqOwjFUGFmfJs+sO0rV9hT3gFaHS6zDz1ZfafDWd+8kXPZn84XAv4UFWthsoMf2QIAwfnlRLtc/mtcks4/NG+XiKF7TW6D3P9tJmY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.214]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4ZHZ221Y7mz2Ccfg; Wed, 19 Mar 2025 11:29:14 +0800 (CST) Received: from kwepemd500013.china.huawei.com (unknown [7.221.188.12]) by mail.maildlp.com (Postfix) with ESMTPS id F391E1A016C; Wed, 19 Mar 2025 11:32:27 +0800 (CST) Received: from localhost.huawei.com (10.169.71.169) by kwepemd500013.china.huawei.com (7.221.188.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 19 Mar 2025 11:32:26 +0800 From: Yongbang Shi To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v7 drm-dp 4/9] drm/hisilicon/hibmc: Refactor the member of drm_aux in struct hibmc_dp Date: Wed, 19 Mar 2025 11:24:30 +0800 Message-ID: <20250319032435.1119469-5-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250319032435.1119469-1-shiyongbang@huawei.com> References: <20250319032435.1119469-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemd500013.china.huawei.com (7.221.188.12) Content-Type: text/plain; charset="utf-8" From: Baihan Li Because the drm_aux of struct hibmc_dp_dev's member is not easy to get in hibmc_drm_dp.c, move the drm_aux to struct hibmc_dp. Then there are some adaptations and modifications to make this patch compile. Signed-off-by: Baihan Li Signed-off-by: Yongbang Shi Reviewed-by: Dmitry Baryshkov --- ChangeLog: v3 -> v4: - fix the comment log to imperative sentence, suggested by Dmitry Baryshk= ov. v2 -> v3: - split the patch into two parts, suggested by Dmitry Baryshkov. --- drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c | 13 +++++++----- drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h | 6 ++++-- drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 2 +- drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h | 2 ++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c | 22 ++++++++++---------- 5 files changed, 26 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c b/drivers/gpu/drm/= hisilicon/hibmc/dp/dp_aux.c index 0a903cce1fa9..ded9e7ce887a 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c @@ -8,6 +8,7 @@ #include #include "dp_comm.h" #include "dp_reg.h" +#include "dp_hw.h" =20 #define HIBMC_AUX_CMD_REQ_LEN GENMASK(7, 4) #define HIBMC_AUX_CMD_ADDR GENMASK(27, 8) @@ -124,7 +125,8 @@ static int hibmc_dp_aux_parse_xfer(struct hibmc_dp_dev = *dp, struct drm_dp_aux_ms /* ret >=3D 0 ,ret is size; ret < 0, ret is err code */ static ssize_t hibmc_dp_aux_xfer(struct drm_dp_aux *aux, struct drm_dp_aux= _msg *msg) { - struct hibmc_dp_dev *dp =3D container_of(aux, struct hibmc_dp_dev, aux); + struct hibmc_dp *dp_priv =3D container_of(aux, struct hibmc_dp, aux); + struct hibmc_dp_dev *dp =3D dp_priv->dp_dev; u32 aux_cmd; int ret; u32 val; /* val will be assigned at the beginning of readl_poll_timeout f= unction */ @@ -151,14 +153,15 @@ static ssize_t hibmc_dp_aux_xfer(struct drm_dp_aux *a= ux, struct drm_dp_aux_msg * return hibmc_dp_aux_parse_xfer(dp, msg); } =20 -void hibmc_dp_aux_init(struct hibmc_dp_dev *dp) +void hibmc_dp_aux_init(struct hibmc_dp *dp) { - hibmc_dp_reg_write_field(dp, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_SYNC_LEN_= SEL, 0x0); - hibmc_dp_reg_write_field(dp, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_TIMER_TIM= EOUT, 0x1); - hibmc_dp_reg_write_field(dp, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_MIN_PULSE= _NUM, + hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_S= YNC_LEN_SEL, 0x0); + hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_T= IMER_TIMEOUT, 0x1); + hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_M= IN_PULSE_NUM, HIBMC_DP_MIN_PULSE_NUM); =20 dp->aux.transfer =3D hibmc_dp_aux_xfer; dp->aux.is_remote =3D 0; drm_dp_aux_init(&dp->aux); + dp->dp_dev->aux =3D &dp->aux; } diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_comm.h index e0c6a3b7463b..4add05c7f161 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h @@ -13,6 +13,8 @@ #include #include =20 +#include "dp_hw.h" + #define HIBMC_DP_LANE_NUM_MAX 2 =20 struct hibmc_link_status { @@ -32,7 +34,7 @@ struct hibmc_dp_link { }; =20 struct hibmc_dp_dev { - struct drm_dp_aux aux; + struct drm_dp_aux *aux; struct drm_device *dev; void __iomem *base; struct mutex lock; /* protects concurrent RW in hibmc_dp_reg_write_field(= ) */ @@ -58,7 +60,7 @@ struct hibmc_dp_dev { mutex_unlock(&_dp->lock); \ } while (0) =20 -void hibmc_dp_aux_init(struct hibmc_dp_dev *dp); +void hibmc_dp_aux_init(struct hibmc_dp *dp); int hibmc_dp_link_training(struct hibmc_dp_dev *dp); int hibmc_dp_serdes_init(struct hibmc_dp_dev *dp); int hibmc_dp_serdes_rate_switch(u8 rate, struct hibmc_dp_dev *dp); diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.c index dcb2ab5ea6bb..aa9354a996c9 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -167,7 +167,7 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) dp_dev->dev =3D drm_dev; dp_dev->base =3D dp->mmio + HIBMC_DP_OFFSET; =20 - hibmc_dp_aux_init(dp_dev); + hibmc_dp_aux_init(dp); =20 ret =3D hibmc_dp_serdes_init(dp_dev); if (ret) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.h index 4dc13b3d9875..53b6d0beecea 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h @@ -10,6 +10,7 @@ #include #include #include +#include =20 struct hibmc_dp_dev; =20 @@ -19,6 +20,7 @@ struct hibmc_dp { struct drm_encoder encoder; struct drm_connector connector; void __iomem *mmio; + struct drm_dp_aux aux; }; =20 int hibmc_dp_hw_init(struct hibmc_dp *dp); diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_link.c index 2b4940ea809c..f80e1d82511b 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c @@ -42,7 +42,7 @@ static int hibmc_dp_link_training_configure(struct hibmc_= dp_dev *dp) /* set rate and lane count */ buf[0] =3D dp->link.cap.link_rate; buf[1] =3D DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes; - ret =3D drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); + ret =3D drm_dp_dpcd_write(dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); if (ret !=3D sizeof(buf)) { drm_dbg_dp(dp->dev, "dp aux write link rate and lanes failed, ret: %d\n"= , ret); return ret >=3D 0 ? -EIO : ret; @@ -51,7 +51,7 @@ static int hibmc_dp_link_training_configure(struct hibmc_= dp_dev *dp) /* set 8b/10b and downspread */ buf[0] =3D DP_SPREAD_AMP_0_5; buf[1] =3D DP_SET_ANSI_8B10B; - ret =3D drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, sizeof(buf)); + ret =3D drm_dp_dpcd_write(dp->aux, DP_DOWNSPREAD_CTRL, buf, sizeof(buf)); if (ret !=3D sizeof(buf)) { drm_dbg_dp(dp->dev, "dp aux write 8b/10b and downspread failed, ret: %d\= n", ret); return ret >=3D 0 ? -EIO : ret; @@ -96,7 +96,7 @@ static int hibmc_dp_link_set_pattern(struct hibmc_dp_dev = *dp, int pattern) =20 hibmc_dp_reg_write_field(dp, HIBMC_DP_PHYIF_CTRL0, HIBMC_DP_CFG_PAT_SEL, = val); =20 - ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_PATTERN_SET, &buf, sizeof= (buf)); + ret =3D drm_dp_dpcd_write(dp->aux, DP_TRAINING_PATTERN_SET, &buf, sizeof(= buf)); if (ret !=3D sizeof(buf)) { drm_dbg_dp(dp->dev, "dp aux write training pattern set failed\n"); return ret >=3D 0 ? -EIO : ret; @@ -126,7 +126,7 @@ static int hibmc_dp_link_training_cr_pre(struct hibmc_d= p_dev *dp) if (ret) return ret; =20 - ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set, dp-= >link.cap.lanes); + ret =3D drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->= link.cap.lanes); if (ret !=3D dp->link.cap.lanes) { drm_dbg_dp(dp->dev, "dp aux write training lane set failed\n"); return ret >=3D 0 ? -EIO : ret; @@ -199,9 +199,9 @@ static int hibmc_dp_link_training_cr(struct hibmc_dp_de= v *dp) =20 voltage_tries =3D 1; for (cr_tries =3D 0; cr_tries < 80; cr_tries++) { - drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd); + drm_dp_link_train_clock_recovery_delay(dp->aux, dp->dpcd); =20 - ret =3D drm_dp_dpcd_read_link_status(&dp->aux, lane_status); + ret =3D drm_dp_dpcd_read_link_status(dp->aux, lane_status); if (ret !=3D DP_LINK_STATUS_SIZE) { drm_err(dp->dev, "Get lane status failed\n"); return ret; @@ -225,7 +225,7 @@ static int hibmc_dp_link_training_cr(struct hibmc_dp_de= v *dp) if (ret) return ret; =20 - ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->link.trai= n_set, + ret =3D drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, dp->link.train= _set, dp->link.cap.lanes); if (ret !=3D dp->link.cap.lanes) { drm_dbg_dp(dp->dev, "Update link training failed\n"); @@ -252,9 +252,9 @@ static int hibmc_dp_link_training_channel_eq(struct hib= mc_dp_dev *dp) return ret; =20 for (eq_tries =3D 0; eq_tries < HIBMC_EQ_MAX_RETRY; eq_tries++) { - drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); + drm_dp_link_train_channel_eq_delay(dp->aux, dp->dpcd); =20 - ret =3D drm_dp_dpcd_read_link_status(&dp->aux, lane_status); + ret =3D drm_dp_dpcd_read_link_status(dp->aux, lane_status); if (ret !=3D DP_LINK_STATUS_SIZE) { drm_err(dp->dev, "get lane status failed\n"); break; @@ -279,7 +279,7 @@ static int hibmc_dp_link_training_channel_eq(struct hib= mc_dp_dev *dp) if (ret) return ret; =20 - ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, + ret =3D drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, dp->link.train_set, dp->link.cap.lanes); if (ret !=3D dp->link.cap.lanes) { drm_dbg_dp(dp->dev, "Update link training failed\n"); @@ -319,7 +319,7 @@ int hibmc_dp_link_training(struct hibmc_dp_dev *dp) struct hibmc_dp_link *link =3D &dp->link; int ret; =20 - ret =3D drm_dp_read_dpcd_caps(&dp->aux, dp->dpcd); + ret =3D drm_dp_read_dpcd_caps(dp->aux, dp->dpcd); if (ret) drm_err(dp->dev, "dp aux read dpcd failed, ret: %d\n", ret); =20 --=20 2.33.0