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[87.10.75.167]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d43f6bf09sm22565005e9.26.2025.03.19.08.46.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Mar 2025 08:46:50 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Wed, 19 Mar 2025 16:45:31 +0100 Subject: [PATCH v3] iio: dac: ad3552r-hs: add debugfs reg access Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250319-wip-bl-ad3552r-fixes-v3-1-9975b38c0082@baylibre.com> X-B4-Tracking: v=1; b=H4sIAJrm2mcC/42NwQ6CMBBEf4X07Bq62CKe/A/joWW30gSFtKZKC P9u4ehFj28m82YWkYPnKE7FLAInH/3wyFDtCtF25nFj8JRZYImqrGQDLz+C7cFQpRQGcP7NEQ7 OWm6IJKEVeToG3oq8vFwzdz4+hzBtL0mu6Q9hkiChdbIk7QwrNGdrpt7bwPt2uIvVmfAfD2YPa qUtka7rI395lmX5AGECNvADAQAA X-Change-ID: 20250319-wip-bl-ad3552r-fixes-4fbbe9dd1d2b To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Angelo Dureghello , =?utf-8?q?Nuno_S=C3=A1?= X-Mailer: b4 0.14.2 From: Angelo Dureghello Add debugfs register access. Reviewed-by: Nuno S=C3=A1 Signed-off-by: Angelo Dureghello Reviewed-by: David Lechner --- Changes in v3: - remove unneeded debugfs include, - move max_reg_addr in model info structure, - set read size to 8 bit, always. - Link to v2: https://lore.kernel.org/r/20250319-wip-bl-ad3552r-fixes-v2-1-= 2656bdd6778e@baylibre.com Changes in v2: - set reg size setup as inline. - Link to v1: https://lore.kernel.org/r/20250319-wip-bl-ad3552r-fixes-v1-1-= cf10d6fae52a@baylibre.com --- drivers/iio/dac/ad3552r-common.c | 4 ++++ drivers/iio/dac/ad3552r-hs.c | 20 ++++++++++++++++++++ drivers/iio/dac/ad3552r.h | 1 + 3 files changed, 25 insertions(+) diff --git a/drivers/iio/dac/ad3552r-common.c b/drivers/iio/dac/ad3552r-com= mon.c index b8807e54fa057fe02afd9734ad67a4eb0a498e3a..38baaea0e6c85cba7ac6f334a3c= 31c7be88ac780 100644 --- a/drivers/iio/dac/ad3552r-common.c +++ b/drivers/iio/dac/ad3552r-common.c @@ -43,6 +43,7 @@ const struct ad3552r_model_data ad3541r_model_data =3D { .num_ranges =3D ARRAY_SIZE(ad3542r_ch_ranges), .requires_output_range =3D true, .num_spi_data_lanes =3D 2, + .max_reg_addr =3D 0x46, }; EXPORT_SYMBOL_NS_GPL(ad3541r_model_data, "IIO_AD3552R"); =20 @@ -54,6 +55,7 @@ const struct ad3552r_model_data ad3542r_model_data =3D { .num_ranges =3D ARRAY_SIZE(ad3542r_ch_ranges), .requires_output_range =3D true, .num_spi_data_lanes =3D 2, + .max_reg_addr =3D 0x49, }; EXPORT_SYMBOL_NS_GPL(ad3542r_model_data, "IIO_AD3552R"); =20 @@ -65,6 +67,7 @@ const struct ad3552r_model_data ad3551r_model_data =3D { .num_ranges =3D ARRAY_SIZE(ad3552r_ch_ranges), .requires_output_range =3D false, .num_spi_data_lanes =3D 4, + .max_reg_addr =3D 0x46, }; EXPORT_SYMBOL_NS_GPL(ad3551r_model_data, "IIO_AD3552R"); =20 @@ -76,6 +79,7 @@ const struct ad3552r_model_data ad3552r_model_data =3D { .num_ranges =3D ARRAY_SIZE(ad3552r_ch_ranges), .requires_output_range =3D false, .num_spi_data_lanes =3D 4, + .max_reg_addr =3D 0x49, }; EXPORT_SYMBOL_NS_GPL(ad3552r_model_data, "IIO_AD3552R"); =20 diff --git a/drivers/iio/dac/ad3552r-hs.c b/drivers/iio/dac/ad3552r-hs.c index cd8dabb60c5548780f0fce5d1b68c494cd71321d..37397e188f225a8099745ec03f7= c604da76960b1 100644 --- a/drivers/iio/dac/ad3552r-hs.c +++ b/drivers/iio/dac/ad3552r-hs.c @@ -464,6 +464,25 @@ static int ad3552r_hs_setup_custom_gain(struct ad3552r= _hs_state *st, gain, 1); } =20 +static int ad3552r_hs_reg_access(struct iio_dev *indio_dev, unsigned int r= eg, + unsigned int writeval, unsigned int *readval) +{ + struct ad3552r_hs_state *st =3D iio_priv(indio_dev); + + if (reg > st->model_data->max_reg_addr) + return -EINVAL; + + /* + * There are 8, 16 or 24 bit registers, but HDL supports only reading 8 + * or 16 bit data, not 24. So, also to avoid to check any proper read + * alignment, supporting only 8-bit readings here. + */ + if (readval) + return ad3552r_hs_reg_read(st, reg, readval, 1); + + return st->data->bus_reg_write(st->back, reg, writeval, 1); +} + static int ad3552r_hs_setup(struct ad3552r_hs_state *st) { u16 id; @@ -639,6 +658,7 @@ static const struct iio_chan_spec ad3552r_hs_channels[]= =3D { static const struct iio_info ad3552r_hs_info =3D { .read_raw =3D &ad3552r_hs_read_raw, .write_raw =3D &ad3552r_hs_write_raw, + .debugfs_reg_access =3D &ad3552r_hs_reg_access, }; =20 static int ad3552r_hs_probe(struct platform_device *pdev) diff --git a/drivers/iio/dac/ad3552r.h b/drivers/iio/dac/ad3552r.h index 768fa264d39e9e6d517aeb4098382e072f153543..9bb46a9e07a586d407a400094f1= 872ea79836dc3 100644 --- a/drivers/iio/dac/ad3552r.h +++ b/drivers/iio/dac/ad3552r.h @@ -156,6 +156,7 @@ struct ad3552r_model_data { int num_ranges; bool requires_output_range; int num_spi_data_lanes; + int max_reg_addr; }; =20 struct ad3552r_ch_data { --- base-commit: 6f9141cdd726e82d209b5fc6d6b5ea32ace339f1 change-id: 20250319-wip-bl-ad3552r-fixes-4fbbe9dd1d2b Best regards, --=20 Angelo Dureghello