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Tue, 18 Mar 2025 00:51:43 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20250318005143epsmtrp2a0619270116f5df2fab464d93f2c13aa~tv2yUVvlv0272102721epsmtrp2d; Tue, 18 Mar 2025 00:51:43 +0000 (GMT) X-AuditID: b6c32a47-f91c170000005659-17-67d8c3a092a5 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id BF.BC.18729.F93C8D76; Tue, 18 Mar 2025 09:51:43 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.126]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250318005143epsmtip29e684ab53bd42196e63f4deb4d6484e4~tv2yHS7i-0595105951epsmtip2K; Tue, 18 Mar 2025 00:51:43 +0000 (GMT) From: Sangwook Shin To: krzk@kernel.org, alim.akhtar@samsung.com, wim@linux-watchdog.org, linux@roeck-us.net Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Kyunghwan Seo , Sangwook Shin Subject: [PATCH v2] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC Date: Tue, 18 Mar 2025 09:44:12 +0900 Message-Id: <20250318004411.695786-1-sw617.shin@samsung.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <9c94a771-b3e6-4ba4-9b7f-dcd93b53f924@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprLJsWRmVeSWpSXmKPExsWy7bCmqe6CwzfSDSaflbd4MG8bm8X89kuM FufPb2C32PT4GqvF5V1z2CxmnN/HZHFj3T52iycLzzBZzFh8ks3i8ct/zA5cHptWdbJ5rFyz htVj85J6j53fG9g9+rasYvT4vEkugC0q2yYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ 0sJcSSEvMTfVVsnFJ0DXLTMH6DIlhbLEnFKgUEBicbGSvp1NUX5pSapCRn5xia1SakFKToF5 gV5xYm5xaV66Xl5qiZWhgYGRKVBhQnbGxHUeBdeFKt5v6WJvYHzC38XIwSEhYCIx4TZPFyMX h5DADkaJqwuvsEA4nxglbuzdywjhfGOUuLDvK5DDCdax+NcadojEXkaJY3NfMsO1vPkzmwWk ik1AR2L6v9tgtohAlMTBHcvAOpgF7jBK7Pv/ghkkISwQKbFi0lRWEJtFQFXiQsd+sAZeARuJ lq2rmSHWyUvMvPSdHeRYTgE7iXtHPCFKBCVOznwCVs4MVNK8dTbYERICnRwSp1ftZ4PodZH4 vvAHK4QtLPHq+BZ2CFtK4vO7vWyQAMiXOPVEGKK3gVHiXfN7qF57iUVnfoLtZRbQlFi/Sx+i XFniyC2otXwSHYf/skOEeSU62oQgGlUkOn5uZoVZdPTMA6ilHhLHZn5ngwTVREaJR1vPME5g VJiF5JtZSL6ZhbB4ASPzKkax1ILi3PTUYqMCY3j8JufnbmIEp1Mt9x2MM95+0DvEyMTBeIhR goNZSYTX/cn1dCHelMTKqtSi/Pii0pzU4kOMpsCgnsgsJZqcD0zoeSXxhiaWBiZmZobmRqYG 5krivNU7WtKFBNITS1KzU1MLUotg+pg4OKUamDiWXvLp67t1vd2Dwfpdd3MBV2DFpa1e/BIr VnWarlk6m/PyvP+ecjMmMDesPCd3WNjKaclitjMLuOubF57UmKXkPp35HvcpkWSmj8fX69Va ivWIfVN+JtW49P6WK8955Q83TGpl/vZesXqavJTUYq8I33JWZ6ELi6Ycq3v+cEFJYq0Qp/iW vt9TnNQO5yTdfTpr4XumzZeaL0wNin5cI5oU9VaD+fhqd0+nRy01ayN8P5pLznbhFJIy++dW k2uYvbP07OctccL77gcyFCSbK0xUSpkXqrXvbPL9bCGjLzdUWpckT771ae3+1j3slmd/ciUY 7/qx7cRvYw2baGlLk0mW85fXMy0RsJVzdf/wXImlOCPRUIu5qDgRAMSwkuowBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRmVeSWpSXmKPExsWy7bCSvO78wzfSDR4eNLJ4MG8bm8X89kuM FufPb2C32PT4GqvF5V1z2CxmnN/HZHFj3T52iycLzzBZzFh8ks3i8ct/zA5cHptWdbJ5rFyz htVj85J6j53fG9g9+rasYvT4vEkugC2KyyYlNSezLLVI3y6BK2PiOo+C60IV77d0sTcwPuHv YuTkkBAwkVj8aw17FyMXh5DAbkaJ2Zses3UxcgAlpCTePbOEqBGWuN9yhBXEFhL4wCjxpkES xGYT0JGY/u82C4gtIhAncax9MzPIHGaBR4wSZ29MYgZJCAuES5yZeJQJxGYRUJW40LEfrIFX wEaiZetqZogF8hIzL31nB9nLKWAnce+IJ8QuW4lHu3rYIcoFJU7OfALWygxU3rx1NvMERoFZ SFKzkKQWMDKtYpRMLSjOTc8tNiwwzEst1ytOzC0uzUvXS87P3cQIDnstzR2M21d90DvEyMTB eIhRgoNZSYTX/cn1dCHelMTKqtSi/Pii0pzU4kOM0hwsSuK84i96U4QE0hNLUrNTUwtSi2Cy TBycUg1MdlvjxTgqFF46LTg9Izps57WX18z/PHGfOZdzqfH0C5ESco9mbZkZwv3jZ4Z4aJvR 5H9bTwrIzTMKWHTcuHyD0MYMHrfN4sEpaR6ieuKvGsUbHJ3CWtnj7/Z+ElkaaJn8Y8u9632X Xr/3jjzlt+GS6CLr3z2NR43s13JevaPdukXTZ3/EjxMi754YRRdMbbGfwDGR46ODU/HTk1Wt 29RPd8wN+7Wz8q/9Pt8EdvGtvO/FTX+96/E4wKTPeDNe4UjXHFXfzb+33d7NefzSwgMfzz1+ J5H/0TkyJzJsdg97b9PS9xUhJhXzRBItbQwPb2+UvKO6ZlKaytmt99epKyroXVCddCZfyblN StBlW9NnJZbijERDLeai4kQAzfm+kOoCAAA= X-CMS-MailID: 20250318005143epcas2p40ebb1954bed8890aaf8d0a641f710423 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250318005143epcas2p40ebb1954bed8890aaf8d0a641f710423 References: <9c94a771-b3e6-4ba4-9b7f-dcd93b53f924@kernel.org> From: Kyunghwan Seo Fix the PMU register bits for the ExynosAutoV920 SoC. This SoC has different bit information compared to its previous version, ExynosAutoV9, and we have made the necessary adjustments. rst_stat_bit: - ExynosAutoV920 cl0 : 0 - ExynosAutoV920 cl1 : 1 cnt_en_bit: - ExynosAutoV920 cl0 : 8 - ExynosAutoV920 cl1 : 8 Signed-off-by: Kyunghwan Seo Reviewed-by: Guenter Roeck Reviewed-by: Alim Akhtar Signed-off-by: Sangwook Shin --- v1 -> v2: Restore previous email history and tags. drivers/watchdog/s3c2410_wdt.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 30450e99e5e9..bdd81d8074b2 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -72,6 +72,8 @@ #define EXYNOS850_CLUSTER1_WDTRESET_BIT 23 #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25 #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24 +#define EXYNOSAUTOV920_CLUSTER0_WDTRESET_BIT 0 +#define EXYNOSAUTOV920_CLUSTER1_WDTRESET_BIT 1 =20 #define GS_CLUSTER0_NONCPU_OUT 0x1220 #define GS_CLUSTER1_NONCPU_OUT 0x1420 @@ -312,9 +314,9 @@ static const struct s3c2410_wdt_variant drv_data_exynos= autov920_cl0 =3D { .mask_bit =3D 2, .mask_reset_inv =3D true, .rst_stat_reg =3D EXYNOS5_RST_STAT_REG_OFFSET, - .rst_stat_bit =3D EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT, + .rst_stat_bit =3D EXYNOSAUTOV920_CLUSTER0_WDTRESET_BIT, .cnt_en_reg =3D EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT, - .cnt_en_bit =3D 7, + .cnt_en_bit =3D 8, .quirks =3D QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_DBGACK_BIT, @@ -325,9 +327,9 @@ static const struct s3c2410_wdt_variant drv_data_exynos= autov920_cl1 =3D { .mask_bit =3D 2, .mask_reset_inv =3D true, .rst_stat_reg =3D EXYNOS5_RST_STAT_REG_OFFSET, - .rst_stat_bit =3D EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT, + .rst_stat_bit =3D EXYNOSAUTOV920_CLUSTER1_WDTRESET_BIT, .cnt_en_reg =3D EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT, - .cnt_en_bit =3D 7, + .cnt_en_bit =3D 8, .quirks =3D QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_DBGACK_BIT, --=20 2.40.1