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(1F2EF046.nat.pool.telekom.hu. [31.46.240.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac314a481absm727454966b.155.2025.03.17.15.18.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 15:18:44 -0700 (PDT) Sender: Ingo Molnar From: Ingo Molnar To: linux-kernel@vger.kernel.org Cc: Juergen Gross , Stefano Stabellini , "Ahmed S . Darwish" , Andrew Cooper , "H . Peter Anvin" , John Ogness , Linus Torvalds , Peter Zijlstra , Borislav Petkov , Thomas Gleixner Subject: [PATCH 1/5] x86/cpuid: Refactor Date: Mon, 17 Mar 2025 23:18:20 +0100 Message-ID: <20250317221824.3738853-2-mingo@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250317221824.3738853-1-mingo@kernel.org> References: <20250317221824.3738853-1-mingo@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: "Ahmed S. Darwish" In preparation for future commits where CPUID headers will be expanded, refactor the CPUID header into: asm/cpuid/ =E2=94=9C=E2=94=80=E2=94=80 api.h =E2=94=94=E2=94=80=E2=94=80 types.h Move the CPUID data structures into and the access APIs into . Let be just an include of so that existing call sites do not break. Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish Signed-off-by: Ingo Molnar Cc: Andrew Cooper Cc: "H. Peter Anvin" Cc: John Ogness Cc: x86-cpuid@lists.linux.dev Link: https://lore.kernel.org/r/20250317164745.4754-3-darwi@linutronix.de --- arch/x86/include/asm/cpuid.h | 217 +--------------------------------= ------------------------ arch/x86/include/asm/cpuid/api.h | 208 +++++++++++++++++++++++++++++++++= +++++++++++++++++++++ arch/x86/include/asm/cpuid/types.h | 29 ++++++++ 3 files changed, 238 insertions(+), 216 deletions(-) diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h index a92e4b08820a..d5749b25fa10 100644 --- a/arch/x86/include/asm/cpuid.h +++ b/arch/x86/include/asm/cpuid.h @@ -1,223 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* - * CPUID-related helpers/definitions - */ =20 #ifndef _ASM_X86_CPUID_H #define _ASM_X86_CPUID_H =20 -#include -#include - -#include - -struct cpuid_regs { - u32 eax, ebx, ecx, edx; -}; - -enum cpuid_regs_idx { - CPUID_EAX =3D 0, - CPUID_EBX, - CPUID_ECX, - CPUID_EDX, -}; - -#define CPUID_LEAF_MWAIT 0x5 -#define CPUID_LEAF_DCA 0x9 -#define CPUID_LEAF_XSTATE 0x0d -#define CPUID_LEAF_TSC 0x15 -#define CPUID_LEAF_FREQ 0x16 -#define CPUID_LEAF_TILE 0x1d - -#ifdef CONFIG_X86_32 -bool have_cpuid_p(void); -#else -static inline bool have_cpuid_p(void) -{ - return true; -} -#endif -static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, - unsigned int *ecx, unsigned int *edx) -{ - /* ecx is often an input as well as an output. */ - asm volatile("cpuid" - : "=3Da" (*eax), - "=3Db" (*ebx), - "=3Dc" (*ecx), - "=3Dd" (*edx) - : "0" (*eax), "2" (*ecx) - : "memory"); -} - -#define native_cpuid_reg(reg) \ -static inline unsigned int native_cpuid_##reg(unsigned int op) \ -{ \ - unsigned int eax =3D op, ebx, ecx =3D 0, edx; \ - \ - native_cpuid(&eax, &ebx, &ecx, &edx); \ - \ - return reg; \ -} - -/* - * Native CPUID functions returning a single datum. - */ -native_cpuid_reg(eax) -native_cpuid_reg(ebx) -native_cpuid_reg(ecx) -native_cpuid_reg(edx) - -#ifdef CONFIG_PARAVIRT_XXL -#include -#else -#define __cpuid native_cpuid -#endif - -/* - * Generic CPUID function - * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx - * resulting in stale register contents being returned. - */ -static inline void cpuid(unsigned int op, - unsigned int *eax, unsigned int *ebx, - unsigned int *ecx, unsigned int *edx) -{ - *eax =3D op; - *ecx =3D 0; - __cpuid(eax, ebx, ecx, edx); -} - -/* Some CPUID calls want 'count' to be placed in ecx */ -static inline void cpuid_count(unsigned int op, int count, - unsigned int *eax, unsigned int *ebx, - unsigned int *ecx, unsigned int *edx) -{ - *eax =3D op; - *ecx =3D count; - __cpuid(eax, ebx, ecx, edx); -} - -/* - * CPUID functions returning a single datum - */ -static inline unsigned int cpuid_eax(unsigned int op) -{ - unsigned int eax, ebx, ecx, edx; - - cpuid(op, &eax, &ebx, &ecx, &edx); - - return eax; -} - -static inline unsigned int cpuid_ebx(unsigned int op) -{ - unsigned int eax, ebx, ecx, edx; - - cpuid(op, &eax, &ebx, &ecx, &edx); - - return ebx; -} - -static inline unsigned int cpuid_ecx(unsigned int op) -{ - unsigned int eax, ebx, ecx, edx; - - cpuid(op, &eax, &ebx, &ecx, &edx); - - return ecx; -} - -static inline unsigned int cpuid_edx(unsigned int op) -{ - unsigned int eax, ebx, ecx, edx; - - cpuid(op, &eax, &ebx, &ecx, &edx); - - return edx; -} - -static inline void __cpuid_read(unsigned int leaf, unsigned int subleaf, u= 32 *regs) -{ - regs[CPUID_EAX] =3D leaf; - regs[CPUID_ECX] =3D subleaf; - __cpuid(regs + CPUID_EAX, regs + CPUID_EBX, regs + CPUID_ECX, regs + CPUI= D_EDX); -} - -#define cpuid_subleaf(leaf, subleaf, regs) { \ - static_assert(sizeof(*(regs)) =3D=3D 16); \ - __cpuid_read(leaf, subleaf, (u32 *)(regs)); \ -} - -#define cpuid_leaf(leaf, regs) { \ - static_assert(sizeof(*(regs)) =3D=3D 16); \ - __cpuid_read(leaf, 0, (u32 *)(regs)); \ -} - -static inline void __cpuid_read_reg(unsigned int leaf, unsigned int sublea= f, - enum cpuid_regs_idx regidx, u32 *reg) -{ - u32 regs[4]; - - __cpuid_read(leaf, subleaf, regs); - *reg =3D regs[regidx]; -} - -#define cpuid_subleaf_reg(leaf, subleaf, regidx, reg) { \ - static_assert(sizeof(*(reg)) =3D=3D 4); \ - __cpuid_read_reg(leaf, subleaf, regidx, (u32 *)(reg)); \ -} - -#define cpuid_leaf_reg(leaf, regidx, reg) { \ - static_assert(sizeof(*(reg)) =3D=3D 4); \ - __cpuid_read_reg(leaf, 0, regidx, (u32 *)(reg)); \ -} - -static __always_inline bool cpuid_function_is_indexed(u32 function) -{ - switch (function) { - case 4: - case 7: - case 0xb: - case 0xd: - case 0xf: - case 0x10: - case 0x12: - case 0x14: - case 0x17: - case 0x18: - case 0x1d: - case 0x1e: - case 0x1f: - case 0x24: - case 0x8000001d: - return true; - } - - return false; -} - -#define for_each_possible_hypervisor_cpuid_base(function) \ - for (function =3D 0x40000000; function < 0x40010000; function +=3D 0x100) - -static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t lea= ves) -{ - uint32_t base, eax, signature[3]; - - for_each_possible_hypervisor_cpuid_base(base) { - cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); - - /* - * This must not compile to "call memcmp" because it's called - * from PVH early boot code before instrumentation is set up - * and memcmp() itself may be instrumented. - */ - if (!__builtin_memcmp(sig, signature, 12) && - (leaves =3D=3D 0 || ((eax - base) >=3D leaves))) - return base; - } - - return 0; -} +#include =20 #endif /* _ASM_X86_CPUID_H */ diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h new file mode 100644 index 000000000000..4d1da9cc8b6f --- /dev/null +++ b/arch/x86/include/asm/cpuid/api.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _ASM_X86_CPUID_API_H +#define _ASM_X86_CPUID_API_H + +#include +#include + +#include +#include + +/* + * Raw CPUID accessors + */ + +#ifdef CONFIG_X86_32 +bool have_cpuid_p(void); +#else +static inline bool have_cpuid_p(void) +{ + return true; +} +#endif +static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx) +{ + /* ecx is often an input as well as an output. */ + asm volatile("cpuid" + : "=3Da" (*eax), + "=3Db" (*ebx), + "=3Dc" (*ecx), + "=3Dd" (*edx) + : "0" (*eax), "2" (*ecx) + : "memory"); +} + +#define native_cpuid_reg(reg) \ +static inline unsigned int native_cpuid_##reg(unsigned int op) \ +{ \ + unsigned int eax =3D op, ebx, ecx =3D 0, edx; \ + \ + native_cpuid(&eax, &ebx, &ecx, &edx); \ + \ + return reg; \ +} + +/* + * Native CPUID functions returning a single datum. + */ +native_cpuid_reg(eax) +native_cpuid_reg(ebx) +native_cpuid_reg(ecx) +native_cpuid_reg(edx) + +#ifdef CONFIG_PARAVIRT_XXL +#include +#else +#define __cpuid native_cpuid +#endif + +/* + * Generic CPUID function + * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx + * resulting in stale register contents being returned. + */ +static inline void cpuid(unsigned int op, + unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx) +{ + *eax =3D op; + *ecx =3D 0; + __cpuid(eax, ebx, ecx, edx); +} + +/* Some CPUID calls want 'count' to be placed in ecx */ +static inline void cpuid_count(unsigned int op, int count, + unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx) +{ + *eax =3D op; + *ecx =3D count; + __cpuid(eax, ebx, ecx, edx); +} + +/* + * CPUID functions returning a single datum + */ + +static inline unsigned int cpuid_eax(unsigned int op) +{ + unsigned int eax, ebx, ecx, edx; + + cpuid(op, &eax, &ebx, &ecx, &edx); + + return eax; +} + +static inline unsigned int cpuid_ebx(unsigned int op) +{ + unsigned int eax, ebx, ecx, edx; + + cpuid(op, &eax, &ebx, &ecx, &edx); + + return ebx; +} + +static inline unsigned int cpuid_ecx(unsigned int op) +{ + unsigned int eax, ebx, ecx, edx; + + cpuid(op, &eax, &ebx, &ecx, &edx); + + return ecx; +} + +static inline unsigned int cpuid_edx(unsigned int op) +{ + unsigned int eax, ebx, ecx, edx; + + cpuid(op, &eax, &ebx, &ecx, &edx); + + return edx; +} + +static inline void __cpuid_read(unsigned int leaf, unsigned int subleaf, u= 32 *regs) +{ + regs[CPUID_EAX] =3D leaf; + regs[CPUID_ECX] =3D subleaf; + __cpuid(regs + CPUID_EAX, regs + CPUID_EBX, regs + CPUID_ECX, regs + CPUI= D_EDX); +} + +#define cpuid_subleaf(leaf, subleaf, regs) { \ + static_assert(sizeof(*(regs)) =3D=3D 16); \ + __cpuid_read(leaf, subleaf, (u32 *)(regs)); \ +} + +#define cpuid_leaf(leaf, regs) { \ + static_assert(sizeof(*(regs)) =3D=3D 16); \ + __cpuid_read(leaf, 0, (u32 *)(regs)); \ +} + +static inline void __cpuid_read_reg(unsigned int leaf, unsigned int sublea= f, + enum cpuid_regs_idx regidx, u32 *reg) +{ + u32 regs[4]; + + __cpuid_read(leaf, subleaf, regs); + *reg =3D regs[regidx]; +} + +#define cpuid_subleaf_reg(leaf, subleaf, regidx, reg) { \ + static_assert(sizeof(*(reg)) =3D=3D 4); \ + __cpuid_read_reg(leaf, subleaf, regidx, (u32 *)(reg)); \ +} + +#define cpuid_leaf_reg(leaf, regidx, reg) { \ + static_assert(sizeof(*(reg)) =3D=3D 4); \ + __cpuid_read_reg(leaf, 0, regidx, (u32 *)(reg)); \ +} + +static __always_inline bool cpuid_function_is_indexed(u32 function) +{ + switch (function) { + case 4: + case 7: + case 0xb: + case 0xd: + case 0xf: + case 0x10: + case 0x12: + case 0x14: + case 0x17: + case 0x18: + case 0x1d: + case 0x1e: + case 0x1f: + case 0x24: + case 0x8000001d: + return true; + } + + return false; +} + +#define for_each_possible_hypervisor_cpuid_base(function) \ + for (function =3D 0x40000000; function < 0x40010000; function +=3D 0x100) + +static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t lea= ves) +{ + uint32_t base, eax, signature[3]; + + for_each_possible_hypervisor_cpuid_base(base) { + cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); + + /* + * This must not compile to "call memcmp" because it's called + * from PVH early boot code before instrumentation is set up + * and memcmp() itself may be instrumented. + */ + if (!__builtin_memcmp(sig, signature, 12) && + (leaves =3D=3D 0 || ((eax - base) >=3D leaves))) + return base; + } + + return 0; +} + +#endif /* _ASM_X86_CPUID_API_H */ diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h new file mode 100644 index 000000000000..724002aaff4d --- /dev/null +++ b/arch/x86/include/asm/cpuid/types.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_CPUID_TYPES_H +#define _ASM_X86_CPUID_TYPES_H + +#include + +/* + * Types for raw CPUID access + */ + +struct cpuid_regs { + u32 eax, ebx, ecx, edx; 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(1F2EF046.nat.pool.telekom.hu. [31.46.240.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac314a481absm727454966b.155.2025.03.17.15.18.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 15:18:45 -0700 (PDT) Sender: Ingo Molnar From: Ingo Molnar To: linux-kernel@vger.kernel.org Cc: Juergen Gross , Stefano Stabellini , "Ahmed S . Darwish" , Andrew Cooper , "H . Peter Anvin" , John Ogness , Linus Torvalds , Peter Zijlstra , Borislav Petkov , Thomas Gleixner Subject: [PATCH 2/5] x86/cpuid: Clean up Date: Mon, 17 Mar 2025 23:18:21 +0100 Message-ID: <20250317221824.3738853-3-mingo@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250317221824.3738853-1-mingo@kernel.org> References: <20250317221824.3738853-1-mingo@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - We have 0x0d, 0x9 and 0x1d as literals for the CPUID_LEAF definitions, pick a single, consistent style of 0xZZ literals. - Likewise, harmonize the style of the 'struct cpuid_regs' list of registers with that of 'enum cpuid_regs_idx'. Because while computers don't care about unnecessary visual noise, humans do. Signed-off-by: Ingo Molnar Cc: Ahmed S. Darwish Cc: Andrew Cooper Cc: "H. Peter Anvin" Cc: John Ogness Cc: x86-cpuid@lists.linux.dev Link: https://lore.kernel.org/r/20250317164745.4754-3-darwi@linutronix.de --- arch/x86/include/asm/cpuid/types.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 724002aaff4d..8582e27e836d 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -5,11 +5,14 @@ #include =20 /* - * Types for raw CPUID access + * Types for raw CPUID access: */ =20 struct cpuid_regs { - u32 eax, ebx, ecx, edx; + u32 eax; + u32 ebx; + u32 ecx; + u32 edx; }; =20 enum cpuid_regs_idx { @@ -19,8 +22,8 @@ enum cpuid_regs_idx { CPUID_EDX, }; =20 -#define CPUID_LEAF_MWAIT 0x5 -#define CPUID_LEAF_DCA 0x9 +#define CPUID_LEAF_MWAIT 0x05 +#define CPUID_LEAF_DCA 0x09 #define CPUID_LEAF_XSTATE 0x0d #define CPUID_LEAF_TSC 0x15 #define CPUID_LEAF_FREQ 0x16 --=20 2.45.2 From nobody Wed Dec 17 11:57:32 2025 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D71B204F99 for ; Mon, 17 Mar 2025 22:18:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742249932; cv=none; b=DUFbtIAnJQAzEI6vILyvWchTL8Dt7CXZ9jtK2wmtZ2rSLO60CgzyyBViuVGRhNqraUCKM8ctRkD0XJdM6AAmTqEKzyfY2UZlstv54WgvaD7CjmsnzvNQfcB4ywewqH53yaTTpLRyrBIXqxS2bPLokWPG6rtcEe+2owjtYDLMcQs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742249932; c=relaxed/simple; bh=21hyvfAgw0UCXSu4Bb7SLxAPr3QZnlntthYvDyrDKoA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s+s2N6uQPM94RWVvGUh/m4nXp/+AEydqLACQPdx7Ddp72+2Gc58dYtikSp9tTvvnyCHPgSOJQQivpg0IuiXY7PbJ015kyfsXYFVchIiFVB8THz0j9WkpTDKfgJrZzYJHRobGKJ1CtBbfIAx6vKCqqDpCAfpx/yvdDe1yA6kSTzE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=kernel.org; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=aOpF6Xxw; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=kernel.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aOpF6Xxw" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-ac339f53df9so326268066b.1 for ; Mon, 17 Mar 2025 15:18:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742249929; x=1742854729; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:from:to:cc:subject:date :message-id:reply-to; bh=FGTDbMbl7rJNc1xMOaRIKrwNGnAZ9yjWyI/0GLpPStk=; b=aOpF6Xxwf0ZoCg8iZpSi6UtMNUaEdkehNUEk3s+C1q2oNWE6VFEFcFDwP3qCFpgTBg Y7O/QH3eZ3tPjp4TM/I6vQYlqGv9Q4xSu6x57Kb4chI6p4iDHLIGW9CpFJCxd1/047PV OgJbsnOH2RyeobHPKmXnyRkxEliaHmhkrWnqMprrLHbrhgWInsgzzFiKm50XprEN6FNF DHPLWA+qgsxlnXDiICrui6yBF9Y5zwWoBh/YeCnm6AGdPbz6eCG18IFGWAEOPfYWw1x1 reI8LVQZy5tDNCMbkVmkqhAcGTcgVk1R1GIc4WI1RDpf/q/fWosfD69vK5XiZknYa7Rl +9mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742249929; x=1742854729; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=FGTDbMbl7rJNc1xMOaRIKrwNGnAZ9yjWyI/0GLpPStk=; b=SVdoxhIxRkGPB4aJocYz9QaW82WbVtNIegoqj05qAF3JxA70Z3aivUUshoE6g37GHP IDLYViil4z6f8L1vBRDinr0v9mybN2esT7Vl76PBbHwomOnkm/0HR/M99cCLB/TOtBN8 Uwx3kZDylMTXgWuUjsZsJMTQ8GcgY/KHIeesW2xwU5XtDuzOEu2KwoXQn79noAmQJdk4 Oc5dIlVi9/pvwG50WQYanY+VMwtOoujf/K5LGktnG9BAtBaqOyrOE8EpQc/svtmGKOIq chTSz1VdNUp6KgSP8kd3rCfB0jUitVnAGPAuRCI78A5tVv4dEEfeaaTKaWEbXzTvR4uz 9Zkw== X-Gm-Message-State: AOJu0YwzkF2XmvI1NhZ1jrULOupVCENuakP32w0gjYC+EFaBF8yYp+Rs 9frQomg4a7ctW3onkt5VgSMM2nUcMl3rxj/WfUJmacxb1GzjIr8WdjWlvRak X-Gm-Gg: ASbGncvV/cVpLvlYMsH6/NVbzdNAoj096AmE0jq/VnpRCwGHhm4drFxq9YwN5I427Nn NqCBF10ZY/J+5+ICq1gmu8HrC9pt3G8Kgj0QZRxKIl04bb7bZWCsF7AdCODrdNJB5wf+adAbMCT 3m+rPB50D+DLurwLe4IsenpC2+mwJQSZhJhlb8pzgatLllCZYjQ8EIz+tlFgTMpb8O0MSEZMrhS qoOgHfFYJYF0LoTRch7e59SbP1p6Q1vmtYx6er3NtQl2pAjIADS2rnU10FjGZtoklTSIu2oercM IO2YmuxiCgU9RFY+B9JRttZHcIr23OgyKsR8EK1+ZUZswIQ87BARLNU35fynpnN8bQ== X-Google-Smtp-Source: AGHT+IGQzCbssnsxCRIDN7nP+aVnUTvQCvb9vk8Zvp+QnPkf9eOEfnjbK/mBdxUK7p+CX5VvjxvbAg== X-Received: by 2002:a17:907:2d89:b0:ac2:7fd5:774 with SMTP id a640c23a62f3a-ac33048970bmr1474047366b.56.1742249928451; Mon, 17 Mar 2025 15:18:48 -0700 (PDT) Received: from starship.. (1F2EF046.nat.pool.telekom.hu. [31.46.240.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac314a481absm727454966b.155.2025.03.17.15.18.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 15:18:47 -0700 (PDT) Sender: Ingo Molnar From: Ingo Molnar To: linux-kernel@vger.kernel.org Cc: Juergen Gross , Stefano Stabellini , "Ahmed S . Darwish" , Andrew Cooper , "H . Peter Anvin" , John Ogness , Linus Torvalds , Peter Zijlstra , Borislav Petkov , Thomas Gleixner Subject: [PATCH 3/5] x86/cpuid: Clean up Date: Mon, 17 Mar 2025 23:18:22 +0100 Message-ID: <20250317221824.3738853-4-mingo@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250317221824.3738853-1-mingo@kernel.org> References: <20250317221824.3738853-1-mingo@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Include first, as is customary. This also has the side effect of build-testing the header dependency assumptions in the types header. - No newline necessary after the SPDX line - Newline necessary after inline function definitions - Rename native_cpuid_reg() to NATIVE_CPUID_REG(): it's a CPP macro, whose name we capitalize in such cases. - Prettify the CONFIG_PARAVIRT_XXL inclusion block a bit - Standardize register references in comments to EAX/EBX/ECX/etc., from the hodgepodge of references. - s/cpus/CPUs because why add noise to common acronyms? - Use u32 instead of uint32_t in hypervisor_cpuid_base(). Yes, I realize uint32_t is used in Xen code, but this is a core x86 architecture header and we should standardize on the type that is being used overwhelmingly in x86 architecture code. The two types are the same so there should be no build warnings. Signed-off-by: Ingo Molnar Cc: Ahmed S. Darwish Cc: Andrew Cooper Cc: "H. Peter Anvin" Cc: John Ogness Cc: x86-cpuid@lists.linux.dev Link: https://lore.kernel.org/r/20250317164745.4754-3-darwi@linutronix.de --- arch/x86/include/asm/cpuid/api.h | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 4d1da9cc8b6f..f26926ba5289 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -1,16 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0 */ - #ifndef _ASM_X86_CPUID_API_H #define _ASM_X86_CPUID_API_H =20 +#include + #include #include =20 -#include #include =20 /* - * Raw CPUID accessors + * Raw CPUID accessors: */ =20 #ifdef CONFIG_X86_32 @@ -21,6 +21,7 @@ static inline bool have_cpuid_p(void) return true; } #endif + static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) { @@ -34,7 +35,7 @@ static inline void native_cpuid(unsigned int *eax, unsign= ed int *ebx, : "memory"); } =20 -#define native_cpuid_reg(reg) \ +#define NATIVE_CPUID_REG(reg) \ static inline unsigned int native_cpuid_##reg(unsigned int op) \ { \ unsigned int eax =3D op, ebx, ecx =3D 0, edx; \ @@ -45,22 +46,23 @@ static inline unsigned int native_cpuid_##reg(unsigned = int op) \ } =20 /* - * Native CPUID functions returning a single datum. + * Native CPUID functions returning a single datum: */ -native_cpuid_reg(eax) -native_cpuid_reg(ebx) -native_cpuid_reg(ecx) -native_cpuid_reg(edx) +NATIVE_CPUID_REG(eax) +NATIVE_CPUID_REG(ebx) +NATIVE_CPUID_REG(ecx) +NATIVE_CPUID_REG(edx) =20 #ifdef CONFIG_PARAVIRT_XXL -#include +# include #else -#define __cpuid native_cpuid +# define __cpuid native_cpuid #endif =20 /* * Generic CPUID function - * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx + * + * Clear ECX since some CPUs (Cyrix MII) do not set or clear ECX * resulting in stale register contents being returned. */ static inline void cpuid(unsigned int op, @@ -72,7 +74,7 @@ static inline void cpuid(unsigned int op, __cpuid(eax, ebx, ecx, edx); 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(1F2EF046.nat.pool.telekom.hu. [31.46.240.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac314a481absm727454966b.155.2025.03.17.15.18.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 15:18:49 -0700 (PDT) Sender: Ingo Molnar From: Ingo Molnar To: linux-kernel@vger.kernel.org Cc: Juergen Gross , Stefano Stabellini , "Ahmed S . Darwish" , Andrew Cooper , "H . Peter Anvin" , John Ogness , Linus Torvalds , Peter Zijlstra , Borislav Petkov , Thomas Gleixner Subject: [PATCH 4/5] x86/cpuid: Standardize on u32 in Date: Mon, 17 Mar 2025 23:18:23 +0100 Message-ID: <20250317221824.3738853-5-mingo@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250317221824.3738853-1-mingo@kernel.org> References: <20250317221824.3738853-1-mingo@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert all uses of 'unsigned int' to 'u32' in . This is how a lot of the call sites are doing it, and the two types are equivalent in the C sense - but 'u32' better expresses that these are expressions of an immutable hardware ABI. Signed-off-by: Ingo Molnar Cc: Ahmed S. Darwish Cc: Andrew Cooper Cc: "H. Peter Anvin" Cc: John Ogness Cc: x86-cpuid@lists.linux.dev Link: https://lore.kernel.org/r/20250317164745.4754-3-darwi@linutronix.de Reviewed-by: Xin Li (Intel) --- arch/x86/include/asm/cpuid/api.h | 40 ++++++++++++++++++++----------------= ---- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index f26926ba5289..356db1894588 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -22,8 +22,8 @@ static inline bool have_cpuid_p(void) } #endif =20 -static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, - unsigned int *ecx, unsigned int *edx) +static inline void native_cpuid(u32 *eax, u32 *ebx, + u32 *ecx, u32 *edx) { /* ecx is often an input as well as an output. */ asm volatile("cpuid" @@ -36,9 +36,9 @@ static inline void native_cpuid(unsigned int *eax, unsign= ed int *ebx, } =20 #define NATIVE_CPUID_REG(reg) \ -static inline unsigned int native_cpuid_##reg(unsigned int op) \ +static inline u32 native_cpuid_##reg(u32 op) \ { \ - unsigned int eax =3D op, ebx, ecx =3D 0, edx; \ + u32 eax =3D op, ebx, ecx =3D 0, edx; \ \ native_cpuid(&eax, &ebx, &ecx, &edx); \ \ @@ -65,9 +65,9 @@ NATIVE_CPUID_REG(edx) * Clear ECX since some CPUs (Cyrix MII) do not set or clear ECX * resulting in stale register contents being returned. */ -static inline void cpuid(unsigned int op, - unsigned int *eax, unsigned int *ebx, - unsigned int *ecx, unsigned int *edx) +static inline void cpuid(u32 op, + u32 *eax, u32 *ebx, + u32 *ecx, u32 *edx) { *eax =3D op; *ecx =3D 0; @@ -75,9 +75,9 @@ static inline void cpuid(unsigned int op, } =20 /* Some CPUID calls want 'count' to be placed in ECX */ -static inline void cpuid_count(unsigned int op, int count, - unsigned int *eax, unsigned int *ebx, - unsigned int *ecx, unsigned int *edx) +static inline void cpuid_count(u32 op, int count, + u32 *eax, u32 *ebx, + u32 *ecx, u32 *edx) { *eax =3D op; *ecx =3D count; @@ -88,43 +88,43 @@ static inline void cpuid_count(unsigned int op, int cou= nt, * CPUID functions returning a single datum: */ =20 -static inline unsigned int cpuid_eax(unsigned int op) +static inline u32 cpuid_eax(u32 op) { - unsigned int eax, ebx, ecx, edx; + u32 eax, ebx, ecx, edx; =20 cpuid(op, &eax, &ebx, &ecx, &edx); =20 return eax; } =20 -static inline unsigned int cpuid_ebx(unsigned int op) +static inline u32 cpuid_ebx(u32 op) { - unsigned int eax, ebx, ecx, edx; + u32 eax, ebx, ecx, edx; =20 cpuid(op, &eax, &ebx, &ecx, &edx); =20 return ebx; } =20 -static inline unsigned int cpuid_ecx(unsigned int op) +static inline u32 cpuid_ecx(u32 op) { - unsigned int eax, ebx, ecx, edx; + u32 eax, ebx, ecx, edx; =20 cpuid(op, &eax, &ebx, &ecx, &edx); =20 return ecx; } =20 -static inline unsigned int cpuid_edx(unsigned int op) +static inline u32 cpuid_edx(u32 op) { - unsigned int eax, ebx, ecx, edx; + u32 eax, ebx, ecx, edx; =20 cpuid(op, &eax, &ebx, &ecx, &edx); =20 return edx; } =20 -static inline void __cpuid_read(unsigned int leaf, unsigned int subleaf, u= 32 *regs) +static inline void __cpuid_read(u32 leaf, u32 subleaf, u32 *regs) { regs[CPUID_EAX] =3D leaf; regs[CPUID_ECX] =3D subleaf; @@ -141,7 +141,7 @@ static inline void __cpuid_read(unsigned int leaf, unsi= gned int subleaf, u32 *re __cpuid_read(leaf, 0, (u32 *)(regs)); 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(1F2EF046.nat.pool.telekom.hu. [31.46.240.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac314a481absm727454966b.155.2025.03.17.15.18.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 15:18:50 -0700 (PDT) Sender: Ingo Molnar From: Ingo Molnar To: linux-kernel@vger.kernel.org Cc: Juergen Gross , Stefano Stabellini , "Ahmed S . Darwish" , Andrew Cooper , "H . Peter Anvin" , John Ogness , Linus Torvalds , Peter Zijlstra , Borislav Petkov , Thomas Gleixner Subject: [PATCH 5/5] x86/cpuid: Use u32 in instead of uint32_t in Date: Mon, 17 Mar 2025 23:18:24 +0100 Message-ID: <20250317221824.3738853-6-mingo@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250317221824.3738853-1-mingo@kernel.org> References: <20250317221824.3738853-1-mingo@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use u32 instead of uint32_t in hypervisor_cpuid_base(). Yes, I realize uint32_t is used in Xen code et al, but this is a core x86 architecture header and we should standardize on the type that is being used overwhelmingly in related x86 architecture code. The two types are the same so there should be no build warnings. Signed-off-by: Ingo Molnar Cc: Juergen Gross Cc: Stefano Stabellini Cc: Ahmed S. Darwish Cc: Andrew Cooper Cc: "H. Peter Anvin" Cc: John Ogness Cc: x86-cpuid@lists.linux.dev Link: https://lore.kernel.org/r/20250317164745.4754-3-darwi@linutronix.de --- arch/x86/include/asm/cpuid/api.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 356db1894588..9c180c9cc58e 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -187,9 +187,9 @@ static __always_inline bool cpuid_function_is_indexed(u= 32 function) #define for_each_possible_hypervisor_cpuid_base(function) \ for (function =3D 0x40000000; function < 0x40010000; function +=3D 0x100) =20 -static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t lea= ves) +static inline u32 hypervisor_cpuid_base(const char *sig, u32 leaves) { - uint32_t base, eax, signature[3]; + u32 base, eax, signature[3]; =20 for_each_possible_hypervisor_cpuid_base(base) { cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); --=20 2.45.2