From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E7C3183098 for ; Mon, 17 Mar 2025 17:08:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231291; cv=none; b=LDJ/O6Awtm49M0B31+W5uSlR8mmYpXvDI7r31BjYbowMvpFxqWxVspMX/xCRT75bqSgrnE2lazH62KmI8ml2MFe9u4AbqtCgZ8q2SUlDD2JbytLiZGdDD8ssJHsp40N6jv0ncM3GGtIgnS8YRo/16I81/6E6C3BPrCY0qczjtO0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231291; c=relaxed/simple; bh=gMTbJG/v304/RzgyXF89VuN8yMkVW4//gJ2IFBZulAM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=c1N2GGFMU1VIVUoxqlBgUv7MSh+cHVdFL+pWFwfA0sIkwaCpql11V1UAnpfKdxBnWnzIAOLRT8Z8Ycebz9IywR1aIKNJ+X6uCp3BZ06RCrsdtRvHn3Fvu5OXSykq0Z9eq4NMqhl697zcJG6URQMoQ+jx9RHIlB5nG3vGu2T0RU0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=vlSOjrou; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="vlSOjrou" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-43cf257158fso15849675e9.2 for ; Mon, 17 Mar 2025 10:08:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231288; x=1742836088; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CVImGrzi7Si4eY1ElT4GTBjapJa7KEDVy79wJkwRK9M=; b=vlSOjrouJL51ciijdwZGFojk6POOm3owvskqTivEWyPbJGLQBUPyx8mt5+6UxUnvxE 1MtYZMTXp5F8WTbpi+hnS/rZnA0LpaovyoMK4+hZNmppauxAdcYX6RaZc6D1ca7n2rqc xelubx6mBl/as7//VNlbWan9QKd9Z/rB8jumEfoKSOtVmT6JRpXIDeyLeo7/E4ygYNm0 zG2Lkd/mVinBXdWq5NPt5VZwDmpVZyv9iQPVRmvBmqEcFvk5Hfq+R5A3gcj8zRkU7TOl RAfehYGaXIXgGQ4I/0e1Kjgv+H1AoPwmhrA/rElKHzxBkT9CqltR1c4f9uJUX1DnXrCT M17w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231288; x=1742836088; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CVImGrzi7Si4eY1ElT4GTBjapJa7KEDVy79wJkwRK9M=; b=JC2VuS6PXQmjfMkM48B2N8yc+mkvv03iKHf4iuM3oP9MfPu7XlWeeP3R+mppcprHAI B65FmtP2sK7KCozwy64mQtgNCayACZnie5enhGmn8sYSH2nhaOUxa0AiS9PLzoRc/EAO DFd8CylqP/AS/c9NQ/86kgf8WvzlLOzlmXW8zzLe1NyBKaqRKRtvTLsBDW8rn8mnxXtb D4aFti2T5YB+zrZUp9j/Xq3i44GBo0KCFFTm8GllOkvC/jvi70kLL6HAb65DwiPXtqTA yLMHHTPVYIEU3qDGuxMUrE/nRsjrPQ99ctam59x1dT9eMQFmUWqS+kOJ7/MYXp80UAl/ 2rgA== X-Forwarded-Encrypted: i=1; AJvYcCV/8vmeHmUeKzpygSzEzhJ0E4Uvr7RNCAzcpPFg3Iig91ZqI/jhdZJXz1POed05qdTJspi86RFGbt7rriI=@vger.kernel.org X-Gm-Message-State: AOJu0Yye0Au/QYeJ6E62T6xR0E83z+cqnq1857E0PUOskC05WzaWnaOS pE0ELj/ObwC2AFqCPzu5k7U9djporvNidHRVK4S9OuinLK943tkZx2eLzAJXJFQ= X-Gm-Gg: ASbGncvzpys5NOy4/2Ee/Lkkx7gp4f/ch8EAChbkPL4fiYgDctTzgvRWCg6Jis4zcxk hSK1Pbddpww8PTm4gaboR2P2P3Zoqa4zj3osmvAcA/QL1UZdHM1R6Z5FilHd+ThII2xzbMsxk4m r2aBVvQR7jGWxoU70XxvWXmbfnOWjxm6UD+lqrZJ+Ik9CAaYgVbpaK3IxxnJBgiPvQ0JIgChg1j NUM2JKsoQr4DUnWw/s4Wusk8ob2fizw9SiK3ss5+m8AyiqgUVsfnJ93eSWw0xv7wjwdyRXfa+IL MHY7sOe6+S2vQSAfABqEDpDrvfr1ZkthF//7BbwuDcbHYw== X-Google-Smtp-Source: AGHT+IHKMm/vFlG6UDlvbMz7uYFJ/kE1+rhH+pJF0OJXqGvzOjYrzfvpGlP18pd4myenVCv8U+eYbw== X-Received: by 2002:a05:600c:4ed2:b0:43d:cc9:b0a3 with SMTP id 5b1f17b1804b1-43d1ed000fdmr113482925e9.22.1742231287574; Mon, 17 Mar 2025 10:08:07 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:06 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones , Deepak Gupta Subject: [PATCH v4 01/18] riscv: add Firmware Feature (FWFT) SBI extensions definitions Date: Mon, 17 Mar 2025 18:06:07 +0100 Message-ID: <20250317170625.1142870-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The Firmware Features extension (FWFT) was added as part of the SBI 3.0 specification. Add SBI definitions to use this extension. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Samuel Holland Tested-by: Samuel Holland Reviewed-by: Deepak Gupta Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 3d250824178b..bb077d0c912f 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -35,6 +35,7 @@ enum sbi_ext_id { SBI_EXT_DBCN =3D 0x4442434E, SBI_EXT_STA =3D 0x535441, SBI_EXT_NACL =3D 0x4E41434C, + SBI_EXT_FWFT =3D 0x46574654, =20 /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START =3D 0x08000000, @@ -402,6 +403,33 @@ enum sbi_ext_nacl_feature { #define SBI_NACL_SHMEM_SRET_X(__i) ((__riscv_xlen / 8) * (__i)) #define SBI_NACL_SHMEM_SRET_X_LAST 31 =20 +/* SBI function IDs for FW feature extension */ +#define SBI_EXT_FWFT_SET 0x0 +#define SBI_EXT_FWFT_GET 0x1 + +enum sbi_fwft_feature_t { + SBI_FWFT_MISALIGNED_EXC_DELEG =3D 0x0, + SBI_FWFT_LANDING_PAD =3D 0x1, + SBI_FWFT_SHADOW_STACK =3D 0x2, + SBI_FWFT_DOUBLE_TRAP =3D 0x3, + SBI_FWFT_PTE_AD_HW_UPDATING =3D 0x4, + SBI_FWFT_POINTER_MASKING_PMLEN =3D 0x5, + SBI_FWFT_LOCAL_RESERVED_START =3D 0x6, + SBI_FWFT_LOCAL_RESERVED_END =3D 0x3fffffff, + SBI_FWFT_LOCAL_PLATFORM_START =3D 0x40000000, + SBI_FWFT_LOCAL_PLATFORM_END =3D 0x7fffffff, + + SBI_FWFT_GLOBAL_RESERVED_START =3D 0x80000000, + SBI_FWFT_GLOBAL_RESERVED_END =3D 0xbfffffff, + SBI_FWFT_GLOBAL_PLATFORM_START =3D 0xc0000000, + SBI_FWFT_GLOBAL_PLATFORM_END =3D 0xffffffff, +}; + +#define SBI_FWFT_PLATFORM_FEATURE_BIT BIT(30) +#define SBI_FWFT_GLOBAL_FEATURE_BIT BIT(31) + +#define SBI_FWFT_SET_FLAG_LOCK BIT(0) + /* SBI spec version fields */ #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 @@ -419,6 +447,11 @@ enum sbi_ext_nacl_feature { #define SBI_ERR_ALREADY_STARTED -7 #define SBI_ERR_ALREADY_STOPPED -8 #define SBI_ERR_NO_SHMEM -9 +#define SBI_ERR_INVALID_STATE -10 +#define SBI_ERR_BAD_RANGE -11 +#define SBI_ERR_TIMEOUT -12 +#define SBI_ERR_IO -13 +#define SBI_ERR_DENIED_LOCKED -14 =20 extern unsigned long sbi_spec_version; struct sbiret { --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 863DDA55 for ; Mon, 17 Mar 2025 17:08:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231292; cv=none; b=RQa625ZD+xt2zJaZAFWZTenfgb5sQKXLE6YZj9H4xL1Ndy2jA92QTMAcCOWErKkKZxgadqLN/Pp74RNn1Y83JAWvDwNsYBaB8+IQeMdZO5P+m90X+q2VTY37KTX2aRdLqzatJOBOWErQ6Hjdnk+k7l11d29R9cowqK1AnIqCM74= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231292; c=relaxed/simple; bh=EqhrCUXSdf6zw+zQLcTnzOZbj5bYjW5BfE2OxtlTOLE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=azBy+BjQT5GOSr2gN/HNdKJRowHZyUU0DldYoFju2W6tewmGvh4yyt+depNsWyAybmGmSbrEq6rnwAquHNUBblw9oDheIMdvyw2jBMfqarSBSgth349W+mCpL1RopAEZhjJBullh7u8tNEz1YarSBl7fSWveFiVzqc0jzCG1fuw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=G9r4nN38; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="G9r4nN38" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-43bb6b0b898so24286305e9.1 for ; Mon, 17 Mar 2025 10:08:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231289; x=1742836089; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xMypehTPr85TSV6ycxYis0bFMGhRtQvpG8E21HWF2pk=; b=G9r4nN38XyH2HTtuBkVy9W+NwDz8Moo4aI4gGr+EwLsKq9NWxXkoYdQ9ubj4p5jFR9 xe1kaDy58L2wL0ItOboKlW9kEIKc63BTQBcyKin+WJl/61p8w9QXJqJaREw4yv7XGf64 xHqKGDaai+CyTVAOqD2Yh3URz1TITAzSfRn3eI2zrw4UyIVafIBi9hZOSgyfoT0Kk9JC xd9tvfVbZUu+8bM0foI7EsfzUIcddT1VcjI8HYvuxKbNWo0k6GhuK+IXNegiOImnCaBH qtL1yFi+1QxvIqRqJmc5h9Lr3749QGvWMym2uKi6Ne5EVrtEv5/oU3mVVYSlHlVUwe36 9x9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231289; x=1742836089; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xMypehTPr85TSV6ycxYis0bFMGhRtQvpG8E21HWF2pk=; b=jtuzfBVaBtNQO5FX5b7FKCLkCA5kp5Vju2HE33+Ztl4POVRm4msNOFEaGjM3Uirgv6 yDxO/B57CCKI+/FkKoftlLau3BollRUbmjDl7PordEUxBRD4FNn5QubJnZy/SpZMVZYQ SLeCNshPIcnZOn0sW4w3UsO9jSH8FXGuv7KkK5p2EPZHuxlOSPG/EIfyuOxB2dtidUGf pjYLf8xRoav1YOGV4cc6NyFXIX03idZvvAjh99iqDQBfElweSAQGP/fjBlxjhwx8075e 8ZlYJvJQTbS+mz3AXl79CQp3YXOR4hQisctJveSbQENrjaiJjYKJLAxUsIHVV1YttiXi xGRA== X-Forwarded-Encrypted: i=1; AJvYcCU8kel/EOmpZ/Y6XSiW7dAzBn9vwqw1o3dOMcCVUJO2JM6O0QWqpHHh+bdZUPDJuiJN+bMoI9oOEpZECvA=@vger.kernel.org X-Gm-Message-State: AOJu0YzW0DTfhzFOYV3Ct3qtfTpzcQKSNeUXEaApuqBzXF5WHzdMiiUJ CWk3WEx6EiZ5AkQxHUG3NuMy9IkWbRcj9qt+FL9qK6h5ZZZq3mtZoZeb2F15aNol6M3kiTAVDeH GTZo= X-Gm-Gg: ASbGncsORD23fm8bKrHaq/lmzp7JqUh4cJVhff7dABcYpVTxsU1CFRHwNQw9warMSIH +/NJsymeVh8o4104vxDgSo1PG5OKLHfDCeS60L1tibHS+CY4f8He8TN2cBdNLKjRTZ8QaLt0ADp CG15wUmLNrY4qm2/bTRsMmwjZN3FrPXPhT/SUVlUxhSbMkrLuq29XN/uY35UgR4lk83T/uUGM14 zYs9gbDExDZySjwNsBLd1dWuKcTX46Txm3J0Rgt/icoqt6XEg7CdYVjKyv4e0K4lLpA3OIg2GW3 dLWVclkCHycLjlvnOt2FsPjWwwWdQyw9UqVEua4Rcr723g== X-Google-Smtp-Source: AGHT+IHUEfWy8vRElctY1RJYRY/dHWRIdTIpUq+PBDo9gX+Yv3PK1rGyecjDgc1lfv0PGC4CYGx5Ng== X-Received: by 2002:a05:600c:1392:b0:43c:f4b3:b0ad with SMTP id 5b1f17b1804b1-43d389d441dmr5431565e9.19.1742231288764; Mon, 17 Mar 2025 10:08:08 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:08 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 02/18] riscv: sbi: add new SBI error mappings Date: Mon, 17 Mar 2025 18:06:08 +0100 Message-ID: <20250317170625.1142870-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable A few new errors have been added with SBI V3.0, maps them as close as possible to errno values. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index bb077d0c912f..d11d22717b49 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -536,11 +536,20 @@ static inline int sbi_err_map_linux_errno(int err) case SBI_SUCCESS: return 0; case SBI_ERR_DENIED: + case SBI_ERR_DENIED_LOCKED: return -EPERM; case SBI_ERR_INVALID_PARAM: + case SBI_ERR_INVALID_STATE: + case SBI_ERR_BAD_RANGE: return -EINVAL; case SBI_ERR_INVALID_ADDRESS: return -EFAULT; + case SBI_ERR_NO_SHMEM: + return -ENOMEM; + case SBI_ERR_TIMEOUT: + return -ETIME; + case SBI_ERR_IO: + return -EIO; case SBI_ERR_NOT_SUPPORTED: case SBI_ERR_FAILURE: default: --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F39271ACEAD for ; Mon, 17 Mar 2025 17:08:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231294; cv=none; b=m/kNtusfYq4ZWIR5O3M6/rTL/UbPzUJIp3fYIDzFzatu9lnjwkIbSCvRyu7jwIL2Q3VBSaq9QCL76GXP2se4NfVnVHRlp+8V8uYnddamxGMuH4rGhI1FfJbILjT15uJuSpSRdAhKYGjsaCUbsenibG+tRXMW4B80WAC0Ik0qozI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231294; c=relaxed/simple; bh=dwkX4ghtuFTs9nXX7YkIDxi1Nt/XeE3g8BNL/2zgIi4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tJyYDOvyUtKh7hon+aKl003OpFwRpiL9Odx773/p7tUBIU0r2tFXvin6/FdBQv8mmMbscN3rcTbaXtuxUm8hn7GJxoySNXGClL0ascj865/Ebmpn58zC+Hopg9i8RotW38j3n+zrZyHInWEJwxzynq+mhY59i4ZOhlGWQnLs2xA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=fEi1VGZ3; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="fEi1VGZ3" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-43cfb6e9031so20958975e9.0 for ; Mon, 17 Mar 2025 10:08:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231290; x=1742836090; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WzyfmLdoy3J2d7N3ElT+BcY4glWrhhZZ3MI8rtjNdBk=; b=fEi1VGZ3P0tiEv4sJLBlTbDthxK+GiJPfJ16u1P1Xo7dzAV+vvmpKuQUZe+oKPFwRF E5YdiuHL26ArbQMkF0pDHTN4XCq3TR6bA9R8L8viIUoZUgp/kuBMOaqTyQ7PUjcM5t7D zkCyUkCBcdd2Vg0svT5IscrK23XEgW5fkRGvMpJNdJmSeDCEmS/e2AkIWcRDZv0kVl4p St/BL6BFMGxzlkdiU/9xlVSTWH4p23a0tRbHR41dX59df3uFFzffDIqwd0kvvDnXTHjg FzRByGhdWdwZTg1tOTH3yK4JgT8G/X3cv5y3xBjaNAk1OX6yar/p9/RnXKBl7JJXOnzL ELvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231290; x=1742836090; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WzyfmLdoy3J2d7N3ElT+BcY4glWrhhZZ3MI8rtjNdBk=; b=bYzQbhl/j/SZexzfVSotROrjZLAG9qJEYRqjlTt+XM+88/Ob7wrul+BmI0dzMEko61 FdDKCTBj3lKMXBXHYla804YLiyZr+NNoV/dAdz2oNz+K76HE8Hhl52dwGbHqJM8fmBTT 6L99uiXtasQC0P/pa+W5bMYxr2bELPCSW8SzZKi1gsax4WPN+wQKE7drIj1Xzg5Ue+uW Tmak8GUa76L+FGu86gs1tY/Aea/ZC2eRFTq8OwE+S7NMRLptfI5vu8Ur5I1TuNLsiXdY XJc7XV6v0fM2hCYyO+3kNLx0kFsoAkJRtZSyzLdzUEDJSupnTkh1RACWhfyQx773nN7D lwFg== X-Forwarded-Encrypted: i=1; AJvYcCX6TbRGgEzhmtTtcf1p9ZKDYaMt9UVZpCR+zkqSEVUArbGTa05vRiq7FRVACPC/mjRcLdwGeDjCs9dm2Ao=@vger.kernel.org X-Gm-Message-State: AOJu0YzGs29WWmRocAafYklnI38zIW/GQigWSXL7un761X9nYC7nLu75 vbcujzXt0Ci3KLFUJ0OefYVMln3/xzBkR4wExktlW+WYxqnzxxF1/gdKAIfSZpo= X-Gm-Gg: ASbGncvzcDHrHp1/VJoWRSOwe52nkkqYrGSEknQ33v3NvuCr4aZBYXNV/OxPAk/v+je rjt0/kzcMc9vp1ds7UwMqS0JOia2J/Er+uquQHLZoNkaU2OJTEvesKHzBKqMnUkc8/Bfs74ejy+ uk4HS0f5tsjyZBVsLY52qUfH8j5+SU3oYFQ7CEVMJQ1veBWVCUsM2Bh/sHjKObXohhWrdeLeK19 tt1t3d+hrxVQiJOSS/iZp4nwyqtbavxE4ObpiDjGnj+rFN6sofN5gPULYLHFq80nAHbbHLr3DPb l1yAI8wmFziLz4pqxnxakwGH+FybKZew88alPjFKwF5zqQ== X-Google-Smtp-Source: AGHT+IEXtMD53rpT5+I6qBlek794Ca+55Nd9V0KPjs7YD1xcg1pmEqFLjYcNNVWjDAHYDrYaGY3dSQ== X-Received: by 2002:a05:600c:3c89:b0:43c:f87c:24ce with SMTP id 5b1f17b1804b1-43d1ecd7adfmr118223885e9.21.1742231290211; Mon, 17 Mar 2025 10:08:10 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:09 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 03/18] riscv: sbi: add FWFT extension interface Date: Mon, 17 Mar 2025 18:06:09 +0100 Message-ID: <20250317170625.1142870-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This SBI extensions enables supervisor mode to control feature that are under M-mode control (For instance, Svadu menvcfg ADUE bit, Ssdbltrp DTE, etc). Add an interface to set local features for a specific cpu mask as well as for the online cpu mask. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 20 +++++++++++ arch/riscv/kernel/sbi.c | 69 ++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index d11d22717b49..1cecfa82c2e5 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -503,6 +503,26 @@ int sbi_remote_hfence_vvma_asid(const struct cpumask *= cpu_mask, unsigned long asid); long sbi_probe_extension(int ext); =20 +int sbi_fwft_local_set_cpumask(const cpumask_t *mask, u32 feature, + unsigned long value, unsigned long flags); +/** + * sbi_fwft_local_set() - Set a feature on all online cpus + * @feature: The feature to be set + * @value: The feature value to be set + * @flags: FWFT feature set flags + * + * Return: 0 on success, appropriate linux error code otherwise. + */ + static inline int sbi_fwft_local_set(u32 feature, unsigned long value, + unsigned long flags) + { + return sbi_fwft_local_set_cpumask(cpu_online_mask, feature, value, + flags); + } + +int sbi_fwft_get(u32 feature, unsigned long *value); +int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags); + /* Check if current SBI specification version is 0.1 or not */ static inline int sbi_spec_is_0_1(void) { diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 1989b8cade1b..d41a5642be24 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -299,6 +299,75 @@ static int __sbi_rfence_v02(int fid, const struct cpum= ask *cpu_mask, return 0; } =20 +/** + * sbi_fwft_get() - Get a feature for the local hart + * @feature: The feature ID to be set + * @value: Will contain the feature value on success + * + * Return: 0 on success, appropriate linux error code otherwise. + */ +int sbi_fwft_get(u32 feature, unsigned long *value) +{ + return -EOPNOTSUPP; +} + +/** + * sbi_fwft_set() - Set a feature on the local hart + * @feature: The feature ID to be set + * @value: The feature value to be set + * @flags: FWFT feature set flags + * + * Return: 0 on success, appropriate linux error code otherwise. + */ +int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags) +{ + return -EOPNOTSUPP; +} + +struct fwft_set_req { + u32 feature; + unsigned long value; + unsigned long flags; + atomic_t error; +}; + +static void cpu_sbi_fwft_set(void *arg) +{ + struct fwft_set_req *req =3D arg; + int ret; + + ret =3D sbi_fwft_set(req->feature, req->value, req->flags); + if (ret) + atomic_set(&req->error, ret); +} + +/** + * sbi_fwft_local_set() - Set a feature for the specified cpumask + * @mask: CPU mask of cpus that need the feature to be set + * @feature: The feature ID to be set + * @value: The feature value to be set + * @flags: FWFT feature set flags + * + * Return: 0 on success, appropriate linux error code otherwise. + */ +int sbi_fwft_local_set_cpumask(const cpumask_t *mask, u32 feature, + unsigned long value, unsigned long flags) +{ + struct fwft_set_req req =3D { + .feature =3D feature, + .value =3D value, + .flags =3D flags, + .error =3D ATOMIC_INIT(0), + }; + + if (feature & SBI_FWFT_GLOBAL_FEATURE_BIT) + return -EINVAL; + + on_each_cpu_mask(mask, cpu_sbi_fwft_set, &req, 1); + + return atomic_read(&req.error); +} + /** * sbi_set_timer() - Program the timer for next timer event. * @stime_value: The value after which next timer event should fire. --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E780B1B0434 for ; Mon, 17 Mar 2025 17:08:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231295; cv=none; b=OnPpGsfPakqkFjhbidwkJyEDhOw69CG+5YnTHQOume4m1KnMzpEnucgwWqoD4sHRChLnUV2AKH2nBRXNCGTCO6LTT5oa2ZgALtoza2eO2EcC5qsr38prcYhgEHG8b7koWKJOjWjx8e4cs7D5igeMsQg6XmWLoJv+UdJ4Sw4F8Oc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231295; c=relaxed/simple; bh=U7CU6+Kbf4DBAxOi6Y/TkfLPplKtNBTWKEM0FEOVzX8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aIoT9Kc+UmbPZjWgFxP+GZf+xk+ZFTx3g4jPRDlhducmeZXIfMPrON2XoUsLR6ZlVF1EmtfTdNeT5kOp5wkhAmsBCLoycUUHAI623sYVdTHzP1LYQfbQOClLhBt8s9agZdwkHTL6m0dywdKA2lAcdaxKJ7P69/lanGu5w+F/gpg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=hy+pSBZe; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="hy+pSBZe" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-43cfa7e7f54so13877975e9.1 for ; Mon, 17 Mar 2025 10:08:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231291; x=1742836091; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MnEzy7kWLGCaTTq9cfZB5uZycg5cp6OZgHd6PiXZO0Y=; b=hy+pSBZeNonnztefokC+XfKGDit/V16KT+Hq5dECtpRpGoHKBF4MkUPgRjcZ0VA4zN iaZi/WuHWE0+QMYllUt7u2XV5WvWPTWUFgQllCSSx3xOx862TAhjQRAI1xDwL24c1xLZ 5HsfS7a/sPvcgcXaCBdHcdlQGOYqCmmefGYCoWiTjYPyWqFF2SX2IUFaPN9ZjoJtSobh 7fLVkoTbPx6ZWWpgSzdypiWAjUNv6gwiT+cUd35svnVUd5G+gMzOsI9meinqhKywK6YN JTel8yxkoDqnfjhQ4zNZNPXSTiRVcoRMdqTfJlp6NCHw2Di3NSakQToCux27OUjkdh5X wxbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231291; x=1742836091; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MnEzy7kWLGCaTTq9cfZB5uZycg5cp6OZgHd6PiXZO0Y=; b=vXqBckC/2/Ok9ioh7RkMO5Exmwpv6cQ6FpRVeKkR+jTpOma35vuZBEyb4jSLqV6i4y 6c0wzhKP6gOR7mSY5+aejflLtzdokWZWYOfqX/3GQdYRl/Xj89OR+J5abtqd/byMEKtq eP1tL5rxXQvmdUf7qhiTRjvJMljb5+14++8LVt31KnTe7N5GcUjaOZzoNfh7mCAeINXC GY/Pcaacykb1OgIXx+vpbBM1D99mEAS4+PXYKARDgdKe4w9/IinHCJQEwRtaG2FoQcgG t80Han7DRL4cIkx068eSFUp9ahV9yJFc9FXy/ZZAE99nkZ9j4ssAV+qG6W9niIcxt3ka UXVg== X-Forwarded-Encrypted: i=1; AJvYcCVuLTGfR2HwMp0ZappnFQMnY7nd6sVaQBFFmsqPl0CERvUdTIuSR8hbomjR2BiwnwWpjqiigXxs3vlC5hk=@vger.kernel.org X-Gm-Message-State: AOJu0YyzMx4fmF/U7tPlLbXRr+fUGXrxPJjd84yU5iREN2CMIcy3zhmd oLLLRnhRKzigYMuUYhg8CoodPsWxhN4mQVwO6UNx/0cZOLydWkALIWrNYoXiyjI= X-Gm-Gg: ASbGncul7hpqkyYpM8Q+/0+H1PfWQNUDtFBRw99oQn3O2w0PhUvLoX1CrvhUQjuu6Z2 U0bhRafmAFxprf7rzo1zhP+ltRzeZuzJgVuZmfK82ksby0ljPAWk/CkpIre78YDfXEfxAjanry/ 5UlSHDBMOonTFaKUBOyTBJPKWiy9HACV3EOdCMqP+IBYI6kLo6Hw3medGBcKpSwLp6qId46nquX 6B1dhc6GUKLy2XbmWkhbKUcjkp5KHwrCRv4rfTruAdmpiF4IcTHgaXcwvuYqdWdQ1ScB5PYC56f aTw+UcokmI5O7++CMqv9/uCBKNvrmbfBVJ/oHmFUSBYqqw== X-Google-Smtp-Source: AGHT+IEhk9ILCkt1d4miwCrhVE7Pp8SXCLMrmpN073cNBxqpViWwe1YnhF1uSTy7oETuXKPGMPnacQ== X-Received: by 2002:a05:600c:a53:b0:43d:b33:679c with SMTP id 5b1f17b1804b1-43d390976e7mr2112565e9.14.1742231291216; Mon, 17 Mar 2025 10:08:11 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:10 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 04/18] riscv: sbi: add SBI FWFT extension calls Date: Mon, 17 Mar 2025 18:06:10 +0100 Message-ID: <20250317170625.1142870-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add FWFT extension calls. This will be ratified in SBI V3.0 hence, it is provided as a separate commit that can be left out if needed. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/kernel/sbi.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index d41a5642be24..54d9ceb7b723 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -299,6 +299,8 @@ static int __sbi_rfence_v02(int fid, const struct cpuma= sk *cpu_mask, return 0; } =20 +static bool sbi_fwft_supported; + /** * sbi_fwft_get() - Get a feature for the local hart * @feature: The feature ID to be set @@ -308,7 +310,15 @@ static int __sbi_rfence_v02(int fid, const struct cpum= ask *cpu_mask, */ int sbi_fwft_get(u32 feature, unsigned long *value) { - return -EOPNOTSUPP; + struct sbiret ret; + + if (!sbi_fwft_supported) + return -EOPNOTSUPP; + + ret =3D sbi_ecall(SBI_EXT_FWFT, SBI_EXT_FWFT_GET, + feature, 0, 0, 0, 0, 0); + + return sbi_err_map_linux_errno(ret.error); } =20 /** @@ -321,7 +331,15 @@ int sbi_fwft_get(u32 feature, unsigned long *value) */ int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags) { - return -EOPNOTSUPP; + struct sbiret ret; + + if (!sbi_fwft_supported) + return -EOPNOTSUPP; + + ret =3D sbi_ecall(SBI_EXT_FWFT, SBI_EXT_FWFT_SET, + feature, value, flags, 0, 0, 0); + + return sbi_err_map_linux_errno(ret.error); } =20 struct fwft_set_req { @@ -360,6 +378,9 @@ int sbi_fwft_local_set_cpumask(const cpumask_t *mask, u= 32 feature, .error =3D ATOMIC_INIT(0), }; =20 + if (!sbi_fwft_supported) + return -EOPNOTSUPP; + if (feature & SBI_FWFT_GLOBAL_FEATURE_BIT) return -EINVAL; =20 @@ -691,6 +712,11 @@ void __init sbi_init(void) pr_info("SBI DBCN extension detected\n"); sbi_debug_console_available =3D true; } + if ((sbi_spec_version >=3D sbi_mk_version(3, 0)) && + (sbi_probe_extension(SBI_EXT_FWFT) > 0)) { + pr_info("SBI FWFT extension detected\n"); + sbi_fwft_supported =3D true; + } } else { __sbi_set_timer =3D __sbi_set_timer_v01; __sbi_send_ipi =3D __sbi_send_ipi_v01; --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8809C1B983F for ; Mon, 17 Mar 2025 17:08:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231297; cv=none; b=Q2+q6DqWiNUhSzPwBL9ASGHkSLIiWPCJCVN0scE9exre3L0XUiHiRqDXt/ToyRTqLDgoSzdh/FIbGj8JWHGaRyTHsV24OTbjcr7yPsTOBuDJtv/BBrexxROB659T86BZDMxjhiIHVzcHPpFTTzjIHBMfA3cQBx4O19ZEoQh3RBs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231297; c=relaxed/simple; bh=OtY2EOfT7IN04wGt9UYX2OMYcXbBRcTX/gnN/1KIezs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=paY+4qJbxBKBGT/igH80O0ADg/DLHhSWdAY+t5smSf9nPlYM6HfYdKCmhx/7WVnx5KpmXve+0q9UxqsFmFaeqGXfqcfCgUYOU/OEpz9967735oEvqb3oBhOkeQWwhXXe+6+6se19qw4opE0hxR1YaoDnK9dhtP11PB6+nT6VUcE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=tvOaMH18; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="tvOaMH18" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-43d0618746bso18244285e9.2 for ; Mon, 17 Mar 2025 10:08:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231293; x=1742836093; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5k1emOUih8WEclNZ1DDbkx/NdClZ1In2F+3XrsHVDoI=; b=tvOaMH18T9CtLFZq5KraGw0x+pTpzzEMKdmbxJqRWSqYJXMXdxs/OS48Gu3giV/9y1 lu4om5ULPsFngpEHwv6tlRnUVQ1C5sFKkMDsK3P68kgNziaUpkhpI9muayQtHLEnZp90 werpjkD909udm6NWc3AaJUFruVSa/UMrrTn1G13o3zdRstM7kLw/mYS2qcPRED3j/51A tpBCm3kUlRFAgZjBZUbvBUiZeg2zWFhJYuXZFWm96MQpx1P0tNViDmMzIACf/wipWMr7 oM9F5NCGe48K+rKy3MZlII2Q/jU2nnhn1WjrVtKFJG+b+jeoDDtn4q/iliCn59hzPkDQ BQAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231293; x=1742836093; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5k1emOUih8WEclNZ1DDbkx/NdClZ1In2F+3XrsHVDoI=; b=FFUmL5WBgbkrAvQq+el/1990rhCGjsABgm2byNWQZiJjgT0o8yDTqTOKlHGhV0SqU1 +14/k+gmZ6iV06hS6VWIPXRVPCV74kdGk6CHizdqz2bbkPi7PVhoTfwF3qrdCtRjq1KJ qyMyEGq61xGtiF9Sdohqec2pZak5Oc+zV3jrFeaM7sKHkGozViCd/38jcMfUWd7Bcson vSTkv9nJkfgcvP/5IB3l97e1hsG6JeF+AEV6csrL5cohNy4eUhYahQtGP+J7qn5dtegR selpEVSXrkKGvaGWUVZv8OyzkEfIrpRRpHtPMjq7XhEH6/eQl21E1l5RP27abpwAXZKj IqZw== X-Forwarded-Encrypted: i=1; AJvYcCUD/i45uU6qFuc6ATz5xdlgvAzlQR2P622KKBQH88ymZYDzXGfV6/J9BQj9syTFm4pMsv0sc6754gEGh8s=@vger.kernel.org X-Gm-Message-State: AOJu0YyqzB8XQ5i2IWIq/IFy/Th7ndvUc7SLFhlCYaxgH16bxSqpRVfC FrLo/uSnJWWfMUrHwDiO1Z/ZMj5feJgWNY12fbxFyXylJuCUa09amOfnw9KjSzI= X-Gm-Gg: ASbGnctwtHSD/rDJ4kA78URnjrPbbdXLi+nGKxw5bGcM1lBdFKA9JXOOWFEzC7kNUJJ giQoyy0/hbbQOKfMKb6mKpuLq5EJZj4S9s1ravS7ZFM0TdeTvSWrhN7rGX69FGQFGHpaWuKZASP jAuff7iYhMrGC+mgWeO992XeD2iT2d519fyAVLeWTzZRIkjc7M1Jke0qM0+ko8nPdQdG0b/yUZi GKzRAsi3eZ8973ndSOCVcf8NI9H57Gq+2jTHW1F6caXFKJnsdr+TsEceZ0DLNwL+Wj7YnpwQtGU eDr1YFHW+Wcb2knGvGfZApN62Pngc5I2S6BcZx9L+xZDag== X-Google-Smtp-Source: AGHT+IGirZlNuMI7AkYZLJxITsbB2mx0iqkOoTwEVui95+l6OuB5d7SYtKlA2CI4i4rX//+fE8Z8jQ== X-Received: by 2002:a05:600c:468a:b0:43c:fb36:d296 with SMTP id 5b1f17b1804b1-43d1ed0e03dmr115529165e9.25.1742231292646; Mon, 17 Mar 2025 10:08:12 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:11 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 05/18] riscv: misaligned: request misaligned exception from SBI Date: Mon, 17 Mar 2025 18:06:11 +0100 Message-ID: <20250317170625.1142870-6-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Now that the kernel can handle misaligned accesses in S-mode, request misaligned access exception delegation from SBI. This uses the FWFT SBI extension defined in SBI version 3.0. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/cpufeature.h | 3 +- arch/riscv/kernel/traps_misaligned.c | 77 +++++++++++++++++++++- arch/riscv/kernel/unaligned_access_speed.c | 11 +++- 3 files changed, 86 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 569140d6e639..ad7d26788e6a 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -64,8 +64,9 @@ void __init riscv_user_isa_enable(void); _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _valida= te) =20 bool check_unaligned_access_emulated_all_cpus(void); +void unaligned_access_init(void); +int cpu_online_unaligned_access_init(unsigned int cpu); #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) -void check_unaligned_access_emulated(struct work_struct *work __always_unu= sed); void unaligned_emulation_finish(void); bool unaligned_ctl_available(void); DECLARE_PER_CPU(long, misaligned_access_speed); diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 7cc108aed74e..fa7f100b95bd 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -16,6 +16,7 @@ #include #include #include +#include #include =20 #define INSN_MATCH_LB 0x3 @@ -635,7 +636,7 @@ bool check_vector_unaligned_access_emulated_all_cpus(vo= id) =20 static bool unaligned_ctl __read_mostly; =20 -void check_unaligned_access_emulated(struct work_struct *work __always_unu= sed) +static void check_unaligned_access_emulated(struct work_struct *work __alw= ays_unused) { int cpu =3D smp_processor_id(); long *mas_ptr =3D per_cpu_ptr(&misaligned_access_speed, cpu); @@ -646,6 +647,13 @@ void check_unaligned_access_emulated(struct work_struc= t *work __always_unused) __asm__ __volatile__ ( " "REG_L" %[tmp], 1(%[ptr])\n" : [tmp] "=3Dr" (tmp_val) : [ptr] "r" (&tmp_var) : "memory"); +} + +static int cpu_online_check_unaligned_access_emulated(unsigned int cpu) +{ + long *mas_ptr =3D per_cpu_ptr(&misaligned_access_speed, cpu); + + check_unaligned_access_emulated(NULL); =20 /* * If unaligned_ctl is already set, this means that we detected that all @@ -654,9 +662,10 @@ void check_unaligned_access_emulated(struct work_struc= t *work __always_unused) */ if (unlikely(unaligned_ctl && (*mas_ptr !=3D RISCV_HWPROBE_MISALIGNED_SCA= LAR_EMULATED))) { pr_crit("CPU misaligned accesses non homogeneous (expected all emulated)= \n"); - while (true) - cpu_relax(); + return -EINVAL; } + + return 0; } =20 bool check_unaligned_access_emulated_all_cpus(void) @@ -688,4 +697,66 @@ bool check_unaligned_access_emulated_all_cpus(void) { return false; } +static int cpu_online_check_unaligned_access_emulated(unsigned int cpu) +{ + return 0; +} #endif + +#ifdef CONFIG_RISCV_SBI + +static bool misaligned_traps_delegated; + +static int cpu_online_sbi_unaligned_setup(unsigned int cpu) +{ + if (sbi_fwft_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0) && + misaligned_traps_delegated) { + pr_crit("Misaligned trap delegation non homogeneous (expected delegated)= "); + return -EINVAL; + } + + return 0; +} + +static void unaligned_sbi_request_delegation(void) +{ + int ret; + + ret =3D sbi_fwft_local_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0); + if (ret) + return; + + misaligned_traps_delegated =3D true; + pr_info("SBI misaligned access exception delegation ok\n"); + /* + * Note that we don't have to take any specific action here, if + * the delegation is successful, then + * check_unaligned_access_emulated() will verify that indeed the + * platform traps on misaligned accesses. + */ +} + +void unaligned_access_init(void) +{ + if (sbi_probe_extension(SBI_EXT_FWFT) > 0) + unaligned_sbi_request_delegation(); +} +#else +void unaligned_access_init(void) {} + +static int cpu_online_sbi_unaligned_setup(unsigned int cpu __always_unused) +{ + return 0; +} +#endif + +int cpu_online_unaligned_access_init(unsigned int cpu) +{ + int ret; + + ret =3D cpu_online_sbi_unaligned_setup(cpu); + if (ret) + return ret; + + return cpu_online_check_unaligned_access_emulated(cpu); +} diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel= /unaligned_access_speed.c index 91f189cf1611..2f3aba073297 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -188,13 +188,20 @@ arch_initcall_sync(lock_and_set_unaligned_access_stat= ic_branch); =20 static int riscv_online_cpu(unsigned int cpu) { + int ret; static struct page *buf; =20 /* We are already set since the last check */ if (per_cpu(misaligned_access_speed, cpu) !=3D RISCV_HWPROBE_MISALIGNED_S= CALAR_UNKNOWN) goto exit; =20 - check_unaligned_access_emulated(NULL); + ret =3D cpu_online_unaligned_access_init(cpu); + if (ret) + return ret; + + if (per_cpu(misaligned_access_speed, cpu) =3D=3D RISCV_HWPROBE_MISALIGNED= _SCALAR_EMULATED) + goto exit; + buf =3D alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); if (!buf) { pr_warn("Allocation failure, not measuring misaligned performance\n"); @@ -403,6 +410,8 @@ static int check_unaligned_access_all_cpus(void) { bool all_cpus_emulated, all_cpus_vec_unsupported; =20 + unaligned_access_init(); + all_cpus_emulated =3D check_unaligned_access_emulated_all_cpus(); all_cpus_vec_unsupported =3D check_vector_unaligned_access_emulated_all_c= pus(); =20 --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 775311C8624 for ; Mon, 17 Mar 2025 17:08:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231298; cv=none; b=Ha7NXbhR8K2FvNRDS3YcyKx23b7UgqYI81u5v/v+jPgu5QDiZUMD8TMCqTOnMpq35j4E7w2m8qzsLYATsbY6IVkgHeWR71glBwxeOqRmWhX3vHFNfkTIX/LsiUNLIu2my8s/Fu73LpwcOSFuLaX8HWPgvoIJ7ggkAt98/zTRWS0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231298; c=relaxed/simple; bh=m22pBr3V6eaVlLVIX44rOw00wFDH5N5l1rGKB3m4pxQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=p4dW/xEpLoT9YBpyKp10lNp4OHIAGhwibZv/KKXPi95Gp5/OAE9VRwRxlYVfuB+Gqjxzq8Vj0NMfREwfHBVfIM7lE5+6CJikjoruA0lA/gDzDM/1cT0geFTw9ow55EfYVSBELZKmzxEnceG3wXrV3/PQLNCWNgnEPIxPlbQp6yw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=RSSH4PMR; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="RSSH4PMR" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-43948021a45so25174755e9.1 for ; Mon, 17 Mar 2025 10:08:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231294; x=1742836094; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rjeBRUPbBkNgIlDeDsLglyk/HEJX/vNaDwxAgvCJumI=; b=RSSH4PMRsfeCZiWscD1JYj+yEnxbSVZ/bWe7EvT8f5S4lgd00i0g3osurYR7gu0lKS 1KaI9sbd4XugSVanJWNMV7w1ZTkE3HkmR/Cj1JNB6CsZxXqm1z/y8YJjFF5kmGqCZd4m zI61GGTPhlXelbPiO9LekJhFT/0hmhG/LIf0azpeyKuYcEVF3z13ezHEP2QpkzWBbPpF 76oCXswhS7q0OcxGmFW/Y9tKMbXqKFD+62dPAXNqt35ZODalW92kXYPZbHV4g5ZL6lx3 5MjfXUMoercuOjOCWWf51HYIaVDvMK5b9kDCjhUd2DH0UBt57xd9vFsnXeE7r1fo/VAv ix7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231294; x=1742836094; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rjeBRUPbBkNgIlDeDsLglyk/HEJX/vNaDwxAgvCJumI=; b=i7AjQP/Txmli0ty5+i3iY6eqLomNb08CPgWCIOHShBVWdwb/LnqMrjMjtub/M0VFl1 K5hqtTd26d/0BTmVpN4oqztXpP8D0lm7z8rrveb1dEH/7YwyR9iD1lfQKalDt4TLP/su i3xHD8m9a9eUEq4AZsGfr7nD48FdMf4+3Dzx/tEnzV3Gu1R9n8Dt3imj8f+m9XByJ67I 7xlmh3WvGofFgxKAOotQ77B4HPD/SpmkAvhSiBanmNyzb8BJg1NKPF6fZtBnoAtRaf9Y 49NXFH44s1Zxj4fSMGBpnJ7BGeA4JJO82jA4+ZVCqQi6ILNcyfFmf0pcU0/RG+Nt8oeZ 0aiQ== X-Forwarded-Encrypted: i=1; AJvYcCXi6oZrkt5jmBVM2M261NSTPNYMNNf7ErUKAUgH7qlMZGoO7iNZ86BCwkIJEmiMNaRyeZ9UcCVcJVUMuCM=@vger.kernel.org X-Gm-Message-State: AOJu0YwVuczkppgycD0LryErHv++j/QH2YDhs/YDZCF616sPIx5+4bpS +gMhKAAhSOaOuoUMPIG2Imf3Vot/TCARaxOqPjPg5BPfukTqZ20m+/5zfhYiB8MF64ppp5BO1pq Zd2s= X-Gm-Gg: ASbGncsCiWLNVOXhmdShc5Vv4Mwy7Au0OVyv9B4AwpC+sq+BRBXSl+vWICjqWosfhkR IaS/WCrcmY69EXSi3lLpOVuL2BbTwhfpgKLzYdwpWkTm2Dvdz89DSvRTDILDHeljjPAuIVElUHA Okb7ABP7wzf/K2vqyVzwnNdq1DNjtW0y7ORLH12WQjE2uUF1BzlaYMEivHtGUgFg6fc89ffN5+P LP7NOMiK4HZnQWh6lkkgGcJsh+6UtM7MugGidj37z6DCrzs7vXvgxfRLFxCnlG37apua5RiEkkl Q/iv82PlNUWEWv/uFVpEXxm/gkgoNN4qQ5oNpIylWvxZCxkgLlfe+LZh X-Google-Smtp-Source: AGHT+IEAV1SSYPsskoq8q0qrPU5Tio7ya8gNR4WNeMxWQDKOPXJ0cX+p31upeUPN82mA8abBVPNApw== X-Received: by 2002:a05:600c:4ed3:b0:43c:fe15:41cb with SMTP id 5b1f17b1804b1-43d1ec80917mr153430805e9.15.1742231293673; Mon, 17 Mar 2025 10:08:13 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:13 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 06/18] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing Date: Mon, 17 Mar 2025 18:06:12 +0100 Message-ID: <20250317170625.1142870-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable schedule_on_each_cpu() was used without any good reason while documented as very slow. This call was in the boot path, so better use on_each_cpu() for scalar misaligned checking. Vector misaligned check still needs to use schedule_on_each_cpu() since it requires irqs to be enabled but that's less of a problem since this code is ran in a kthread. Add a comment to explicit that. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/kernel/traps_misaligned.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index fa7f100b95bd..4584f2e1d39d 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -616,6 +616,10 @@ bool check_vector_unaligned_access_emulated_all_cpus(v= oid) return false; } =20 + /* + * While being documented as very slow, schedule_on_each_cpu() is used si= nce + * kernel_vector_begin() expects irqs to be enabled or it will panic() + */ schedule_on_each_cpu(check_vector_unaligned_access_emulated); =20 for_each_online_cpu(cpu) @@ -636,7 +640,7 @@ bool check_vector_unaligned_access_emulated_all_cpus(vo= id) =20 static bool unaligned_ctl __read_mostly; =20 -static void check_unaligned_access_emulated(struct work_struct *work __alw= ays_unused) +static void check_unaligned_access_emulated(void *arg __always_unused) { int cpu =3D smp_processor_id(); long *mas_ptr =3D per_cpu_ptr(&misaligned_access_speed, cpu); @@ -677,7 +681,7 @@ bool check_unaligned_access_emulated_all_cpus(void) * accesses emulated since tasks requesting such control can run on any * CPU. */ - schedule_on_each_cpu(check_unaligned_access_emulated); + on_each_cpu(check_unaligned_access_emulated, NULL, 1); =20 for_each_online_cpu(cpu) if (per_cpu(misaligned_access_speed, cpu) --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 689FA1DD0D6 for ; Mon, 17 Mar 2025 17:08:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231298; cv=none; b=RmUSZg+qauKgwxEu8/jn1eHNGmit4Ize9isvFroSlV76hS7DbKsLHhV12Ryc+wS8ivHa94AAub/8Vp51GWizZrhhSWAD6WhDfknqnY8pBR7Q5YhR7iD3g0A4jovDGxWpYd+eqWiaN+vIodhMq0GbGePosUXt5Mec79yDXNPlnDM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231298; c=relaxed/simple; bh=PGO9LR6+AbkkV+AvdmztnqTXaQaryBDcmq2YW6awKdo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BXCtKuPrDZugZ7VQmVrAaLJIsEK7xzY0mvWkY0eGBg6WXxYBnWpMYCLCUbjzsUHK4yapny7wizb5xQU0bU/s1h0i8OkRwMDjx8ZrtYA8H8mGzcNGQp9I6tlVrXYVOgnwNSyiuTKrbAmjvqiTOiwI4zdW7lcOuheMZ//imdYxuww= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=eiUoWQEJ; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="eiUoWQEJ" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-43948021a45so25174905e9.1 for ; Mon, 17 Mar 2025 10:08:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231295; x=1742836095; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0kTF+ccGFA3pCz5oiuUa/A8mZMPFTX0HIKuC7hxXfUI=; b=eiUoWQEJoM3/ZBL2/o27ia03zD1qjd0wldAO3SsbmVozrOH7FfIpntGc7lJkB00XSE dqtiXVIrYQ+QrKGVGo9bUWCXSABHMjh7M/zewxO3fk/W86V2KcUQKez4esncLD7wm6H9 /W0W5Vd5xr0ToDDIk4b+PdrtycaXehKCtEOy73vPsJuJnE21Z9ndz+1unEjrNNaPc2Am HjoYmIWrCrnC2kp33csVdQEFrtnNH+37bDAuInps/LvQEJMkN8CSbUycXP0Pc+86V2R/ +SOwHYybYeYVpLGkhtNGXWB+UEVlVMMYI+dg5YL9AWt7GaAdeIAQSTdGdzwrgOfjyog3 oz0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231295; x=1742836095; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0kTF+ccGFA3pCz5oiuUa/A8mZMPFTX0HIKuC7hxXfUI=; b=okIQg5wCHNmuzxa36O/kGE3qpykhwIZ/gNzh+x3o8IlpCZDt7nq3wU3a2lRbtJNpjB HeJt230Lw7TC3azzXD6YdrYKTjEjl/0Ywn9JNMoZw4RaV+fhklRAk2LPUPo1NzQT1WqX uGTHq+9uJRFKuJk04RxKs/czSMA2dQE1evEDtlAXeDG1zr+COug9d+/sRBZAe5xxhCwM BwnY0JS/53/bS89/lThJVj6SRjJ44Hz5EqIQdIYqyDUOfnHmtSUOhxjlIHVqZOiOt/FZ SrY9b8adKrQExnbsCdAEWjPBrCE9bjwjRsjXxaCKFLClnnn8h4apWsFACSU9mA/3ekv5 eiSQ== X-Forwarded-Encrypted: i=1; AJvYcCUiCyzW7mNVrBK+4dbZ/IZR06B61ce/YQD2wjcdkDPpu5vvRBQGBF5aBPIL2vlOSVrbL13gpQLPmlk2kQU=@vger.kernel.org X-Gm-Message-State: AOJu0YzQvGdgL8JcTGkHnLUUI4RWLP8xHVPs09tbB3km6wPv6PB4htUs U7NEbdKPjIRvLN0tr/nfHf4ZyM02ajR0ZUtktuknRR3a7qlKdhl+hoBhDvBTZofNiI3olqD9SW7 umGI= X-Gm-Gg: ASbGnct7peMTmvOw1uXWOgeG7URe1cYSY3A5vrsAkV2/3mYpwk9iBXDqSzLl6nrDi8P 3HTkdomAwEFy2e4JN9eEENXDA2jq4rNGS0dPz5bwfAgW6yDaVe6JBN0rbGfM0p4MGyTnowcMe5v CXLATY6mKXqJUvlh+sNrccL5IJg0+ziOz03qDy0GC7Tb1+yopwr9LoefJUQGPJzfvSLpB8XoTL6 ubL5+VPa+Xh6SKgly0xKMFyW4Pix8occIhHOFBHEN2j5nSQh+ZT3WSGNC7X/ajsmErSHuXGuInD zaQdtwOVCq4EoAOMFOkZ5WSurmeszVowVHieVta2M+z99A== X-Google-Smtp-Source: AGHT+IH4sjX9gto0lgEtyEEfUnQHUD379+GVWmuhA4p7t8yk18Gi55URplLVQo2Ek/+dIEHXcxDHKA== X-Received: by 2002:a05:600c:314b:b0:43c:fbbf:7bf1 with SMTP id 5b1f17b1804b1-43d1ecd894fmr147448025e9.30.1742231294732; Mon, 17 Mar 2025 10:08:14 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:14 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 07/18] riscv: misaligned: use correct CONFIG_ ifdef for misaligned_access_speed Date: Mon, 17 Mar 2025 18:06:13 +0100 Message-ID: <20250317170625.1142870-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable misaligned_access_speed is defined under CONFIG_RISCV_SCALAR_MISALIGNED but was used under CONFIG_RISCV_PROBE_UNALIGNED_ACCESS. Fix that by using the correct config option. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/kernel/traps_misaligned.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 4584f2e1d39d..8175b3449b73 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -362,7 +362,7 @@ static int handle_scalar_misaligned_load(struct pt_regs= *regs) =20 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); =20 -#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS +#ifdef CONFIG_RISCV_SCALAR_MISALIGNED *this_cpu_ptr(&misaligned_access_speed) =3D RISCV_HWPROBE_MISALIGNED_SCAL= AR_EMULATED; #endif =20 --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 528351B87E2 for ; Mon, 17 Mar 2025 17:08:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231299; cv=none; b=hKwtOXn/fYr4UViOTVIdBe/ch6O2buF8EOa4X7uWSXVlU40bSc5EJihgn/gT+cbZDzbpteN5lhKBY+miedLNDBiJO9MNWE9BNvMdXdC6SuB1w/2eI35oYUvgWPPDeA3Dg7oJOyYgpjcfr4nY0Ama+PD6PgUSdBvgk9OlinGU1g0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231299; c=relaxed/simple; bh=URKzj8Sa7kgDDDlyaeXh5hfGFe5Tx1TfaYrSR/tVBTo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ehCDfrijztBDtpg0U/FQfk9amFqhx7P8LctTIP3walVJsRve17W8884nu9A/x9AI8/fREZjpTsmWiHx4xDCjvGDzoFJiFiz3BMbB3YOiZIPBLv9CMLjDLTLQ0F5JW/V3bkKheKC8xcA6QQsxI74P5hav2MS7cyhwC5BLp9qWPTE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=2qkOmLwQ; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="2qkOmLwQ" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-43cfb6e9031so20959545e9.0 for ; Mon, 17 Mar 2025 10:08:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231296; x=1742836096; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AU7F+Sv/M47Pn2Qo6/tW45mjDMKI8ET1F5gpFniyHfw=; b=2qkOmLwQrpndyOnNnJY1Io08m3nA8cnKEb2BfXVs6Ma3AxvKvLrekN7O3SDY3HQLD6 uDHunCw7HiilmZmMQVh2Z4+kNK4gzv+Zy9Nw+uEEnyFHuk6l6liVgE3la2MY/pk0xZeM q4Gef5+6Lvi/+kBpwQFYN17Gcw7NlkP+XK3KLeXFdzOE4xmkyuZn2pFTzYGNvLfE7pKz P7uA0gziGZGzLLGAKAnM8WvBQ/smwpXMKJrRhYtYNkSUQxh3JhxgrTKENnu4UpIfVhPB PBIbeDJ96LVwibmr31mrzcFVkbLSWedY73PtbknXg8gWBTwe4OL+SPRiTPFb7SZhOCPU 1gpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231296; x=1742836096; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AU7F+Sv/M47Pn2Qo6/tW45mjDMKI8ET1F5gpFniyHfw=; b=mRQSqm8VbEsPO+R1HX1O8JanZUH86H5a57RoKygw28540Ez14ZuxRc+Qmog6ZkMmB1 /GZZH7Bb/WHLYUYeZAq4BTudE6E+c+vbA663UsJPXUGc/HG8jOb8UNaCVuOl6R/EPIRb PDXLSYWI6c4qqN534l+83e8O4lxU1qLEU+wjKAtymr0mMk4AZWi+TCNCW/1tktQuUFT+ 81/hfziOoMZfR698LdIl5mmSaIGnKV7ojyhTKvGkEPI7lcPGYr43df7e6zIi3PIiHLpg EX0e7BsUHG/mWDneYk4V3Wi6nAWHyTcn9Gqogk8Jch5ZDiKLC0muKRHQWFiaWM91o8D+ CMHw== X-Forwarded-Encrypted: i=1; AJvYcCUpo425nEXshQmRz1qw1U0/7KlwAdRami24xHXnIbKuW0p7m2eRCSVAhcED8v1CEec5fbq8sxZnnRYHp0A=@vger.kernel.org X-Gm-Message-State: AOJu0YzoqLx3V4LtzSEO0oj+2dSWDxhkUBAn6hj/H4jZnUqNO0pDQAVS 4Pj/pQTBpA70vQtBENDoRLiQGi7RhaRWdc93mWFdF1OZXKMq6fGK/gDuN4qsxc0= X-Gm-Gg: ASbGncuitbW2pegfgLTV5p8ZcCWb+iscAv1n5YA3Pca6i1jLZJztcOCDAoqUPgZUEsB 8Ks9jtTt9xR577y99K0KozFaYnU81DTtfwAPG7a4j/wz0Y3ygiNny3as+dv/ac4FUc7GyLORECJ senNhTRDqChBlwsI2Y3Pp3hDD4W2Dy/kAe6PckyAOIohmjVnRUPxiSBaPGf6o8oHTmIADf8z+s6 bwTupgUJuKm0ezLRzwjxW3Egd7iubHCmM3LWtakQJ6nRnIJV8VXi4NKai6xO4KNVz3H3a2cNKtd Ct58wdpla317+MVM/TpQ/OqO/Yc/IoGAQTMNDvXIkhVk3Q== X-Google-Smtp-Source: AGHT+IGpDbXWpDYRUzGh2bTIaNirJTVxXi2O+kKj5FZQdCmID2IJ/McRsJVBPF2vymf5U0IMdZpfhQ== X-Received: by 2002:a05:600c:3b9f:b0:43d:94:cff0 with SMTP id 5b1f17b1804b1-43d1ecd83demr128705695e9.19.1742231295702; Mon, 17 Mar 2025 10:08:15 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:15 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 08/18] riscv: misaligned: move emulated access uniformity check in a function Date: Mon, 17 Mar 2025 18:06:14 +0100 Message-ID: <20250317170625.1142870-9-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Split the code that check for the uniformity of misaligned accesses performance on all cpus from check_unaligned_access_emulated_all_cpus() to its own function which will be used for delegation check. No functional changes intended. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/kernel/traps_misaligned.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 8175b3449b73..3c77fc78fe4f 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -672,10 +672,20 @@ static int cpu_online_check_unaligned_access_emulated= (unsigned int cpu) return 0; } =20 -bool check_unaligned_access_emulated_all_cpus(void) +static bool all_cpus_unaligned_scalar_access_emulated(void) { int cpu; =20 + for_each_online_cpu(cpu) + if (per_cpu(misaligned_access_speed, cpu) !=3D + RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) + return false; + + return true; +} + +bool check_unaligned_access_emulated_all_cpus(void) +{ /* * We can only support PR_UNALIGN controls if all CPUs have misaligned * accesses emulated since tasks requesting such control can run on any @@ -683,10 +693,8 @@ bool check_unaligned_access_emulated_all_cpus(void) */ on_each_cpu(check_unaligned_access_emulated, NULL, 1); =20 - for_each_online_cpu(cpu) - if (per_cpu(misaligned_access_speed, cpu) - !=3D RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) - return false; + if (!all_cpus_unaligned_scalar_access_emulated()) + return false; =20 unaligned_ctl =3D true; return true; --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48B771E1E03 for ; Mon, 17 Mar 2025 17:08:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231300; cv=none; b=Odr5Vl1irB82UDROMp83colKblADIbSqeESVvQ/1QgALLm7+SoZrH3NpNA6rErDNjca3ve3VV3mS4XrRwf/P1Uj6Dav+B+bjhPuZB7Y61Gnys354vKeaTm6A8yLMEWRovBBjRuEY9UVt0asrL7v7HyrM/1MaBY6bWWo++3sCbtE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231300; c=relaxed/simple; bh=s4E957oqIf8er7oaqipLhpUVd977hLf6TtGqZJ/vs/E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=u4rUv4naQXuYQBgctx+0shUEzm4O2VrepZevdk/2NozU+2Hp2Z427ftXt17+m7mnCuSI9lyq8r7g+HvJ6rUNxMQZTsndFxbwwI7WT7J25Be8lgi+69FJjNvLiVRZBXEauTIvaCe6Y97nG9UMsJtpTa5L4sONxQlsH0zeUSdGSVw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=q2CTpS6Q; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="q2CTpS6Q" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-43d0359b1fcso15670605e9.0 for ; Mon, 17 Mar 2025 10:08:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231297; x=1742836097; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=goQPfqUUhZrDcxyWXuqyDL1Ho5AqcAiizxxMLq8C+LA=; b=q2CTpS6QJi8dW1qdnBA0JvHSyuONwujIfHN+9AEMomvVztDcwc6S85/MBlQvtsCxjL oc+yf5/SO0wma9uU3DXO/mCKCD42WDqZtap+n/4vPJ4/fsmPcjVuNj9hrXbjmMKIKJN9 3aW12fbP68JHbxRGpGhQin9fWC4pECamas80Pzs0IWpN2cNgonJm9wzGLGMVyhR+JSHn MRw9TfAMNzHjGEW71MROy66cMPt642/Odp6UYfai+j9SRLUSvog/AW7kMswsJCwk/Kzt /4j02ifaPq/5Lba8XgXCRe8JLytb6cOXQUDyv60EVHFnKH1FuSLta5xPASUlmjVv1w1x JSvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231297; x=1742836097; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=goQPfqUUhZrDcxyWXuqyDL1Ho5AqcAiizxxMLq8C+LA=; b=OcI+gLGnytuo9H9GsNplfa50R4we9cqGivC39kjPa4Vi+DgxMY27DRKWyMZM8r4uJI 5N4jPCkWAR7qZboxwvampjWy5YuquHm1CEJFGljb5akMuljro1QQ2XhXiClIxA15CeGJ 5CzeB4kolfhFEHKoBBGzevPhHCWM4566yQ4a86hVd7rBromKooouP3w2a3YYqsfosq9A jKYQi1RrM77dn3E80DTv+FvdV67NVglnz2FdvbxlhCcCp+2dVEQ9N2GlvvIAeaRIMOjg VTUnPnfG3VO7OGXaM3gYMpHOxg2vk/S3o0I51znKIIBdU6Ma+FL0qzRWlIUvflGQW9An jtnw== X-Forwarded-Encrypted: i=1; AJvYcCXuqkK48OcEFIFi4usN2QKuNTUWX9srGoiMoFSJT6nXUcRsx5OtyrF9E6vZPm03pMTAtuLNkU2O8v2V9ws=@vger.kernel.org X-Gm-Message-State: AOJu0YywYmyE6nwwl3wGYwbzd+N7Wr4oLILZd2oy2fFD9GfPM/DxXKOP iArJXBPgLTxLIMuwEszPaQYSID6UKj0n02LT+Vs6Y7EmM8mLR31S3SOT1960A9M= X-Gm-Gg: ASbGncvtxYzzrsVmbeEIODpIqp7eigRAupZVoiUJLISErlKjkPvsXNpueVDAnu5GK55 AShxxZW//v/Z5sxXeLmkcuU/aQprAASdwl+9BfEdb6+twqkGiwH27PVPayXUKJAt1C4DE71aCBg ErKlKMDe4TWTAlU0qpFNo6pKIUQ7NkQ2tuVwOLGan4GdYezhrP9cOwGsSzWc2qmHpVRgKnoG4kX 1D7gFC7ESi6oXxZCvs5GeEBGp+gQGX41G5QhnfIQPfUiDD9CrhOwqbIug6XJKNvBVn3DMD2qaMY s94ATcIhAKQbWk5lMD3FZgVNg/1fqr+O+6eycMoyE7IRVg== X-Google-Smtp-Source: AGHT+IFputIgv6zhtm+v7+MGBN3nI7X+BtRN1fT5rRbozYZS+RzAoNXF9CqISuMs9K5H8TPGERcLdQ== X-Received: by 2002:a05:600c:4e51:b0:439:8878:5029 with SMTP id 5b1f17b1804b1-43d38f72af6mr2448325e9.2.1742231296757; Mon, 17 Mar 2025 10:08:16 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:16 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 09/18] riscv: misaligned: add a function to check misalign trap delegability Date: Mon, 17 Mar 2025 18:06:15 +0100 Message-ID: <20250317170625.1142870-10-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Checking for the delegability of the misaligned access trap is needed for the KVM FWFT extension implementation. Add a function to get the delegability of the misaligned trap exception. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/cpufeature.h | 5 +++++ arch/riscv/kernel/traps_misaligned.c | 17 +++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index ad7d26788e6a..8b97cba99fc3 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -69,12 +69,17 @@ int cpu_online_unaligned_access_init(unsigned int cpu); #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) void unaligned_emulation_finish(void); bool unaligned_ctl_available(void); +bool misaligned_traps_can_delegate(void); DECLARE_PER_CPU(long, misaligned_access_speed); #else static inline bool unaligned_ctl_available(void) { return false; } +static inline bool misaligned_traps_can_delegate(void) +{ + return false; +} #endif =20 bool check_vector_unaligned_access_emulated_all_cpus(void); diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 3c77fc78fe4f..0fb663ac200f 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -715,10 +715,10 @@ static int cpu_online_check_unaligned_access_emulated= (unsigned int cpu) } #endif =20 -#ifdef CONFIG_RISCV_SBI - static bool misaligned_traps_delegated; =20 +#ifdef CONFIG_RISCV_SBI + static int cpu_online_sbi_unaligned_setup(unsigned int cpu) { if (sbi_fwft_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0) && @@ -760,6 +760,7 @@ static int cpu_online_sbi_unaligned_setup(unsigned int = cpu __always_unused) { return 0; } + #endif =20 int cpu_online_unaligned_access_init(unsigned int cpu) @@ -772,3 +773,15 @@ int cpu_online_unaligned_access_init(unsigned int cpu) =20 return cpu_online_check_unaligned_access_emulated(cpu); } + +bool misaligned_traps_can_delegate(void) +{ + /* + * Either we successfully requested misaligned traps delegation for all + * CPUS or the SBI does not implemented FWFT extension but delegated the + * exception by default. + */ + return misaligned_traps_delegated || + all_cpus_unaligned_scalar_access_emulated(); +} +EXPORT_SYMBOL_GPL(misaligned_traps_can_delegate); --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C37781EDA10 for ; Mon, 17 Mar 2025 17:08:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231302; cv=none; b=ut/z/N69NNu6zOTGFy1lEvpV09GSGgrJ2BTVmkRnZCSYNRHqdC1FUHyqdHpqGY7QGhhPuCl6H69OE8sTkpuUbjeVzyZZsHBzudd2fVZBC1jMbdXO6Vd0mS1ip73Y3XJjaufZoToJsqpeEhWCPiz43KR2JIVCam4YTR2Q64eYvIg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231302; c=relaxed/simple; bh=B4l5ww4xM3ybuxVDnFD7O4s6SCugiqPi0tOYv0B/adg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qlM8F0bPuncy9N0olSAG/WduGHyiO4uj6Uyz5mrnHccNmNmEs4/LwKvQ3E2Hb2iqvn2QBcI1SQrSP9RL5c01AWcfUEhAEYg6ZFlMRQlrkp984tgqCvueM6T/ZdVX5tQ3ptgXZlI5mRcRYzAfs2LBggI/RmM3y1BfNgd8pC9KAyo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=TH0Wpr6k; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="TH0Wpr6k" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-399676b7c41so700971f8f.3 for ; Mon, 17 Mar 2025 10:08:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231298; x=1742836098; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z9Vwlc46bZsQyt2QxW9m2l1M9vTOam7Mm6HyDDfLEZk=; b=TH0Wpr6kUlHO8JCQ8f1xc1hUwdTwBLerRFQ1twh7EsTet8H64iJxR7jlfxf4PtwVsk VXRN09JsGKDl7bY4vCW0Ht2UFXJ1kdeHbPrjlSVA3Eho+hcUH1ZUF9cUDYufFnkKkWbb f4ETFjelcXuCl7cyxhkKFvNpn4547+fOHY9Rrso8D78/OUSgoe3wKWtPwfYxqSA+ma9d xPemuYDNAL9vwUieKeknaKYh85TIPPhPeNbNeII+DXeoIiPQ2NGhnzSf4n6rb42h+ICU /5BZuHy9st5KLNxj/lERhDOCDRtPCd0+D+MqaLN3MhM0rVeQyU+XrA80YfffflQxVQA4 swUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231298; x=1742836098; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z9Vwlc46bZsQyt2QxW9m2l1M9vTOam7Mm6HyDDfLEZk=; b=OqEJHF3SlvsTSaER8JtxKyh3+0IMTo5falV4FchEQNk/NFU552ZS8h5tm8ipEcUo0+ L/YZa+aAbjS9kTbrns+REgUxUQ6u967Jb3FHO6qBiKxTSgWms+IDnejqT6r7ewz5klZ+ f2a5IjtGm7Cma6LdFtc/a1LY9EprDLL+1iGrTnV9BZypVf0zwgtCTJpagLTrSGhAvE/J q1SbxshQliyWklau0Yitwnef4Tif9bNESkpvQZhWN9SeGYmTAAvryQODnxLm2QqZfEj3 T5aglesaT1Y6YqPgm6tBTBXfZ/Ld0h82aUpGjBP6Xboy6nQMhAep894JhSo+03TFugFz YUpQ== X-Forwarded-Encrypted: i=1; AJvYcCWA6ASr8YZqLyKnukIDgk0OQ/jCx8LFmmqfKFLz0fq66aqtfKf5bkm4BCtz18OGTSk2fkjYR2lcMxZpLd4=@vger.kernel.org X-Gm-Message-State: AOJu0YyNRiemKaOxKow+DGP9N9eTTpF43Iu5wwQuZvzIhEpjw8kuunIS 6tJt9UpzfiQ2KBj/y0IC0KcHDE85OoDwRw5wGhsCZ4wXUTaDGVNeREx2pILqbtc= X-Gm-Gg: ASbGncvgdV/JkCmO8ISqnAKbi37BSXu8lJC7NbarNtDKIzPwhdPWNHeSV+99iY5otHQ +3+2//ZrkaXqg546np3dd4MFMvVhIMvuwg7WEnnKWsyqEyi3vvufEkxeWVWViaD+AK844YVwfxd 9qo3NA3dwdbyVgODGFQyg+xsb3AMVVQCaEkGQdvESbnHqfWCxR1XXd1Lfb/QRaYOOExTC8bpcyA vTHSp9T2dzX6zRUObgfM3OjykiXpw+XNWx4PIDwhOdYLu37f04Rk1RYleoYeeyC8qlQ4Sl2Sirl 4TC9Uxfl8NxJian6tF0r07dJLxw3MDgV7K/XWttPgwOKlQ== X-Google-Smtp-Source: AGHT+IGA2Rdk6jf2tb4X7esu4pon4fXkJaTK84F8Y0BwgA61Xp90vVw97TtNBjS5pxzMobEPki6sdQ== X-Received: by 2002:a05:6000:1f8e:b0:391:253b:4046 with SMTP id ffacd0b85a97d-3971d51f3f8mr14939898f8f.16.1742231298143; Mon, 17 Mar 2025 10:08:18 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:17 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 10/18] riscv: misaligned: factorize trap handling Date: Mon, 17 Mar 2025 18:06:16 +0100 Message-ID: <20250317170625.1142870-11-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable misaligned accesses traps are not nmi and should be treated as normal one using irqentry_enter()/exit(). Since both load/store and user/kernel should use almost the same path and that we are going to add some code around that, factorize it. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/kernel/traps.c | 49 ++++++++++++++++----------------------- 1 file changed, 20 insertions(+), 29 deletions(-) diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 8ff8e8b36524..55d9f3450398 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -198,47 +198,38 @@ asmlinkage __visible __trap_section void do_trap_insn= _illegal(struct pt_regs *re DO_ERROR_INFO(do_trap_load_fault, SIGSEGV, SEGV_ACCERR, "load access fault"); =20 -asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt= _regs *regs) +enum misaligned_access_type { + MISALIGNED_STORE, + MISALIGNED_LOAD, +}; + +static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_acces= s_type type) { - if (user_mode(regs)) { - irqentry_enter_from_user_mode(regs); + irqentry_state_t state =3D irqentry_enter(regs); =20 + if (type =3D=3D MISALIGNED_LOAD) { if (handle_misaligned_load(regs)) do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, - "Oops - load address misaligned"); - - irqentry_exit_to_user_mode(regs); + "Oops - load address misaligned"); } else { - irqentry_state_t state =3D irqentry_nmi_enter(regs); - - if (handle_misaligned_load(regs)) + if (handle_misaligned_store(regs)) do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, - "Oops - load address misaligned"); - - irqentry_nmi_exit(regs, state); + "Oops - store (or AMO) address misaligned"); } + + irqentry_exit(regs, state); } =20 -asmlinkage __visible __trap_section void do_trap_store_misaligned(struct p= t_regs *regs) +asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt= _regs *regs) { - if (user_mode(regs)) { - irqentry_enter_from_user_mode(regs); - - if (handle_misaligned_store(regs)) - do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, - "Oops - store (or AMO) address misaligned"); - - irqentry_exit_to_user_mode(regs); - } else { - irqentry_state_t state =3D irqentry_nmi_enter(regs); - - if (handle_misaligned_store(regs)) - do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, - "Oops - store (or AMO) address misaligned"); + do_trap_misaligned(regs, MISALIGNED_LOAD); +} =20 - irqentry_nmi_exit(regs, state); - } +asmlinkage __visible __trap_section void do_trap_store_misaligned(struct p= t_regs *regs) +{ + do_trap_misaligned(regs, MISALIGNED_STORE); } + DO_ERROR_INFO(do_trap_store_fault, SIGSEGV, SEGV_ACCERR, "store (or AMO) access fault"); DO_ERROR_INFO(do_trap_ecall_s, --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2FBA1F460B for ; Mon, 17 Mar 2025 17:08:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231303; cv=none; b=sJFbNgLp5RO2tq0X/eyZ6z8GqxHBGkeXI/QJ8If8zhY2/UoTy6kgQnbRkciOK1L/CYdbEuQupkGys5KRcefjM2ev1Ax1gkUOwHQ3UnusqVIcj5dWtHD5xGd6L4tMj0LFlFOaaJ3ao/Xw2myTxGuhViGtCXFkjBsYgcoE7EsZocI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231303; c=relaxed/simple; bh=o8LicozigsBJPUxfw0UjH/+haPfd2EDEodthfJ8bhLQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bQOYgMAimgTnuVnxwXB6Q8QKHqoaBoaKkdwC3XTjEJDsl7r1tBjQRBdeneNO4q8d+RQnup8KSg6kMgQNsz7J0PRcR5kqyN18r3AmI0nVBJaA4IpFxoFzAHlRhJfLd3JMATxO0//E7xlwsnMcprpuX93DAI2Wjh27p8UCtzb7WeE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=B6RaHu7w; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="B6RaHu7w" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-43cf58eea0fso12575255e9.0 for ; Mon, 17 Mar 2025 10:08:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231299; x=1742836099; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NTEMNxwWUDdJDHTSWR5BaYosnBDapUg7Ev6g031TeV8=; b=B6RaHu7w/vTAvs3i8oBRPcmJ8fCdI1+ASycCRjRmU/aXVuSytN2BuFIBoIc/VNDS5a NM94toxBLBIm/xJCFrkkhoiXwUpvIWUSb2+QdDFKNuxKKtVxkTcAGDRu8jO8QoM3x1Tj UgBIsidJk3qPU5H4UexAOs+t6ejR2FHSdgnPPqiZAHZ9zyFGESmhdYPzQVKSx4zDjoGn vxbI1J96zO5+8wdjI5Qpr6x3DnEQQoh2/vy3LjWzuvxVSJn6EVEXhJzwdTtD9C6XzQ3Y 958QFE5CsO7gK5IobDmz9kvdgiUHGgDP2kOqv8+gMczVqY6NDEra89bHpU0q5sfomCoV XrlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231299; x=1742836099; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NTEMNxwWUDdJDHTSWR5BaYosnBDapUg7Ev6g031TeV8=; b=eB72ar7qmp81HJpFFFJedhV8j/5dFZP4sX/ZdskU7XddL+WgM2xpKYPi7UQ/DR1Rx9 FUBG2zCGU6QNCAwCHYnsw6Hu8B30zO3WK+Y+ZVQbeAim7cRJxfpYRvmbf/NYdb1CdeZe o3EG+1xB+vdYhnLpgkf3ij1sv1N8w7Q2l/uKp5+/iEGmxF1o68LnknGCvTDBnG5MEIGC KeQtPtwwQRUWaRsVLZRZvW6sSLfhJ13w6GtN8+GCWDaRBD3eUVgrw6VTdfLmG5lq0OB0 e4Rk6P8NdomFXPr6iBLHYKeVu5fv5KSHDDPA1cyFn1d/vH1MCd6ZqUF8EmAkCwdip9Ab uefA== X-Forwarded-Encrypted: i=1; AJvYcCUDJ7+NgmXpQAw2k/c7xE8DdbXPmPfzER8XATzbvNaVYjs1rAUquE5BO2TZteBC4dzVcRaV0j2rdKafgGw=@vger.kernel.org X-Gm-Message-State: AOJu0YwHcCghDY/Lgktu6dATVp6JMgr5xmmhERR9fKxMeopI7GozXZul wNb/kb/invT6lLz6I6ALoGWxLKUiS3YpTrV+5UXlalp+GHx07Yis/Q7YQSSPH9o= X-Gm-Gg: ASbGncsMpNLinkGvztXfvFm8WeIO93EehUb3Uc6a0MzYg5SGUGlITAY7pWWct3xfQkj OaBT6OKt05QyahCOCiX73D2XbzpiCogn9zdoLMMKw59sriJEzqdRZvbU22LpKR4Td3juT+WY9Y2 m50ICO+Pvd6fWEXFYJiIwQit8OSKp9uAc+xaKDOIR+vku7ROUyNyJpbJqdKss3ozY1O5JZHCX92 R3Ue7K0qIs3blVGQOSrHRkjQVXjPUStPYYvtZXBv3PVhLBdE7vETqMuhS/+ghhRHVS6oCE3OJB8 zMM4ytY1g9dAcSTOBiVIi2/o3NwcAuvVtTwXIrmzt4xvDg== X-Google-Smtp-Source: AGHT+IF/jPZgtuKO9F2UOB0NNJAFXUmhCJVLus67Lul9R3bvXGZReu7Tw2V0Z3eVtQhps9kA5NlJfg== X-Received: by 2002:a05:600c:4451:b0:43c:fa24:8721 with SMTP id 5b1f17b1804b1-43d1ec8a44cmr134590325e9.17.1742231299101; Mon, 17 Mar 2025 10:08:19 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:18 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 11/18] riscv: misaligned: enable IRQs while handling misaligned accesses Date: Mon, 17 Mar 2025 18:06:17 +0100 Message-ID: <20250317170625.1142870-12-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable We can safely reenable IRQs if they were enabled in the previous context. This allows to access user memory that could potentially trigger a page fault. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/kernel/traps.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 55d9f3450398..3eecc2addc41 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -206,6 +206,11 @@ enum misaligned_access_type { static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_acces= s_type type) { irqentry_state_t state =3D irqentry_enter(regs); + bool enable_irqs =3D !regs_irqs_disabled(regs); + + /* Enable interrupts if they were enabled in the interrupted context. */ + if (enable_irqs) + local_irq_enable(); =20 if (type =3D=3D MISALIGNED_LOAD) { if (handle_misaligned_load(regs)) @@ -217,6 +222,9 @@ static void do_trap_misaligned(struct pt_regs *regs, en= um misaligned_access_type "Oops - store (or AMO) address misaligned"); } =20 + if (enable_irqs) + local_irq_disable(); + irqentry_exit(regs, state); } =20 --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC2971F666B for ; Mon, 17 Mar 2025 17:08:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231304; cv=none; b=d3qtbxAbWMgwktLjoRAr4W7026dCr47AlMmZ41TQNHyfQ0I/7Wfi+QUJLj26UuVQSPPSvFeb6rgkrC/DJp23FSwT1rsupOxeCRx4y9qq9HYWyjQyFnZdAb1SLt88PRtcHux0bBbQc6WsEjjlk5hdsL1P7GgNG+vlCdHHtbSF/xA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231304; c=relaxed/simple; bh=NrkciCzcfMsvIfgMNhHy3LIzh0NIZkRsvpzrJFbFJ/4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=s3dUGjUQ8kuDrDTGBqiuvFClx+q1CFSLp5tuUazXIuxQbklXdCcMELh8/+7o7wY9+1WkML5P0DvrXjIies9c/YGu/f/69YZfDn502ne+0Azofjqt5J9by+/Y3IPXN6Q6tCEvk+CgUHTyPuLZRoMYlinG2CRzoA8pVDhy1K/WeU8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=tHO/2EPG; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="tHO/2EPG" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-43cf05f0c3eso17349445e9.0 for ; Mon, 17 Mar 2025 10:08:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231300; x=1742836100; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K8U+T9Diad+CXpLV3u2uHxRVp5OvAkVUCVXAkQQVM7Y=; b=tHO/2EPGYoeUHl4RrmFGDy77abGJZlR4BpX/cXBzxheJJ3zHn8pJetgqKmvg7L101X BHuL94HBPfcS60utSgZOudJQ3G85MLcvB6lGapvIbEz6yaE4mkJPfrIqG/48gMGYdqyo l0EUM3aIGVoPO0xAULYa1wW5Oxcw7aZfxDgjd9VlloeG8G5lns4Ske6kYmEuDGn5+4gX 1YcMGB4IJoKaveNqU36LoQPOY8LCjgLjcyUGxqlViAjySMi1jfwtOVrPfGhH0hnMLIPE l9WXxZx+Eg0e1iEOVw/CWzWgBxqAbFLF0WXtdvcJbv2lXWGhkvWiBHqcjNWoD6n8s1Vt R09A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231300; x=1742836100; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K8U+T9Diad+CXpLV3u2uHxRVp5OvAkVUCVXAkQQVM7Y=; b=b1ZtJPaJcll9+ZKXT8ZS1pk26UCkQ6phXqpUfwvQsv+nqznX1VKEi7VvvnlSXmx2Ic 6oli0kNM7KIpKP05pQGu483Wld2kVciuscLoZEbOX4o5VwvWMIwn0T2wa1ZqXN/3Mdrh tAHvbzpU3avdRXRWAMQzFUMOl64CHAJUqY/MHzZT/sY7ZBIHlZr8hgaGhJ4FlWVI43vq N60owoKeSgkjsJJKfyfUqdClFHwgbdPcsIfev1MyMqaOkUwmUlcLOKiyHzs34KT9P0gt EIvu/fqoJiKUhWwHgmuoMpCj8c8tctDfc3xWnIuRulE+TytwVhyhba+bEP0Gc8Y4O+32 KQkw== X-Forwarded-Encrypted: i=1; AJvYcCVlcQUEE0x4X4p9m4GoWqKKsiDQoMDVRrQcRIDABXd25e9yMbjm13gBJPWr+9yW/l+ys/1n0TNzzX9+kdY=@vger.kernel.org X-Gm-Message-State: AOJu0YxhGvVo1ncAilshkGTMQC8EWArNdOn9GdlSAH+L5AzBjuT2nJ4t C6ZxfxaUwUSFs1UB61q3ev3w4BpHkJDGFp3y74jzyQuMPl1Kw2IMsVW5aPXAXvA= X-Gm-Gg: ASbGnctVD56odUSOOcTpqbmOiCCIcvZ8G5YCkm33rVX0MP9xICIBmmjakDyuw7uaocO cYW97qh1Mgr3V49zYw7NnsE/8QqUC20+oQTLqHDs0Sj7+uffh1ssJaXhpTgq4eGRkbIlyeQF85C JfXA4UQFN/N/mqJkYWZN8f1AqCFEmuoXBSVVDbgO4Xby/h6sKvSFPi/2+Cb6E3ySvS4RjWwqy5n Q5FJIcLfNIm7ZInUyXrpuXO1I4w2OGVxdTnQBT7zj5JwEr4XaSishOQ3E4TEgVoVMil7Wja1UR0 2FR0osqBPIelYIh1ZEkMraoSvNbgAQOFalcUDn4Y4pPJsg== X-Google-Smtp-Source: AGHT+IFmrC4L2BBEGglHCKwEAqKUy9nE7lsKyuSMTJqBTFYq88vyNhKpBkqIwmbEPtXGJrbb0KbkPQ== X-Received: by 2002:a05:600c:4ed0:b0:43d:ed:acd5 with SMTP id 5b1f17b1804b1-43d2a2eca5bmr70290895e9.10.1742231300051; Mon, 17 Mar 2025 10:08:20 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:19 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 12/18] riscv: misaligned: use get_user() instead of __get_user() Date: Mon, 17 Mar 2025 18:06:18 +0100 Message-ID: <20250317170625.1142870-13-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Now that we can safely handle user memory accesses while in the misaligned access handlers, use get_user() instead of __get_user() to have user memory access checks. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/kernel/traps_misaligned.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 0fb663ac200f..90466a171f58 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -269,7 +269,7 @@ static unsigned long get_f32_rs(unsigned long insn, u8 = fp_reg_offset, int __ret; \ \ if (user_mode(regs)) { \ - __ret =3D __get_user(insn, (type __user *) insn_addr); \ + __ret =3D get_user(insn, (type __user *) insn_addr); \ } else { \ insn =3D *(type *)insn_addr; \ __ret =3D 0; \ --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DF381FECAD for ; Mon, 17 Mar 2025 17:08:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231305; cv=none; b=JoEtwa+39wCyhM3o2pSx+2ZmPDIb5/DiBCyfKR3rR1uStuCLKJZ0/r7rtybq810cTwTQIXNBV+BoU1KVFJAppk9DMvJ1B5Q5z9YPxcu9cf7AYaROXRqfD/4ENBHjj7UM+SAXxXvAyuD5d4jIfmAy6ZoLaW8K9dt53Z6VI//HU90= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231305; c=relaxed/simple; bh=Nf3XuDar9gitRVwziVjGXEjo/ltPNzme/nCKwMDO140=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PZuGUQADIsr0FoJ4dEu8i600gezI0L7inQ95Sk1KotQGwN7xoYXR0kHlFAe+HMuxfZDpgr6MKlmLVgPtL5ufDU59dFylqej3yjqEvr+EAQKjljA1Xn8WHpAbOZq3aSHQueWGjeWiESSNfTj7YIpiUCpnl3q0ci+rQGvpI7bKlVs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=ofsUQIZx; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="ofsUQIZx" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-43ce71582e9so16000705e9.1 for ; Mon, 17 Mar 2025 10:08:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231301; x=1742836101; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2pNqCCOYMsZxxXyyqHIS5snuORKLAQN1trvRZ+awEuI=; b=ofsUQIZxvs8LTJ56g982crtRu6dTuFCOkCYZVrQCWEM9tNwWGc1A6HRz94CH1V87MH B4CtaDJ5EA8iRA8aj+Qw3axJREL5n9xqwSCj4nwn01RplBuROB7Lz67ZX7QT6akWUHah gopoaQKzRnZugbRPKYYYXR9uq1Hc0tC6QABH79m51W+4O9+a8g0LjEB6zxWDTjNyB/Fj 8BcvwfOE83wsZKwYkLJpajNNfRWPrcq2hcAp7fU9fDhGmQfXVMFfgX1MmzlbctXI6MSL 8XvmcW/VO12HZtFd+jtyTPhMJXyqBxV95XQk0bhtTKu5XLpIdVZmbhetpI9hvCzkqvpJ qfww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231301; x=1742836101; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2pNqCCOYMsZxxXyyqHIS5snuORKLAQN1trvRZ+awEuI=; b=Ncl6gTtS3KwHSLxMfzNhPVrfAmoHF1/NnCCwgS3VKtljwNSGhBwLHnAKNsb+6qebl9 U2/D3nIvBUP9bFUe/PBjfsjlvHEyvMKxo1XPqIQbd+W12MqAudGDa4sFIfBEL8EVcAgI fqLOii55LR9JGDVkDWL/9eeshNcRW6c8K641ONz04DTsFpo4Q5aI76r0gsXX7xssT1sY 5OXRE4IcQtJ7Me3WpEwX55iSVyFrLjcOzC9U9D+yD6J/tlXID/Po4E1zZ17hTCxBUueZ 4QMHdb+ya7IngBk8n1NisNuYo5Dm08YLJAJ0zfUxGzNEgYB/qODRhYrEt08fQuJQBC46 04mw== X-Forwarded-Encrypted: i=1; AJvYcCWTNCkYrJC4y/qI2afZz0UBAlW9mqvIJqmyZCHDSQTS5zjm3JR55MhLY8u4jRLN8ELYGCOMfbItO3vauOo=@vger.kernel.org X-Gm-Message-State: AOJu0YwVcHo9WUO54D+L6qD3le2PTpES+ne46jDwGzkkDbzZaXjutaXW 7o/1ue8Posa0Vxg4UVSEedMBvKbT+EEjE75Jx1rVQ3w0BvL3fmP8ISjJEvCLjaE= X-Gm-Gg: ASbGncuWBSI4YwTSLq3NGs4IA4mH4kEIXh2BNGn8mKSxE+RZfwp8ha0zjUke2WTlWa8 5/27BuJ70rsK7RkDN/ku5xAkpBRlLN4U2Rbm7WDiXvvotol29852HKxOqycpH9ToUnd41bN6CsO Q7HAu93VfUP6prPoRAfelLdc0zqG1t3zRDTkbyefx9RPOWe3b9Vg7K9hgwk/chXCeL3k32C+UVn Y7DwGecn0FMGOBNgG/OH3HFzUrDVihtSEENAhuWD7KM38rj7YZlTan6/CzEqKRZhQFNmujHHIw2 HbyIQV21wkdQM6jkLZhUqEdF0Vry2Zr31wSxfesSZCo+mA== X-Google-Smtp-Source: AGHT+IE6X4Zl2SvCnLBWCWxVkBGrawQ8DSM4qV1sZG6LsJ3FF5B07Zi+O2FlbpqV8a0E2j6PRS6VBQ== X-Received: by 2002:adf:b183:0:b0:390:f88c:a6a2 with SMTP id ffacd0b85a97d-3971f12cd8emr13396928f8f.39.1742231301480; Mon, 17 Mar 2025 10:08:21 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:20 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 13/18] Documentation/sysctl: add riscv to unaligned-trap supported archs Date: Mon, 17 Mar 2025 18:06:19 +0100 Message-ID: <20250317170625.1142870-14-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable riscv supports the "unaligned-trap" sysctl variable, add it to the list of supported architectures. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/admin-guide/sysctl/kernel.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/ad= min-guide/sysctl/kernel.rst index dd49a89a62d3..a38e91c4d92c 100644 --- a/Documentation/admin-guide/sysctl/kernel.rst +++ b/Documentation/admin-guide/sysctl/kernel.rst @@ -1595,8 +1595,8 @@ unaligned-trap =20 On architectures where unaligned accesses cause traps, and where this feature is supported (``CONFIG_SYSCTL_ARCH_UNALIGN_ALLOW``; currently, -``arc``, ``parisc`` and ``loongarch``), controls whether unaligned traps -are caught and emulated (instead of failing). +``arc``, ``parisc``, ``loongarch`` and ``riscv``), controls whether unalig= ned +traps are caught and emulated (instead of failing). =20 =3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D 0 Do not emulate unaligned accesses. --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDDF42036FD for ; Mon, 17 Mar 2025 17:08:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231308; cv=none; b=SebxNr5lbMLOuYCXeUd/LubdVHsQ+obTAcj7MDwjsJIzg5zXGnm86cgwrJaUtRB15aN0oTdP2lARyv+YyfeY0dxOOzDOjrNfA9EMTtUAw3XMwN43NqZo32DZ4G6AfFAG7i0UdDVT5OTzHRHMUbVbtmVos5Duq19X+ZMDgk7bFYE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231308; c=relaxed/simple; bh=qX5so5AU+yLLimNIkDktcyO1mUKmJ4t5Tli6ol780Y8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WyM8dPGn1WV2ZSNgnuY0NLhz5VDIdYruWpRrJeXNguzCdFa96UMqgtBxdy97bi/92hqigMboZJCM2YP/gsbyDdtB2j+d3i3pfin2C3CgcejXq/ot4Wdpx5p8P8I1lOxGg/N860LTyoSVrGOT+9VG/Kd6cUi5MVIcvWGetXkrQqI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=13NMucgk; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="13NMucgk" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-43cfdc2c8c9so13748195e9.2 for ; Mon, 17 Mar 2025 10:08:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231303; x=1742836103; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VKDplUA2XX/hbzyOxbYWLc7Q9RboQ/w3e3i+SZL4wNg=; b=13NMucgkidWjHq5gnUW9fA6sSEIzYtRYMC4HyXy9xKY0YomuVuFr+z/GlkUsGQA4ND 4uSibDEfkbxBjN1lli2gMP3E1Lg1LF69srKx8Ltcl8cJr4uj5lVM+MIv2sTs9OEFM3zr VuJs3kP3iAMrf+xK1R95twOS6qH5n0UVISdzEofVojZTvPpl9ePNBs6TknVT9AZwUFpH nNSdem4QOAE64Uz1AjrR6PbMTnaLoD0ubnZtH4mTt5nNKCP2rjv7rmoaS2+Ik38FiXux Z6Iq05MGiguu6wKGemGStSk6dvfxmrQlsgYugZK2GxEQq5nmcsgcJeqDuDFHmb/iL49v e5YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231303; x=1742836103; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VKDplUA2XX/hbzyOxbYWLc7Q9RboQ/w3e3i+SZL4wNg=; b=VL39AtiNIiE+7KjTBUoI/0iuja6F1dqlYaOSZ2Y/GEGrrSbqaLjW6JaepeqXCgAMeV vmcNq8vkAXkC2tllmpKpqqt849lLYJfMKLPYcKmfkgFMVyQuOQkk4Ojy/v00PDOP9rZ5 kxjMa2dwxjoXq8IG30PWuO0s3uLNzxZuvFEL/AAwytWeb0B/+KcfFfnIWy7kF1QHML/+ mppYOfOzKbZa9Y0fsg9GLVF+pa0zFZhBYNqKDxZvYdKIAPRR3wEG5ehUEbnjUkdzDAjJ hWV/RrNEQOVwgOknRtmR3Asz6ypIwmOT9KTsXh7v0Mw6WG75aAXZ7QSom5mDK3kbE4xR OmdQ== X-Forwarded-Encrypted: i=1; AJvYcCXd2ExmFdcc8vFHtb5IHMqfyidP6unfVXDXgcS9ezb1ZwhIuQUkrEvsjP0AdSKTOAkqX4aPfTXnoXiWG7I=@vger.kernel.org X-Gm-Message-State: AOJu0YwxKiYAZv+HqPn/J5g8K4R0y7/XnXYueJGreFBYYTTnJ1Os7sJV JY56zRgt+7g9DuggL2faL6upxoQQQzSMQf/lh2zlst9qw7JFGaPKqlr32WvgNhg= X-Gm-Gg: ASbGncvhyC+LwYucjDvH4TuOw5foYP+4fFMdmmbzcGrcR+lvD8ClNvrEPaHDFBG6KC3 yPuIKd139m26b+SPPsW3Ek2g99rkRAghEmexjb6fRUJ+0DS8poC2On19SgpWg7EIFKiNb5/iTwE zmJfuxBPyU/FeHMzuffZRjH06wYOyBcbMWrGjrHuSzuiPVRYqx9nD/nMA0iHDFGPdzWYdmGbvLH HgPcDFeaLNrkpnDVwmo9I6VxI4/F6afjsqUw7cG6pdk6etIYlyqSk8sMg5DlKivrG+i6WecjiGT WM9YPwCOxyzOXivkpvmtmy58OCVC1LYz3WEp9+FM/X0TRg== X-Google-Smtp-Source: AGHT+IHYqakxMqLykAu8hVgungq+pEq9jN18lc5kC73JGVKr25cJlS/60mBYd+yEImb3bsX8Hv6BZA== X-Received: by 2002:a05:600c:a00b:b0:43d:cc9:b09d with SMTP id 5b1f17b1804b1-43d3898770amr5615915e9.20.1742231302877; Mon, 17 Mar 2025 10:08:22 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:21 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 14/18] selftests: riscv: add misaligned access testing Date: Mon, 17 Mar 2025 18:06:20 +0100 Message-ID: <20250317170625.1142870-15-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Now that the kernel can emulate misaligned access and control its behavior, add a selftest for that. This selftest tests all the currently emulated instruction (except for the RV32 compressed ones which are left as a future exercise for a RV32 user). For the FPU instructions, all the FPU registers are tested. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- .../selftests/riscv/misaligned/.gitignore | 1 + .../selftests/riscv/misaligned/Makefile | 12 + .../selftests/riscv/misaligned/common.S | 33 +++ .../testing/selftests/riscv/misaligned/fpu.S | 180 +++++++++++++ tools/testing/selftests/riscv/misaligned/gp.S | 103 +++++++ .../selftests/riscv/misaligned/misaligned.c | 254 ++++++++++++++++++ 6 files changed, 583 insertions(+) create mode 100644 tools/testing/selftests/riscv/misaligned/.gitignore create mode 100644 tools/testing/selftests/riscv/misaligned/Makefile create mode 100644 tools/testing/selftests/riscv/misaligned/common.S create mode 100644 tools/testing/selftests/riscv/misaligned/fpu.S create mode 100644 tools/testing/selftests/riscv/misaligned/gp.S create mode 100644 tools/testing/selftests/riscv/misaligned/misaligned.c diff --git a/tools/testing/selftests/riscv/misaligned/.gitignore b/tools/te= sting/selftests/riscv/misaligned/.gitignore new file mode 100644 index 000000000000..5eff15a1f981 --- /dev/null +++ b/tools/testing/selftests/riscv/misaligned/.gitignore @@ -0,0 +1 @@ +misaligned diff --git a/tools/testing/selftests/riscv/misaligned/Makefile b/tools/test= ing/selftests/riscv/misaligned/Makefile new file mode 100644 index 000000000000..1aa40110c50d --- /dev/null +++ b/tools/testing/selftests/riscv/misaligned/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2021 ARM Limited +# Originally tools/testing/arm64/abi/Makefile + +CFLAGS +=3D -I$(top_srcdir)/tools/include + +TEST_GEN_PROGS :=3D misaligned + +include ../../lib.mk + +$(OUTPUT)/misaligned: misaligned.c fpu.S gp.S + $(CC) -g3 -static -o$@ -march=3Drv64imafdc $(CFLAGS) $(LDFLAGS) $^ diff --git a/tools/testing/selftests/riscv/misaligned/common.S b/tools/test= ing/selftests/riscv/misaligned/common.S new file mode 100644 index 000000000000..8fa00035bd5d --- /dev/null +++ b/tools/testing/selftests/riscv/misaligned/common.S @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 Rivos Inc. + * + * Authors: + * Cl=C3=A9ment L=C3=A9ger + */ + +.macro lb_sb temp, offset, src, dst + lb \temp, \offset(\src) + sb \temp, \offset(\dst) +.endm + +.macro copy_long_to temp, src, dst + lb_sb \temp, 0, \src, \dst, + lb_sb \temp, 1, \src, \dst, + lb_sb \temp, 2, \src, \dst, + lb_sb \temp, 3, \src, \dst, + lb_sb \temp, 4, \src, \dst, + lb_sb \temp, 5, \src, \dst, + lb_sb \temp, 6, \src, \dst, + lb_sb \temp, 7, \src, \dst, +.endm + +.macro sp_stack_prologue offset + addi sp, sp, -8 + sub sp, sp, \offset +.endm + +.macro sp_stack_epilogue offset + add sp, sp, \offset + addi sp, sp, 8 +.endm diff --git a/tools/testing/selftests/riscv/misaligned/fpu.S b/tools/testing= /selftests/riscv/misaligned/fpu.S new file mode 100644 index 000000000000..d008bff58310 --- /dev/null +++ b/tools/testing/selftests/riscv/misaligned/fpu.S @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 Rivos Inc. + * + * Authors: + * Cl=C3=A9ment L=C3=A9ger + */ + +#include "common.S" + +#define CASE_ALIGN 4 + +.macro fpu_load_inst fpreg, inst, precision, load_reg +.align CASE_ALIGN + \inst \fpreg, 0(\load_reg) + fmv.\precision fa0, \fpreg + j 2f +.endm + +#define flw(__fpreg) fpu_load_inst __fpreg, flw, s, s1 +#define fld(__fpreg) fpu_load_inst __fpreg, fld, d, s1 +#define c_flw(__fpreg) fpu_load_inst __fpreg, c.flw, s, s1 +#define c_fld(__fpreg) fpu_load_inst __fpreg, c.fld, d, s1 +#define c_fldsp(__fpreg) fpu_load_inst __fpreg, c.fldsp, d, sp + +.macro fpu_store_inst fpreg, inst, precision, store_reg +.align CASE_ALIGN + fmv.\precision \fpreg, fa0 + \inst \fpreg, 0(\store_reg) + j 2f +.endm + +#define fsw(__fpreg) fpu_store_inst __fpreg, fsw, s, s1 +#define fsd(__fpreg) fpu_store_inst __fpreg, fsd, d, s1 +#define c_fsw(__fpreg) fpu_store_inst __fpreg, c.fsw, s, s1 +#define c_fsd(__fpreg) fpu_store_inst __fpreg, c.fsd, d, s1 +#define c_fsdsp(__fpreg) fpu_store_inst __fpreg, c.fsdsp, d, sp + +.macro fp_test_prologue + move s1, a1 + /* + * Compute jump offset to store the correct FP register since we don't + * have indirect FP register access (or at least we don't use this + * extension so that works on all archs) + */ + sll t0, a0, CASE_ALIGN + la t2, 1f + add t0, t0, t2 + jr t0 +.align CASE_ALIGN +1: +.endm + +.macro fp_test_prologue_compressed + /* FP registers for compressed instructions starts from 8 to 16 */ + addi a0, a0, -8 + fp_test_prologue +.endm + +#define fp_test_body_compressed(__inst_func) \ + __inst_func(f8); \ + __inst_func(f9); \ + __inst_func(f10); \ + __inst_func(f11); \ + __inst_func(f12); \ + __inst_func(f13); \ + __inst_func(f14); \ + __inst_func(f15); \ +2: + +#define fp_test_body(__inst_func) \ + __inst_func(f0); \ + __inst_func(f1); \ + __inst_func(f2); \ + __inst_func(f3); \ + __inst_func(f4); \ + __inst_func(f5); \ + __inst_func(f6); \ + __inst_func(f7); \ + __inst_func(f8); \ + __inst_func(f9); \ + __inst_func(f10); \ + __inst_func(f11); \ + __inst_func(f12); \ + __inst_func(f13); \ + __inst_func(f14); \ + __inst_func(f15); \ + __inst_func(f16); \ + __inst_func(f17); \ + __inst_func(f18); \ + __inst_func(f19); \ + __inst_func(f20); \ + __inst_func(f21); \ + __inst_func(f22); \ + __inst_func(f23); \ + __inst_func(f24); \ + __inst_func(f25); \ + __inst_func(f26); \ + __inst_func(f27); \ + __inst_func(f28); \ + __inst_func(f29); \ + __inst_func(f30); \ + __inst_func(f31); \ +2: +.text + +#define __gen_test_inst(__inst, __suffix) \ +.global test_ ## __inst; \ +test_ ## __inst:; \ + fp_test_prologue ## __suffix; \ + fp_test_body ## __suffix(__inst); \ + ret + +#define gen_test_inst_compressed(__inst) \ + .option arch,+c; \ + __gen_test_inst(c_ ## __inst, _compressed) + +#define gen_test_inst(__inst) \ + .balign 16; \ + .option push; \ + .option arch,-c; \ + __gen_test_inst(__inst, ); \ + .option pop + +.macro fp_test_prologue_load_compressed_sp + copy_long_to t0, a1, sp +.endm + +.macro fp_test_epilogue_load_compressed_sp +.endm + +.macro fp_test_prologue_store_compressed_sp +.endm + +.macro fp_test_epilogue_store_compressed_sp + copy_long_to t0, sp, a1 +.endm + +#define gen_inst_compressed_sp(__inst, __type) \ + .global test_c_ ## __inst ## sp; \ + test_c_ ## __inst ## sp:; \ + sp_stack_prologue a2; \ + fp_test_prologue_## __type ## _compressed_sp; \ + fp_test_prologue_compressed; \ + fp_test_body_compressed(c_ ## __inst ## sp); \ + fp_test_epilogue_## __type ## _compressed_sp; \ + sp_stack_epilogue a2; \ + ret + +#define gen_test_load_compressed_sp(__inst) gen_inst_compressed_sp(__inst,= load) +#define gen_test_store_compressed_sp(__inst) gen_inst_compressed_sp(__inst= , store) + +/* + * float_fsw_reg - Set a FP register from a register containing the value + * a0 =3D FP register index to be set + * a1 =3D addr where to store register value + * a2 =3D address offset + * a3 =3D value to be store + */ +gen_test_inst(fsw) + +/* + * float_flw_reg - Get a FP register value and return it + * a0 =3D FP register index to be retrieved + * a1 =3D addr to load register from + * a2 =3D address offset + */ +gen_test_inst(flw) + +gen_test_inst(fsd) +#ifdef __riscv_compressed +gen_test_inst_compressed(fsd) +gen_test_store_compressed_sp(fsd) +#endif + +gen_test_inst(fld) +#ifdef __riscv_compressed +gen_test_inst_compressed(fld) +gen_test_load_compressed_sp(fld) +#endif diff --git a/tools/testing/selftests/riscv/misaligned/gp.S b/tools/testing/= selftests/riscv/misaligned/gp.S new file mode 100644 index 000000000000..f53f4c6d81dd --- /dev/null +++ b/tools/testing/selftests/riscv/misaligned/gp.S @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 Rivos Inc. + * + * Authors: + * Cl=C3=A9ment L=C3=A9ger + */ + +#include "common.S" + +.text + +.macro __gen_test_inst inst, src_reg + \inst a2, 0(\src_reg) + move a0, a2 +.endm + +.macro gen_func_header func_name, rvc + .option arch,\rvc + .global test_\func_name + test_\func_name: +.endm + +.macro gen_test_inst inst + .option push + gen_func_header \inst, -c + __gen_test_inst \inst, a0 + .option pop + ret +.endm + +.macro __gen_test_inst_c name, src_reg + .option push + gen_func_header c_\name, +c + __gen_test_inst c.\name, \src_reg + .option pop + ret +.endm + +.macro gen_test_inst_c name + __gen_test_inst_c \name, a0 +.endm + + +.macro gen_test_inst_load_c_sp name + .option push + gen_func_header c_\name\()sp, +c + sp_stack_prologue a1 + copy_long_to t0, a0, sp + c.ldsp a0, 0(sp) + sp_stack_epilogue a1 + .option pop + ret +.endm + +.macro lb_sp_sb_a0 reg, offset + lb_sb \reg, \offset, sp, a0 +.endm + +.macro gen_test_inst_store_c_sp inst_name + .option push + gen_func_header c_\inst_name\()sp, +c + /* Misalign stack pointer */ + sp_stack_prologue a1 + /* Misalign access */ + c.sdsp a2, 0(sp) + copy_long_to t0, sp, a0 + sp_stack_epilogue a1 + .option pop + ret +.endm + + + /* + * a0 =3D addr to load from + * a1 =3D address offset + * a2 =3D value to be loaded + */ +gen_test_inst lh +gen_test_inst lhu +gen_test_inst lw +gen_test_inst lwu +gen_test_inst ld +#ifdef __riscv_compressed +gen_test_inst_c lw +gen_test_inst_c ld +gen_test_inst_load_c_sp ld +#endif + +/* + * a0 =3D addr where to store value + * a1 =3D address offset + * a2 =3D value to be stored + */ +gen_test_inst sh +gen_test_inst sw +gen_test_inst sd +#ifdef __riscv_compressed +gen_test_inst_c sw +gen_test_inst_c sd +gen_test_inst_store_c_sp sd +#endif + diff --git a/tools/testing/selftests/riscv/misaligned/misaligned.c b/tools/= testing/selftests/riscv/misaligned/misaligned.c new file mode 100644 index 000000000000..c66aa87ec03e --- /dev/null +++ b/tools/testing/selftests/riscv/misaligned/misaligned.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Rivos Inc. + * + * Authors: + * Cl=C3=A9ment L=C3=A9ger + */ +#include +#include +#include +#include +#include "../../kselftest_harness.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define stringify(s) __stringify(s) +#define __stringify(s) #s + +#define VAL16 0x1234 +#define VAL32 0xDEADBEEF +#define VAL64 0x45674321D00DF789 + +#define VAL_float 78951.234375 +#define VAL_double 567890.512396965789589290 + +static bool float_equal(float a, float b) +{ + float scaled_epsilon; + float difference =3D fabsf(a - b); + + // Scale to the largest value. + a =3D fabsf(a); + b =3D fabsf(b); + if (a > b) + scaled_epsilon =3D FLT_EPSILON * a; + else + scaled_epsilon =3D FLT_EPSILON * b; + + return difference <=3D scaled_epsilon; +} + +static bool double_equal(double a, double b) +{ + double scaled_epsilon; + double difference =3D fabsf(a - b); + + // Scale to the largest value. + a =3D fabs(a); + b =3D fabs(b); + if (a > b) + scaled_epsilon =3D DBL_EPSILON * a; + else + scaled_epsilon =3D DBL_EPSILON * b; + + return difference <=3D scaled_epsilon; +} + +#define fpu_load_proto(__inst, __type) \ +extern __type test_ ## __inst(unsigned long fp_reg, void *addr, unsigned l= ong offset, __type value) + +fpu_load_proto(flw, float); +fpu_load_proto(fld, double); +fpu_load_proto(c_flw, float); +fpu_load_proto(c_fld, double); +fpu_load_proto(c_fldsp, double); + +#define fpu_store_proto(__inst, __type) \ +extern void test_ ## __inst(unsigned long fp_reg, void *addr, unsigned lon= g offset, __type value) + +fpu_store_proto(fsw, float); +fpu_store_proto(fsd, double); +fpu_store_proto(c_fsw, float); +fpu_store_proto(c_fsd, double); +fpu_store_proto(c_fsdsp, double); + +#define gp_load_proto(__inst, __type) \ +extern __type test_ ## __inst(void *addr, unsigned long offset, __type val= ue) + +gp_load_proto(lh, uint16_t); +gp_load_proto(lhu, uint16_t); +gp_load_proto(lw, uint32_t); +gp_load_proto(lwu, uint32_t); +gp_load_proto(ld, uint64_t); +gp_load_proto(c_lw, uint32_t); +gp_load_proto(c_ld, uint64_t); +gp_load_proto(c_ldsp, uint64_t); + +#define gp_store_proto(__inst, __type) \ +extern void test_ ## __inst(void *addr, unsigned long offset, __type value) + +gp_store_proto(sh, uint16_t); +gp_store_proto(sw, uint32_t); +gp_store_proto(sd, uint64_t); +gp_store_proto(c_sw, uint32_t); +gp_store_proto(c_sd, uint64_t); +gp_store_proto(c_sdsp, uint64_t); + +#define TEST_GP_LOAD(__inst, __type_size) \ +TEST(gp_load_ ## __inst) \ +{ \ + int offset, ret; \ + uint8_t buf[16] __attribute__((aligned(16))); \ + \ + ret =3D prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT); \ + ASSERT_EQ(ret, 0); \ + \ + for (offset =3D 1; offset < __type_size / 8; offset++) { \ + uint ## __type_size ## _t val =3D VAL ## __type_size; \ + uint ## __type_size ## _t *ptr =3D (uint ## __type_size ## _t *) (buf + = offset); \ + memcpy(ptr, &val, sizeof(val)); \ + val =3D test_ ## __inst(ptr, offset, val); \ + EXPECT_EQ(VAL ## __type_size, val); \ + } \ +} + +TEST_GP_LOAD(lh, 16); +TEST_GP_LOAD(lhu, 16); +TEST_GP_LOAD(lw, 32); +TEST_GP_LOAD(lwu, 32); +TEST_GP_LOAD(ld, 64); +#ifdef __riscv_compressed +TEST_GP_LOAD(c_lw, 32); +TEST_GP_LOAD(c_ld, 64); +TEST_GP_LOAD(c_ldsp, 64); +#endif + +#define TEST_GP_STORE(__inst, __type_size) \ +TEST(gp_load_ ## __inst) \ +{ \ + int offset, ret; \ + uint8_t buf[16] __attribute__((aligned(16))); \ + \ + ret =3D prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT); \ + ASSERT_EQ(ret, 0); \ + \ + for (offset =3D 1; offset < __type_size / 8; offset++) { \ + uint ## __type_size ## _t val =3D VAL ## __type_size; \ + uint ## __type_size ## _t *ptr =3D (uint ## __type_size ## _t *) (buf + = offset); \ + memset(ptr, 0, sizeof(val)); \ + test_ ## __inst(ptr, offset, val); \ + memcpy(&val, ptr, sizeof(val)); \ + EXPECT_EQ(VAL ## __type_size, val); \ + } \ +} +TEST_GP_STORE(sh, 16); +TEST_GP_STORE(sw, 32); +TEST_GP_STORE(sd, 64); +#ifdef __riscv_compressed +TEST_GP_STORE(c_sw, 32); +TEST_GP_STORE(c_sd, 64); +TEST_GP_STORE(c_sdsp, 64); +#endif + +#define __TEST_FPU_LOAD(__type, __inst, __reg_start, __reg_end) \ +TEST(fpu_load_ ## __inst) \ +{ \ + int i, ret, offset, fp_reg; \ + uint8_t buf[16] __attribute__((aligned(16))); \ + \ + ret =3D prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT); \ + ASSERT_EQ(ret, 0); \ + \ + for (fp_reg =3D __reg_start; fp_reg < __reg_end; fp_reg++) { \ + for (offset =3D 1; offset < 4; offset++) { \ + void *load_addr =3D (buf + offset); \ + __type val =3D VAL_ ## __type ; \ + \ + memcpy(load_addr, &val, sizeof(val)); \ + val =3D test_ ## __inst(fp_reg, load_addr, offset, val); \ + EXPECT_TRUE(__type ##_equal(val, VAL_## __type)); \ + } \ + } \ +} +#define TEST_FPU_LOAD(__type, __inst) \ + __TEST_FPU_LOAD(__type, __inst, 0, 32) +#define TEST_FPU_LOAD_COMPRESSED(__type, __inst) \ + __TEST_FPU_LOAD(__type, __inst, 8, 16) + +TEST_FPU_LOAD(float, flw) +TEST_FPU_LOAD(double, fld) +#ifdef __riscv_compressed +TEST_FPU_LOAD_COMPRESSED(double, c_fld) +TEST_FPU_LOAD_COMPRESSED(double, c_fldsp) +#endif + +#define __TEST_FPU_STORE(__type, __inst, __reg_start, __reg_end) \ +TEST(fpu_store_ ## __inst) \ +{ \ + int i, ret, offset, fp_reg; \ + uint8_t buf[16] __attribute__((aligned(16))); \ + \ + ret =3D prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT); \ + ASSERT_EQ(ret, 0); \ + \ + for (fp_reg =3D __reg_start; fp_reg < __reg_end; fp_reg++) { \ + for (offset =3D 1; offset < 4; offset++) { \ + \ + void *store_addr =3D (buf + offset); \ + __type val =3D VAL_ ## __type ; \ + \ + test_ ## __inst(fp_reg, store_addr, offset, val); \ + memcpy(&val, store_addr, sizeof(val)); \ + EXPECT_TRUE(__type ## _equal(val, VAL_## __type)); \ + } \ + } \ +} +#define TEST_FPU_STORE(__type, __inst) \ + __TEST_FPU_STORE(__type, __inst, 0, 32) +#define TEST_FPU_STORE_COMPRESSED(__type, __inst) \ + __TEST_FPU_STORE(__type, __inst, 8, 16) + +TEST_FPU_STORE(float, fsw) +TEST_FPU_STORE(double, fsd) +#ifdef __riscv_compressed +TEST_FPU_STORE_COMPRESSED(double, c_fsd) +TEST_FPU_STORE_COMPRESSED(double, c_fsdsp) +#endif + +TEST_SIGNAL(gen_sigbus, SIGBUS) +{ + uint32_t *ptr; + uint8_t buf[16] __attribute__((aligned(16))); + int ret; + + ret =3D prctl(PR_SET_UNALIGN, PR_UNALIGN_SIGBUS); + ASSERT_EQ(ret, 0); + + ptr =3D (uint32_t *)(buf + 1); + *ptr =3D 0xDEADBEEFULL; +} + +int main(int argc, char **argv) +{ + int ret, val; + + ret =3D prctl(PR_GET_UNALIGN, &val); + if (ret =3D=3D -1 && errno =3D=3D EINVAL) + ksft_exit_skip("SKIP GET_UNALIGN_CTL not supported\n"); + + exit(test_harness_run(argc, argv)); +} --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9ECD62040B3 for ; Mon, 17 Mar 2025 17:08:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231308; cv=none; b=U1F7KoCrvD/0MK/Rdf2PCuAXIeqQReR12GbDPLBrSHigy+M4f3INqeY6rRVcFJ+MZpdz8JbTZm3Rs6crbgiau56oFcvPjkVS8qfPer69h9UFPCd8CpozkOBkQCB8n7ZaUrrV//zONdzEh5N2TI6wcKM3R37FP3X3yCh6CRiSSCI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231308; c=relaxed/simple; bh=Gv1UmUfkNzV+unmWCBGWmF8ZtodrzRVBnrtgrN2t0IA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o3FlXoQznOlSb8HXOMGhIqOy++xnk1mIDdulkT5yH8NQ8VGyn4QxyMmFxpsegSaDWT/o+uSGv05Q3F54nQX/uYg1nfVDwHzPWxO/XXemQr1N0jCvoVBYSRQHwf00VzTOD3IsmbvI6XEopxUTwcodlJZ12PrX4WdGCICcMFQRnc8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=fVAu8bpc; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="fVAu8bpc" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-43d2d952eb1so12126755e9.1 for ; Mon, 17 Mar 2025 10:08:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231304; x=1742836104; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AdADaa+vHUZsa5aS61sZ5FN/C9kboqasJ4Wux/Gk/Z4=; b=fVAu8bpcPvNBBp2G2pEgWrL0RqlJR7LCWRfwQ+ACsiiXzdoomn34nf0poKGf9ZypBD Kn3EbEwEQRsHaSEYqijzRpRv5HXWiEHZkZFr6l5/D39LpkSJe0ywxBh4LVQ293R/vMR6 uDwFj3oqkS2Jo2mG1qppZMvZs20b2FOhwagv4MB16uR2IFOLLHULWvwJnsUTaXR6aLt+ 6CPDI4WT4XWXnWGDcjf7NnzbzLuQsW36LG4ELxA2UgAKfiz7GTiP4VmKOC0j0Aonm/01 iNDk8Q4SbPos8eMdWk5cU0KZHoylcUU5OunbvyJ+602spJIpGsgGFMwaMNnWyAR6pdBl dh8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231304; x=1742836104; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AdADaa+vHUZsa5aS61sZ5FN/C9kboqasJ4Wux/Gk/Z4=; b=f1q++RcbbN1XjdFOCipsdjK7WCk+za6pjNj5EjCsVPVkG87NzNfR9I6qzQd8w2GSv3 qtA0NZnrOlGQkiIFUiUmIZy1yjxpyRB0jZIJI5VAq0U5AMbRf1cb7+5OgmTD5qsxHUcf VVHG300LbrxxZGgTjiJTou8hokLqbs7Dm/ltF/HVvXuhg7WigSzPB1g7dGv4xJL8rcTN 5CaodJghbOdSmii3nUjDG/8bEfkMJu4+V2cPjo0XQYT8zI0F/kaqkwo7cRQ+Iaoj6Y+a PnJ7n2Jgy5OUk+WpO5NByHVaToQv9Abvje9TXEWjdA0x/MtN8F5HIkerVsl1I/FqdnSR +CeQ== X-Forwarded-Encrypted: i=1; AJvYcCUD2wvKv5O4YNZ88mqGmJu1amXxbG2bcjAsUcrnRUpnGb3gLjdUS7ud1g9TOuKR5H9qXEjYRY7fBGH5zwM=@vger.kernel.org X-Gm-Message-State: AOJu0YwNxNGU0M/rrPuGGPgCiQpS4lJgMjiTAkQoZRiBbocud25zlO1f pYrH07mGxSWX2XPIPU6PEECK7lIIzw+QrABx26WlVtfc2QJs2MAqGArfpHdShio= X-Gm-Gg: ASbGncsE6bUtE7gUaezLP+n2yTpJ3tX1DJ8w1lWDO+hlnQUBeZVUT3FyfZKhxgxr8b6 OEti14dk+46Waq4b+gqG0Ku1jWi+CC4L3RyzP8e0U4AZUzU0TgIya4u7a9tGegB81A5QsM/I2VK qF0RQBrtQLga8Qt64p4+RLzkEd3np/OE4Mx/WIyfZ1a2uApwXeY2iyhCdc7fXxCjbaXK1PZHNoQ 3WT07BMiCPhYwieR/EIhycvjmmFuG2H595wAf6ZLfGDClQSnCKzUdb5XSJ9ddI/UtMOWD3NLyiV 6InIt1rZYDzBsh1/32ikJZHqoeIYuexggoTiIT+qXpbnxw== X-Google-Smtp-Source: AGHT+IGGvUDucTyZhua2TIOWY68n/psfaPPQ4wKaNSWwyNxLgrTgzrMr5DXu7tUeZ+5c3PBxx/axlQ== X-Received: by 2002:a05:600c:450c:b0:43d:609:b305 with SMTP id 5b1f17b1804b1-43d389790acmr6282865e9.17.1742231304068; Mon, 17 Mar 2025 10:08:24 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:23 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 15/18] RISC-V: KVM: add SBI extension init()/deinit() functions Date: Mon, 17 Mar 2025 18:06:21 +0100 Message-ID: <20250317170625.1142870-16-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The FWFT SBI extension will need to dynamically allocate memory and do init time specific initialization. Add an init/deinit callbacks that allows to do so. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 9 +++++++++ arch/riscv/kvm/vcpu.c | 2 ++ arch/riscv/kvm/vcpu_sbi.c | 26 ++++++++++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index 4ed6203cdd30..bcb90757b149 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -49,6 +49,14 @@ struct kvm_vcpu_sbi_extension { =20 /* Extension specific probe function */ unsigned long (*probe)(struct kvm_vcpu *vcpu); + + /* + * Init/deinit function called once during VCPU init/destroy. These + * might be use if the SBI extensions need to allocate or do specific + * init time only configuration. + */ + int (*init)(struct kvm_vcpu *vcpu); + void (*deinit)(struct kvm_vcpu *vcpu); }; =20 void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run= ); @@ -69,6 +77,7 @@ const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ex= t( bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx); int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run); void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu); =20 int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, unsigned long re= g_num, unsigned long *reg_val); diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 60d684c76c58..877bcc85c067 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -185,6 +185,8 @@ void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) =20 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) { + kvm_riscv_vcpu_sbi_deinit(vcpu); + /* Cleanup VCPU AIA context */ kvm_riscv_vcpu_aia_deinit(vcpu); =20 diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index d1c83a77735e..3139f171c20f 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -508,5 +508,31 @@ void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu) scontext->ext_status[idx] =3D ext->default_disabled ? KVM_RISCV_SBI_EXT_STATUS_DISABLED : KVM_RISCV_SBI_EXT_STATUS_ENABLED; + + if (ext->init && ext->init(vcpu) !=3D 0) + scontext->ext_status[idx] =3D KVM_RISCV_SBI_EXT_STATUS_UNAVAILABLE; + } +} + +void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_sbi_context *scontext =3D &vcpu->arch.sbi_context; + const struct kvm_riscv_sbi_extension_entry *entry; + const struct kvm_vcpu_sbi_extension *ext; + int idx, i; + + for (i =3D 0; i < ARRAY_SIZE(sbi_ext); i++) { + entry =3D &sbi_ext[i]; + ext =3D entry->ext_ptr; + idx =3D entry->ext_idx; + + if (idx < 0 || idx >=3D ARRAY_SIZE(scontext->ext_status)) + continue; + + if (scontext->ext_status[idx] =3D=3D KVM_RISCV_SBI_EXT_STATUS_UNAVAILABL= E || + !ext->deinit) + continue; + + ext->deinit(vcpu); } } --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94522204879 for ; Mon, 17 Mar 2025 17:08:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231310; cv=none; b=kAaMfRfNh6bB1QCXvkn8PPacBIHbMakNWsoZCRFYb+Ht/Y4Q73FuytrPSp8YNfN3tufz2hDTIcFqJtFmZXTZ1Z1GEjsVMVJW62yKCNSSqztAKW8l4pFv1ffXXAaggoJCCwL4G+Ws9187q1mQ0mYpGKpJ7IRZ1Z+j7WlPdZPoL58= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231310; c=relaxed/simple; bh=A4sN/k9udFYHC8rKOJ7GPL1gc/l4wJ5pXjUE1OCS49A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=phOwFt9E+eb6ESL/e/URDQD5gDK9UxpFSgCE2JqZqXaWTNv45dpsIPQGV1lcBwp5NYT5pALZpx3w+T4qXGa4BJIicL+8AMo7VCV2rAn4BTq2fjbV/Oin7aidJ7VpNjxI9EiUAQ3jNfd3lCNYH0iP138TGgZhUgvqiSzWLdwFpo8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=lDAhLQyY; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="lDAhLQyY" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-43cf05f0c3eso17350225e9.0 for ; Mon, 17 Mar 2025 10:08:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231305; x=1742836105; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nBnjzkDoAHCYES1tTH1RlHgMSmamC+5QlhVYnXgdQEI=; b=lDAhLQyYSYSJcmGW+xNXKfAcqyeKyhel8pIznadDrnGv4Rk+7wz31QHjTiGb577KI+ 0ZwdOzQL7V34YMw8sr6RmrsdNOGf1A6T4OhWr7ywBCHHrT2nvP5F/oLOB5S1X8MHOFe/ VF6owPEEmSlZHYJMcaJR0WwSDnHjpiof3i6KjvmzvqFm0muYRjHWk/t8N603i5Kj/EA2 FJ1IS7I670otwVLyRMsGxRSmo/M68hStnqYd37jjHB9bImrdRB26qSI4INyzTC94a/4/ JMEUDByvF7U8lZVnG1cgYsyWTAkO89Arw5CRc2cvhJ0AUZcEMajormoxTKa2tPJTpFip VViQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231305; x=1742836105; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nBnjzkDoAHCYES1tTH1RlHgMSmamC+5QlhVYnXgdQEI=; b=d3aD04Twy3WTfpKgms8j8pzcb5PHSmzrBVED6M2DVAZ6CmlRwl9bS6iiNa9BLi22SO wk3yhYkeRe+99oO375k6uhRwTorCHzB66IeiYCYRlhtLAICbznkz9z4l3HF1rh8CiDlp XYTqstSfHW372ZxXpL11Kbm/y4Iqo4cZ2FpElbJt07INijyUU41TCa7eNngfs0katvue 6x20yrB5JzbcW7aGPFNwrXXVioJW/oMgwfQYuV75IputN8+buHDylDI1xJBWkREHCBXr vpx9gjL/lqB1jmTMkmoP0J/f1AtwCNBxy+mZLBbIFsv4/H0Ur+SzeVYaleOT3xzfmDFN bm5g== X-Forwarded-Encrypted: i=1; AJvYcCWzQpj8OfVLih5l/AwRIK5MctPOk8XByOl8QoIf9Z3jA0eHwseYv4sfPxt1Ax/bMHh8S3Pw0SMGB6D1JUE=@vger.kernel.org X-Gm-Message-State: AOJu0YznSG5rHrDrBzJ21fejCAxWfXdAaXXqcaMyySzo9HBPFv/NZWZ8 2/P28yc5+SdwquQPWiRY0W/WY9i3r1DHY449jhl+4hDNhCU1dc1lor6AUuRgum0= X-Gm-Gg: ASbGncsUlvG7mMeBNMJRe1ihiBe2xNAH88pK8tW2RJFLC+4tVA87qP3whMMYvNNQmMI 63l7NFXxdWf+a2jvzaGJnUMqMdzrDbQz0mwemC8qoJ7QcfpGAIUJXRP6a1X/BCFs7VVlEm0Fdj1 wrn2+08TIWTCo/1JaFKyFRO0cZ6rwIB08nkDIAoSqkpaiTylR/xe2k6GPmxI4uTvn3A0bfK9rvg G4QqNvDHZrCDPbxzK2NpU0bDokzQ9+TElIbtLJr1Oakex2c1asUQ4MzijhVP09Si6gyijBjj8+y mxBF6Cugb37CmQkaFhZKtQxLhDVBLfwwEEUKSi6IlYGJwSd05Ke5eqdn X-Google-Smtp-Source: AGHT+IEqhdp5dcBzbvbBuH3dLSPFcvLdqKUwlLK3z0GBcZnv77CKTJXWVzz2XGRU3Xp4MOn6/tiCWA== X-Received: by 2002:a05:600c:4ed0:b0:43d:ed:acd5 with SMTP id 5b1f17b1804b1-43d2a2eca5bmr70294645e9.10.1742231305531; Mon, 17 Mar 2025 10:08:25 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:24 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 16/18] RISC-V: KVM: add SBI extension reset callback Date: Mon, 17 Mar 2025 18:06:22 +0100 Message-ID: <20250317170625.1142870-17-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Currently, only the STA extension needed a reset function but that's going to be the case for FWFT as well. Add a reset callback that can be implemented by SBI extensions. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_host.h | 1 - arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 ++ arch/riscv/kvm/vcpu.c | 2 +- arch/riscv/kvm/vcpu_sbi.c | 24 ++++++++++++++++++++++++ arch/riscv/kvm/vcpu_sbi_sta.c | 3 ++- 5 files changed, 29 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index cc33e35cd628..bb93d2995ea2 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -409,7 +409,6 @@ void __kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); bool kvm_riscv_vcpu_stopped(struct kvm_vcpu *vcpu); =20 -void kvm_riscv_vcpu_sbi_sta_reset(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_record_steal_time(struct kvm_vcpu *vcpu); =20 #endif /* __RISCV_KVM_HOST_H__ */ diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index bcb90757b149..cb68b3a57c8f 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -57,6 +57,7 @@ struct kvm_vcpu_sbi_extension { */ int (*init)(struct kvm_vcpu *vcpu); void (*deinit)(struct kvm_vcpu *vcpu); + void (*reset)(struct kvm_vcpu *vcpu); }; =20 void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run= ); @@ -78,6 +79,7 @@ bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, i= nt idx); int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run); void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_sbi_reset(struct kvm_vcpu *vcpu); =20 int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, unsigned long re= g_num, unsigned long *reg_val); diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 877bcc85c067..542747e2c7f5 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -94,7 +94,7 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) vcpu->arch.hfence_tail =3D 0; memset(vcpu->arch.hfence_queue, 0, sizeof(vcpu->arch.hfence_queue)); =20 - kvm_riscv_vcpu_sbi_sta_reset(vcpu); + kvm_riscv_vcpu_sbi_reset(vcpu); =20 /* Reset the guest CSRs for hotplug usecase */ if (loaded) diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 3139f171c20f..50be079b5528 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -536,3 +536,27 @@ void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu) ext->deinit(vcpu); } } + +void kvm_riscv_vcpu_sbi_reset(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_sbi_context *scontext =3D &vcpu->arch.sbi_context; + const struct kvm_riscv_sbi_extension_entry *entry; + const struct kvm_vcpu_sbi_extension *ext; + int idx, i; + + for (i =3D 0; i < ARRAY_SIZE(sbi_ext); i++) { + entry =3D &sbi_ext[i]; + ext =3D entry->ext_ptr; + idx =3D entry->ext_idx; + + if (idx < 0 || idx >=3D ARRAY_SIZE(scontext->ext_status)) + continue; + + if (scontext->ext_status[idx] !=3D KVM_RISCV_SBI_EXT_STATUS_ENABLED || + !ext->reset) + continue; + + ext->reset(vcpu); + } +} + diff --git a/arch/riscv/kvm/vcpu_sbi_sta.c b/arch/riscv/kvm/vcpu_sbi_sta.c index 5f35427114c1..cc6cb7c8f0e4 100644 --- a/arch/riscv/kvm/vcpu_sbi_sta.c +++ b/arch/riscv/kvm/vcpu_sbi_sta.c @@ -16,7 +16,7 @@ #include #include =20 -void kvm_riscv_vcpu_sbi_sta_reset(struct kvm_vcpu *vcpu) +static void kvm_riscv_vcpu_sbi_sta_reset(struct kvm_vcpu *vcpu) { vcpu->arch.sta.shmem =3D INVALID_GPA; vcpu->arch.sta.last_steal =3D 0; @@ -156,6 +156,7 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_sta = =3D { .extid_end =3D SBI_EXT_STA, .handler =3D kvm_sbi_ext_sta_handler, .probe =3D kvm_sbi_ext_sta_probe, + .reset =3D kvm_riscv_vcpu_sbi_sta_reset, }; =20 int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7856F204C25 for ; Mon, 17 Mar 2025 17:08:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231311; cv=none; b=IbFOfJnJxg2uvOZIbjs4wcJzmo7vwluYq4hN/psXjCS1xt4mZ4Uv/xl/9XLwDyavdbD6epGvln7nvuzegE9HtoYtVHWy6i1pU9I2je8COPIsLCTyqNj5/xWo4MghK54/kDV6J28QjxM1OJHeqZTeRH4vQ9K5lKqaeK3K4Pp9R8A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231311; c=relaxed/simple; bh=ETZkdj6KdcMl5e6ZBIgvLRcLQFhiOf/kmFKu+WD3VOo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nw3IVP5aFQsJuh6VJjUdQX+JJsBu3C4NM7OLu1D8gM4JqD7d/jGgJZ5X2p7gXBDBTiwrhBVgPDZxh8YjsLk/M45deSz4lyogam7HkG9+9i5JoU48azFYF+nOukjFHFhp6lT1A82on0zjAgSXEtVeUL7JJn4Uok5T1mQy8QEhDAg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=J1oMxS5A; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="J1oMxS5A" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4394a823036so22834645e9.0 for ; Mon, 17 Mar 2025 10:08:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231307; x=1742836107; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=htANgsmbkNgRMbGQD4e3tcAhU02WYfiaQrP01+RVlsg=; b=J1oMxS5Azoe4h5IP5KvKfM8jUBYcnk5c92RXXQx6F9NRsmawVXda5I8A/KpnASBGh5 1UR8TmaUaNs4ZNgid8+1seKYn1yRmfnD8vUdkFM6VFFjNH279IHeCQwwJBwTkAP9saQC 2cgsAqFnZDFgrIY7RCok45Lit1WAJiirVg4kUt4qn4QGELFLJk+zigoj/RklCPuIkJAb twHUVJ3agRe95c1ju7TAZ7G40ywmGazwpNGtwfu2i3LzlBDZ1OxLrQR/Q0iPFReBIGZP 4bGjMPNuTKk4S71B1QdE0+gMQ1CBGR3ZO5Z/XBx2pdkYeN9vdmF/zqG1H8BvwjX13OMG WATg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231307; x=1742836107; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=htANgsmbkNgRMbGQD4e3tcAhU02WYfiaQrP01+RVlsg=; b=oggx3dgigeFVSZNfXyu2bw5qqOaI5Rc/3kPHxA48LhyG/fkNGKtEJWfAfFP0VifNxw OWtFMbthgv9guYuGct4jdRA7OStRckBp5G1zaBbqir/uVrRYCJiShfLgP77RlIVLCwcz imuR2S5PgHUTUlnFuXPrL+5qoMYmVL437PEheh5jOxuqLVNsmLByuCX//NHQVmnRxPUY PQm1miSXCVT4QLGtp09db58DHnGtCOsNcVdNfd9RUaDP+6skLFWpYvC2k3s06Vcz9MZU AD6MtgoddJ4jCw1yjhdJSZNGjv/nwMGGXwDkyh3NzSw7w1Wp8W6mKgVl6XjOY/mQJhTd TBXw== X-Forwarded-Encrypted: i=1; AJvYcCVX6znvq2Rwmx+ni8/g5nPC55FCJ4NWrL8Ag5OP5Iep6j8D/cAAPWdzIBCDyyk7UoP531t40YEaCduKKw8=@vger.kernel.org X-Gm-Message-State: AOJu0YzYxCj+d4qagpXkdtB7Ymlru9rQ6flowmEhuf+3PCsmOplOsRg3 d3UYHaTmIwYwYwC70sJHyTA71eAxmR9akca/pT5JNAkWCrtK5qJjuTuSqAf7/15hjOmEePjNG3F Zo8U= X-Gm-Gg: ASbGncvMB7YDSVcu5DILUIL7sVN7Au0OAFLxSUPmuh14myzO1mtWWfR88KboZ3h1qYQ JbrskrMsMhyVexRh/ERIbrMDlcWXS1YTzZ0qfCDxjNvGIYfptlQaphQqBUDCWpylWgoUvHveFTS U/qVhY1vTiBYJfRNxnDncWiP4ODdlcaIjlTsqKsQTx4EBBotqRKTGbnAkAaSkh0jtO07hmGkrMY zyKXtPY6BoGH1/IDCYBrwiJ0eD06pGjGalO8/f1PqaUhLK21gI7tsOZ1lkFJYr8ferQi20blZli pxgD9Elf2llQVd6Pog3wAef7yLscvybRXXCs2yAIpDXhZZwsNgt0SC5u X-Google-Smtp-Source: AGHT+IFfYY3GNObYbRkOWr107QkuPT9aClIwdgADGAW00AGW4WvCO631D/hnLE5yPui2XsBly5Wj2g== X-Received: by 2002:a05:6000:4182:b0:390:f6be:af1d with SMTP id ffacd0b85a97d-3996b49903fmr451332f8f.41.1742231306653; Mon, 17 Mar 2025 10:08:26 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:26 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 17/18] RISC-V: KVM: add support for FWFT SBI extension Date: Mon, 17 Mar 2025 18:06:23 +0100 Message-ID: <20250317170625.1142870-18-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add basic infrastructure to support the FWFT extension in KVM. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_host.h | 4 + arch/riscv/include/asm/kvm_vcpu_sbi.h | 1 + arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h | 29 +++ arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu_sbi.c | 4 + arch/riscv/kvm/vcpu_sbi_fwft.c | 216 +++++++++++++++++++++ 7 files changed, 256 insertions(+) create mode 100644 arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h create mode 100644 arch/riscv/kvm/vcpu_sbi_fwft.c diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index bb93d2995ea2..c0db61ba691a 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -19,6 +19,7 @@ #include #include #include +#include #include #include =20 @@ -281,6 +282,9 @@ struct kvm_vcpu_arch { /* Performance monitoring context */ struct kvm_pmu pmu_context; =20 + /* Firmware feature SBI extension context */ + struct kvm_sbi_fwft fwft_context; + /* 'static' configurations which are set only once */ struct kvm_vcpu_config cfg; =20 diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index cb68b3a57c8f..ffd03fed0c06 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -98,6 +98,7 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_h= sm; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_dbcn; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_susp; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_sta; +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor; =20 diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h b/arch/riscv/includ= e/asm/kvm_vcpu_sbi_fwft.h new file mode 100644 index 000000000000..9ba841355758 --- /dev/null +++ b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 Rivos Inc. + * + * Authors: + * Cl=C3=A9ment L=C3=A9ger + */ + +#ifndef __KVM_VCPU_RISCV_FWFT_H +#define __KVM_VCPU_RISCV_FWFT_H + +#include + +struct kvm_sbi_fwft_feature; + +struct kvm_sbi_fwft_config { + const struct kvm_sbi_fwft_feature *feature; + bool supported; + unsigned long flags; +}; + +/* FWFT data structure per vcpu */ +struct kvm_sbi_fwft { + struct kvm_sbi_fwft_config *configs; +}; + +#define vcpu_to_fwft(vcpu) (&(vcpu)->arch.fwft_context) + +#endif /* !__KVM_VCPU_RISCV_FWFT_H */ diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index f06bc5efcd79..fa6eee1caf41 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -202,6 +202,7 @@ enum KVM_RISCV_SBI_EXT_ID { KVM_RISCV_SBI_EXT_DBCN, KVM_RISCV_SBI_EXT_STA, KVM_RISCV_SBI_EXT_SUSP, + KVM_RISCV_SBI_EXT_FWFT, KVM_RISCV_SBI_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 4e0bba91d284..06e2d52a9b88 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -26,6 +26,7 @@ kvm-y +=3D vcpu_onereg.o kvm-$(CONFIG_RISCV_PMU_SBI) +=3D vcpu_pmu.o kvm-y +=3D vcpu_sbi.o kvm-y +=3D vcpu_sbi_base.o +kvm-y +=3D vcpu_sbi_fwft.o kvm-y +=3D vcpu_sbi_hsm.o kvm-$(CONFIG_RISCV_PMU_SBI) +=3D vcpu_sbi_pmu.o kvm-y +=3D vcpu_sbi_replace.o diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 50be079b5528..0748810c0252 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -78,6 +78,10 @@ static const struct kvm_riscv_sbi_extension_entry sbi_ex= t[] =3D { .ext_idx =3D KVM_RISCV_SBI_EXT_STA, .ext_ptr =3D &vcpu_sbi_ext_sta, }, + { + .ext_idx =3D KVM_RISCV_SBI_EXT_FWFT, + .ext_ptr =3D &vcpu_sbi_ext_fwft, + }, { .ext_idx =3D KVM_RISCV_SBI_EXT_EXPERIMENTAL, .ext_ptr =3D &vcpu_sbi_ext_experimental, diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c new file mode 100644 index 000000000000..8a7cfe1fe7a7 --- /dev/null +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Rivos Inc. + * + * Authors: + * Cl=C3=A9ment L=C3=A9ger + */ + +#include +#include +#include +#include +#include +#include +#include + +struct kvm_sbi_fwft_feature { + /** + * @id: Feature ID + */ + enum sbi_fwft_feature_t id; + + /** + * @supported: Check if the feature is supported on the vcpu + * + * This callback is optional, if not provided the feature is assumed to + * be supported + */ + bool (*supported)(struct kvm_vcpu *vcpu); + + /** + * @set: Set the feature value + * + * Return SBI_SUCCESS on success or an SBI error (SBI_ERR_*) + * + * This callback is mandatory + */ + long (*set)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, unsi= gned long value); + + /** + * @get: Get the feature current value + * + * Return SBI_SUCCESS on success or an SBI error (SBI_ERR_*) + * + * This callback is mandatory + */ + long (*get)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, uns= igned long *value); +}; + +static const enum sbi_fwft_feature_t kvm_fwft_defined_features[] =3D { + SBI_FWFT_MISALIGNED_EXC_DELEG, + SBI_FWFT_LANDING_PAD, + SBI_FWFT_SHADOW_STACK, + SBI_FWFT_DOUBLE_TRAP, + SBI_FWFT_PTE_AD_HW_UPDATING, + SBI_FWFT_POINTER_MASKING_PMLEN, +}; + +static bool kvm_fwft_is_defined_feature(enum sbi_fwft_feature_t feature) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(kvm_fwft_defined_features); i++) { + if (kvm_fwft_defined_features[i] =3D=3D feature) + return true; + } + + return false; +} + +static const struct kvm_sbi_fwft_feature features[] =3D { +}; + +static struct kvm_sbi_fwft_config * +kvm_sbi_fwft_get_config(struct kvm_vcpu *vcpu, enum sbi_fwft_feature_t fea= ture) +{ + int i; + struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); + + for (i =3D 0; i < ARRAY_SIZE(features); i++) { + if (fwft->configs[i].feature->id =3D=3D feature) + return &fwft->configs[i]; + } + + return NULL; +} + +static int kvm_fwft_get_feature(struct kvm_vcpu *vcpu, u32 feature, + struct kvm_sbi_fwft_config **conf) +{ + struct kvm_sbi_fwft_config *tconf; + + tconf =3D kvm_sbi_fwft_get_config(vcpu, feature); + if (!tconf) { + if (kvm_fwft_is_defined_feature(feature)) + return SBI_ERR_NOT_SUPPORTED; + + return SBI_ERR_DENIED; + } + + if (!tconf->supported) + return SBI_ERR_NOT_SUPPORTED; + + *conf =3D tconf; + + return SBI_SUCCESS; +} + +static int kvm_sbi_fwft_set(struct kvm_vcpu *vcpu, u32 feature, + unsigned long value, unsigned long flags) +{ + int ret; + struct kvm_sbi_fwft_config *conf; + + ret =3D kvm_fwft_get_feature(vcpu, feature, &conf); + if (ret) + return ret; + + if ((flags & ~SBI_FWFT_SET_FLAG_LOCK) !=3D 0) + return SBI_ERR_INVALID_PARAM; + + if (conf->flags & SBI_FWFT_SET_FLAG_LOCK) + return SBI_ERR_DENIED_LOCKED; + + conf->flags =3D flags; + + return conf->feature->set(vcpu, conf, value); +} + +static int kvm_sbi_fwft_get(struct kvm_vcpu *vcpu, unsigned long feature, + unsigned long *value) +{ + int ret; + struct kvm_sbi_fwft_config *conf; + + ret =3D kvm_fwft_get_feature(vcpu, feature, &conf); + if (ret) + return ret; + + return conf->feature->get(vcpu, conf, value); +} + +static int kvm_sbi_ext_fwft_handler(struct kvm_vcpu *vcpu, struct kvm_run = *run, + struct kvm_vcpu_sbi_return *retdata) +{ + int ret; + struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; + unsigned long funcid =3D cp->a6; + + switch (funcid) { + case SBI_EXT_FWFT_SET: + ret =3D kvm_sbi_fwft_set(vcpu, cp->a0, cp->a1, cp->a2); + break; + case SBI_EXT_FWFT_GET: + ret =3D kvm_sbi_fwft_get(vcpu, cp->a0, &retdata->out_val); + break; + default: + ret =3D SBI_ERR_NOT_SUPPORTED; + break; + } + + retdata->err_val =3D ret; + + return 0; +} + +static int kvm_sbi_ext_fwft_init(struct kvm_vcpu *vcpu) +{ + struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + int i; + + fwft->configs =3D kcalloc(ARRAY_SIZE(features), sizeof(struct kvm_sbi_fwf= t_config), + GFP_KERNEL); + if (!fwft->configs) + return -ENOMEM; + + for (i =3D 0; i < ARRAY_SIZE(features); i++) { + feature =3D &features[i]; + conf =3D &fwft->configs[i]; + if (feature->supported) + conf->supported =3D feature->supported(vcpu); + else + conf->supported =3D true; + + conf->feature =3D feature; + } + + return 0; +} + +static void kvm_sbi_ext_fwft_deinit(struct kvm_vcpu *vcpu) +{ + struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); + + kfree(fwft->configs); +} + +static void kvm_sbi_ext_fwft_reset(struct kvm_vcpu *vcpu) +{ + int i; + struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); + + for (i =3D 0; i < ARRAY_SIZE(features); i++) + fwft->configs[i].flags =3D 0; +} + +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft =3D { + .extid_start =3D SBI_EXT_FWFT, + .extid_end =3D SBI_EXT_FWFT, + .handler =3D kvm_sbi_ext_fwft_handler, + .init =3D kvm_sbi_ext_fwft_init, + .deinit =3D kvm_sbi_ext_fwft_deinit, + .reset =3D kvm_sbi_ext_fwft_reset, +}; --=20 2.47.2 From nobody Wed Dec 17 15:39:17 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DAC6205507 for ; Mon, 17 Mar 2025 17:08:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231313; cv=none; b=RP6yFvn22N2aiUYuDFgozje2Hq3wJwaBUBCZmWMXo5psYicxcQ+4HGHJTzUxW03h5g6ZyTWkmobBYDm9JOhO631NgWWYNSznhnYf0q5nvMQp/Ffr35ZPdj7TF423Wt2kayi8byg4nSzVOqYkr7RKkDluSUboEedZrSfVSSxbiTc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742231313; c=relaxed/simple; bh=4He7dvOKishM2ucXHkTOK3TfNl17p9VqU9eRpxqFxeo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ScrObdiPGPNYDr+vSPKRqrVROpOGH5lKPsAJulO8aqRWD5vVWVJgkpbOwWCdiddiaND7aDnz2qPsz2xt4EmvV4FnJMZ+JkoHc5IyHDujOVqwrISxffAphyP3OSBT97GzRBns1CDPW1RcU45V9xB0Y8kl59qkQe9uewZGwGSlH4w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=xjlWxnSL; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="xjlWxnSL" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4394036c0efso16189095e9.2 for ; Mon, 17 Mar 2025 10:08:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231308; x=1742836108; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P8A8Qnnc9KJsjMpibTJNoHdSMni25LFd1e2ExEX8AcE=; b=xjlWxnSLh6PdUsNvp3BNdORMZz3Az9IpPa3hSuX1GcrPNJJw6fi8wrqWDDvbmuTxQg nfjiRaRmsYBV2SBZSsPMK0Q9G5RFEfE4VimhCdcAAOgt/yPrBpQKiU5FkNj03B7pLgXY ARtTOal2PIyExzpb2OhTVW7rWd98Wm3eO4Lt90+jeH/QJzMDAt9NbwEc/2T9xwkaR08p iwNwAOc7bmHoSpP4Uv8bTcAv0NfxwKg/I7AyEQFPwY8wEU44z6ckvvy9/Fj5hDLl4wue UhaX+fKRQLFF0EZUkxQFpouH9ZXvns8vXhWYLBMd5yr0AdcJ0RvJpIjj4SObCh1zsIG/ uwWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231308; x=1742836108; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P8A8Qnnc9KJsjMpibTJNoHdSMni25LFd1e2ExEX8AcE=; b=JT0uEhNDq7mEpK4XeOEl3OjuteI2phX/VKJhr3/4ysrXh+fi0OOIhgiO5fV/ast0oP BZo5ZO5vzl1lSBLsyAOoHlHliDZ5o4YZE8dTm+Vgybo0pt0nNdINpnM7YBlAEyLcXOfH nGS4eDalPe5flemBn64tLz5lowhiclkCuw08JpHGa8Vy7DSXS87cbkw4qAcW9Q8SSulm tYHLt9P62TT5ZG7Xokw4G4ouScoocXVT9N2OCgq11mobX51vSDXFC8w4epjIbvqmN99X S/8Q1e3nsX6yMLgyHcHKQQvAJ6FpsNdRtHPkE8cpHj/81uxQ+o25nTl9hd1CxfVVCgDR 2k6w== X-Forwarded-Encrypted: i=1; AJvYcCV14veBZbpg4+0MCIAfXedcqxU1g/NelWgng7GYV4ueJrPcl9hMHLmts0k6HlhjwfarvFULWzB4k7QEgBs=@vger.kernel.org X-Gm-Message-State: AOJu0Yzh4gZ3+GB/lAE4iqpU1HLmld/AevyZ3qI3u9MGAqJhnxuEyBcj TcU+ti1J2b4THmj/W9utstc6ByhPYfTGxVFZ2HWQhvFzRZUvH436WWl7jVe0Y1o= X-Gm-Gg: ASbGnctspBYOoOaB0dhahWFYk+vV/isKrCZrOnJFivvAqZR3oZEr4JVvSICNzfLaPH0 GFzlNfexGPL+sUjvFHUCGdFQwy0iosBKxdscXo04tFM2QVKQVxXbHD9A/bXgTDZydNZwLgEQz1j mE8bhFop+4mAplq7Ul2ugBP3BHrX7zM9cFXSyVgnRj7CB6VoC84xLKXQebyrgix/Bgpv7jpZTYI 3LhGMcGdClB6L4+k+BmdTyPyMN8S2/hJ7DSCTXAVhiBz2c9+IyTHT45yaTXtdRP1Zzg/APSunr+ ySfVX2OqbPEEyMigXPnIIgcDZlh/t/L2IBAmZaJzl1BT7w== X-Google-Smtp-Source: AGHT+IGdYqlnvEy/PawZt8Sx5CxSE5paeIGe9C/m17bEJMfGQaAbMdJsnw0bGmy+W1Inh7nCACydaQ== X-Received: by 2002:a05:600c:4f0f:b0:43d:683:8caa with SMTP id 5b1f17b1804b1-43d1ec8632dmr150023255e9.15.1742231308146; Mon, 17 Mar 2025 10:08:28 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:27 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones , Deepak Gupta Subject: [PATCH v4 18/18] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Date: Mon, 17 Mar 2025 18:06:24 +0100 Message-ID: <20250317170625.1142870-19-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable SBI_FWFT_MISALIGNED_DELEG needs hedeleg to be modified to delegate misaligned load/store exceptions. Save and restore it during CPU load/put. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Deepak Gupta Reviewed-by: Andrew Jones --- arch/riscv/kvm/vcpu.c | 3 +++ arch/riscv/kvm/vcpu_sbi_fwft.c | 36 ++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 542747e2c7f5..d98e379945c3 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -646,6 +646,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) { void *nsh; struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; =20 vcpu->cpu =3D -1; =20 @@ -671,6 +672,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) csr->vstval =3D nacl_csr_read(nsh, CSR_VSTVAL); csr->hvip =3D nacl_csr_read(nsh, CSR_HVIP); csr->vsatp =3D nacl_csr_read(nsh, CSR_VSATP); + cfg->hedeleg =3D nacl_csr_read(nsh, CSR_HEDELEG); } else { csr->vsstatus =3D csr_read(CSR_VSSTATUS); csr->vsie =3D csr_read(CSR_VSIE); @@ -681,6 +683,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) csr->vstval =3D csr_read(CSR_VSTVAL); csr->hvip =3D csr_read(CSR_HVIP); csr->vsatp =3D csr_read(CSR_VSATP); + cfg->hedeleg =3D csr_read(CSR_HEDELEG); } } =20 diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 8a7cfe1fe7a7..b0556d66e775 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -14,6 +14,8 @@ #include #include =20 +#define MIS_DELEG (BIT_ULL(EXC_LOAD_MISALIGNED) | BIT_ULL(EXC_STORE_MISALI= GNED)) + struct kvm_sbi_fwft_feature { /** * @id: Feature ID @@ -68,7 +70,41 @@ static bool kvm_fwft_is_defined_feature(enum sbi_fwft_fe= ature_t feature) return false; } =20 +static bool kvm_sbi_fwft_misaligned_delegation_supported(struct kvm_vcpu *= vcpu) +{ + return misaligned_traps_can_delegate(); +} + +static long kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + unsigned long value) +{ + if (value =3D=3D 1) + csr_set(CSR_HEDELEG, MIS_DELEG); + else if (value =3D=3D 0) + csr_clear(CSR_HEDELEG, MIS_DELEG); + else + return SBI_ERR_INVALID_PARAM; + + return SBI_SUCCESS; +} + +static long kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + unsigned long *value) +{ + *value =3D (csr_read(CSR_HEDELEG) & MIS_DELEG) !=3D 0; + + return SBI_SUCCESS; +} + static const struct kvm_sbi_fwft_feature features[] =3D { + { + .id =3D SBI_FWFT_MISALIGNED_EXC_DELEG, + .supported =3D kvm_sbi_fwft_misaligned_delegation_supported, + .set =3D kvm_sbi_fwft_set_misaligned_delegation, + .get =3D kvm_sbi_fwft_get_misaligned_delegation, + }, }; =20 static struct kvm_sbi_fwft_config * --=20 2.47.2