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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 29/29] x86/cacheinfo: Apply maintainer-tip coding style fixes Date: Mon, 17 Mar 2025 17:47:45 +0100 Message-ID: <20250317164745.4754-30-darwi@linutronix.de> In-Reply-To: <20250317164745.4754-1-darwi@linutronix.de> References: <20250317164745.4754-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The x86/cacheinfo code has been heavily refactored and fleshed out at parent commits, where any necessary coding style fixes were also done in place. Apply maintainer-tip.rst coding style fixes to the rest of the code, and align its assignment expressions for readability. At cacheinfo_amd_init_llc_id(), rename variable msb to index_msb as this is how it's called at the rest of cacheinfo.c code. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 211 ++++++++++++++++---------------- 1 file changed, 106 insertions(+), 105 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 397c3dbc5851..ad0d1b0445b0 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Routines to identify caches on Intel CPU. + * x86 CPU caches detection and configuration * - * Changes: - * Venkatesh Pallipadi : Adding cache identification through cpuid(4) - * Ashok Raj : Work with CPU hotplug infrastructure. - * Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD. + * Previous changes + * - Venkatesh Pallipadi: Cache identification through CPUID(4) + * - Ashok Raj : Work with CPU hotplug infrastructure + * - Andi Kleen / Andreas Herrmann: CPUID(4) emulation on AMD */ =20 #include @@ -35,37 +35,37 @@ static cpumask_var_t cpu_cacheinfo_mask; unsigned int memory_caching_control __ro_after_init; =20 enum _cache_type { - CTYPE_NULL =3D 0, - CTYPE_DATA =3D 1, - CTYPE_INST =3D 2, - CTYPE_UNIFIED =3D 3 + CTYPE_NULL =3D 0, + CTYPE_DATA =3D 1, + CTYPE_INST =3D 2, + CTYPE_UNIFIED =3D 3 }; =20 union _cpuid4_leaf_eax { struct { - enum _cache_type type:5; - unsigned int level:3; - unsigned int is_self_initializing:1; - unsigned int is_fully_associative:1; - unsigned int reserved:4; - unsigned int num_threads_sharing:12; - unsigned int num_cores_on_die:6; + enum _cache_type type :5; + unsigned int level :3; + unsigned int is_self_initializing :1; + unsigned int is_fully_associative :1; + unsigned int reserved :4; + unsigned int num_threads_sharing :12; + unsigned int num_cores_on_die :6; } split; u32 full; }; =20 union _cpuid4_leaf_ebx { struct { - unsigned int coherency_line_size:12; - unsigned int physical_line_partition:10; - unsigned int ways_of_associativity:10; + unsigned int coherency_line_size :12; + unsigned int physical_line_partition :10; + unsigned int ways_of_associativity :10; } split; u32 full; }; =20 union _cpuid4_leaf_ecx { struct { - unsigned int number_of_sets:32; + unsigned int number_of_sets :32; } split; u32 full; }; @@ -93,60 +93,59 @@ static const enum cache_type cache_type_map[] =3D { =20 union l1_cache { struct { - unsigned line_size:8; - unsigned lines_per_tag:8; - unsigned assoc:8; - unsigned size_in_kb:8; + unsigned line_size :8; + unsigned lines_per_tag :8; + unsigned assoc :8; + unsigned size_in_kb :8; }; - unsigned val; + unsigned int val; }; =20 union l2_cache { struct { - unsigned line_size:8; - unsigned lines_per_tag:4; - unsigned assoc:4; - unsigned size_in_kb:16; + unsigned line_size :8; + unsigned lines_per_tag :4; + unsigned assoc :4; + unsigned size_in_kb :16; }; - unsigned val; + unsigned int val; }; =20 union l3_cache { struct { - unsigned line_size:8; - unsigned lines_per_tag:4; - unsigned assoc:4; - unsigned res:2; - unsigned size_encoded:14; + unsigned line_size :8; + unsigned lines_per_tag :4; + unsigned assoc :4; + unsigned res :2; + unsigned size_encoded :14; }; - unsigned val; + unsigned int val; }; =20 static const unsigned short assocs[] =3D { - [1] =3D 1, - [2] =3D 2, - [4] =3D 4, - [6] =3D 8, - [8] =3D 16, - [0xa] =3D 32, - [0xb] =3D 48, - [0xc] =3D 64, - [0xd] =3D 96, - [0xe] =3D 128, - [0xf] =3D 0xffff /* fully associative - no way to show this currently */ + [1] =3D 1, + [2] =3D 2, + [4] =3D 4, + [6] =3D 8, + [8] =3D 16, + [0xa] =3D 32, + [0xb] =3D 48, + [0xc] =3D 64, + [0xd] =3D 96, + [0xe] =3D 128, + [0xf] =3D 0xffff /* Fully associative */ }; =20 static const unsigned char levels[] =3D { 1, 1, 2, 3 }; -static const unsigned char types[] =3D { 1, 2, 3, 3 }; +static const unsigned char types[] =3D { 1, 2, 3, 3 }; =20 static void legacy_amd_cpuid4(int index, union _cpuid4_leaf_eax *eax, union _cpuid4_leaf_ebx *ebx, union _cpuid4_leaf_ecx *ecx) { unsigned int dummy, line_size, lines_per_tag, assoc, size_in_kb; - union l1_cache l1i, l1d; + union l1_cache l1i, l1d, *l1; union l2_cache l2; union l3_cache l3; - union l1_cache *l1 =3D &l1d; =20 eax->full =3D 0; ebx->full =3D 0; @@ -155,6 +154,7 @@ static void legacy_amd_cpuid4(int index, union _cpuid4_= leaf_eax *eax, cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val); cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val); =20 + l1 =3D &l1d; switch (index) { case 1: l1 =3D &l1i; @@ -162,48 +162,52 @@ static void legacy_amd_cpuid4(int index, union _cpuid= 4_leaf_eax *eax, case 0: if (!l1->val) return; - assoc =3D assocs[l1->assoc]; - line_size =3D l1->line_size; - lines_per_tag =3D l1->lines_per_tag; - size_in_kb =3D l1->size_in_kb; + + assoc =3D assocs[l1->assoc]; + line_size =3D l1->line_size; + lines_per_tag =3D l1->lines_per_tag; + size_in_kb =3D l1->size_in_kb; break; case 2: if (!l2.val) return; - assoc =3D assocs[l2.assoc]; - line_size =3D l2.line_size; - lines_per_tag =3D l2.lines_per_tag; - /* cpu_data has errata corrections for K7 applied */ - size_in_kb =3D __this_cpu_read(cpu_info.x86_cache_size); + + /* Use x86_cache_size as it might have K7 errata fixes */ + assoc =3D assocs[l2.assoc]; + line_size =3D l2.line_size; + lines_per_tag =3D l2.lines_per_tag; + size_in_kb =3D __this_cpu_read(cpu_info.x86_cache_size); break; case 3: if (!l3.val) return; - assoc =3D assocs[l3.assoc]; - line_size =3D l3.line_size; - lines_per_tag =3D l3.lines_per_tag; - size_in_kb =3D l3.size_encoded * 512; + + assoc =3D assocs[l3.assoc]; + line_size =3D l3.line_size; + lines_per_tag =3D l3.lines_per_tag; + size_in_kb =3D l3.size_encoded * 512; if (boot_cpu_has(X86_FEATURE_AMD_DCM)) { - size_in_kb =3D size_in_kb >> 1; - assoc =3D assoc >> 1; + size_in_kb =3D size_in_kb >> 1; + assoc =3D assoc >> 1; } break; default: return; } =20 - eax->split.is_self_initializing =3D 1; - eax->split.type =3D types[index]; - eax->split.level =3D levels[index]; - eax->split.num_threads_sharing =3D 0; - eax->split.num_cores_on_die =3D topology_num_cores_per_package(); + eax->split.is_self_initializing =3D 1; + eax->split.type =3D types[index]; + eax->split.level =3D levels[index]; + eax->split.num_threads_sharing =3D 0; + eax->split.num_cores_on_die =3D topology_num_cores_per_package(); =20 if (assoc =3D=3D 0xffff) eax->split.is_fully_associative =3D 1; - ebx->split.coherency_line_size =3D line_size - 1; - ebx->split.ways_of_associativity =3D assoc - 1; - ebx->split.physical_line_partition =3D lines_per_tag - 1; - ecx->split.number_of_sets =3D (size_in_kb * 1024) / line_size / + + ebx->split.coherency_line_size =3D line_size - 1; + ebx->split.ways_of_associativity =3D assoc - 1; + ebx->split.physical_line_partition =3D lines_per_tag - 1; + ecx->split.number_of_sets =3D (size_in_kb * 1024) / line_size / (ebx->split.ways_of_associativity + 1) - 1; } =20 @@ -260,18 +264,14 @@ static int fill_cpuid4_info(int index, struct _cpuid4= _info *id4) =20 static int find_num_cache_leaves(struct cpuinfo_x86 *c) { - unsigned int eax, ebx, ecx, edx, op; - union _cpuid4_leaf_eax cache_eax; - int i =3D -1; - - if (x86_vendor_amd_or_hygon(c->x86_vendor)) - op =3D 0x8000001d; - else - op =3D 4; + unsigned int eax, ebx, ecx, edx, op; + union _cpuid4_leaf_eax cache_eax; + int i =3D -1; =20 + /* Do a CPUID(op) loop to calculate num_cache_leaves */ + op =3D x86_vendor_amd_or_hygon(c->x86_vendor) ? 0x8000001d : 4; do { ++i; - /* Do cpuid(op) loop to find out num_cache_leaves */ cpuid_count(op, i, &eax, &ebx, &ecx, &edx); cache_eax.full =3D eax; } while (cache_eax.split.type !=3D CTYPE_NULL); @@ -309,9 +309,9 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u= 16 die_id) num_sharing_cache =3D ((eax >> 14) & 0xfff) + 1; =20 if (num_sharing_cache) { - int bits =3D get_count_order(num_sharing_cache); + int index_msb =3D get_count_order(num_sharing_cache); =20 - c->topo.llc_id =3D c->topo.apicid >> bits; + c->topo.llc_id =3D c->topo.apicid >> index_msb; } } } @@ -332,14 +332,10 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) { struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 - if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { + if (boot_cpu_has(X86_FEATURE_TOPOEXT)) ci->num_leaves =3D find_num_cache_leaves(c); - } else if (c->extended_cpuid_level >=3D 0x80000006) { - if (cpuid_edx(0x80000006) & 0xf000) - ci->num_leaves =3D 4; - else - ci->num_leaves =3D 3; - } + else if (c->extended_cpuid_level >=3D 0x80000006) + ci->num_leaves =3D (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3; } =20 void init_hygon_cacheinfo(struct cpuinfo_x86 *c) @@ -466,6 +462,9 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) intel_cacheinfo_0x2(c); } =20 +/* + * linux/cacheinfo.h shared_cpu_map setup, AMD/Hygon + */ static int __cache_amd_cpumap_setup(unsigned int cpu, int index, const struct _cpuid4_info *id4) { @@ -482,12 +481,12 @@ static int __cache_amd_cpumap_setup(unsigned int cpu,= int index, this_cpu_ci =3D get_cpu_cacheinfo(i); if (!this_cpu_ci->info_list) continue; + ci =3D this_cpu_ci->info_list + index; for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) { if (!cpu_online(sibling)) continue; - cpumask_set_cpu(sibling, - &ci->shared_cpu_map); + cpumask_set_cpu(sibling, &ci->shared_cpu_map); } } } else if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { @@ -513,8 +512,7 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, i= nt index, apicid =3D cpu_data(sibling).topo.apicid; if ((apicid < first) || (apicid > last)) continue; - cpumask_set_cpu(sibling, - &ci->shared_cpu_map); + cpumask_set_cpu(sibling, &ci->shared_cpu_map); } } } else @@ -523,14 +521,17 @@ static int __cache_amd_cpumap_setup(unsigned int cpu,= int index, return 1; } =20 +/* + * linux/cacheinfo.h shared_cpu_map setup, Intel + fallback AMD/Hygon + */ static void __cache_cpumap_setup(unsigned int cpu, int index, const struct _cpuid4_info *id4) { struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); + struct cpuinfo_x86 *c =3D &cpu_data(cpu); struct cacheinfo *ci, *sibling_ci; unsigned long num_threads_sharing; int index_msb, i; - struct cpuinfo_x86 *c =3D &cpu_data(cpu); =20 if (x86_vendor_amd_or_hygon(c->x86_vendor)) { if (__cache_amd_cpumap_setup(cpu, index, id4)) @@ -550,8 +551,10 @@ static void __cache_cpumap_setup(unsigned int cpu, int= index, if (cpu_data(i).topo.apicid >> index_msb =3D=3D c->topo.apicid >> index_= msb) { struct cpu_cacheinfo *sib_cpu_ci =3D get_cpu_cacheinfo(i); =20 + /* Skip if itself or no cacheinfo */ if (i =3D=3D cpu || !sib_cpu_ci->info_list) - continue;/* skip if itself or no cacheinfo */ + continue; + sibling_ci =3D sib_cpu_ci->info_list + index; cpumask_set_cpu(i, &ci->shared_cpu_map); cpumask_set_cpu(cpu, &sibling_ci->shared_cpu_map); @@ -585,7 +588,7 @@ int init_cache_level(unsigned int cpu) } =20 /* - * The max shared threads number comes from CPUID.4:EAX[25-14] with input + * The max shared threads number comes from CPUID(4) EAX[25-14] with input * ECX as cache index. Then right shift apicid by the number's order to get * cache id for this cache node. */ @@ -621,8 +624,8 @@ int populate_cache_leaves(unsigned int cpu) ci_info_init(ci++, &id4, nb); __cache_cpumap_setup(cpu, idx, &id4); } - this_cpu_ci->cpu_map_populated =3D true; =20 + this_cpu_ci->cpu_map_populated =3D true; return 0; } =20 @@ -654,12 +657,10 @@ void cache_disable(void) __acquires(cache_disable_loc= k) unsigned long cr0; =20 /* - * Note that this is not ideal - * since the cache is only flushed/disabled for this CPU while the - * MTRRs are changed, but changing this requires more invasive - * changes to the way the kernel boots + * This is not ideal since the cache is only flushed/disabled + * for this CPU while the MTRRs are changed, but changing this + * requires more invasive changes to the way the kernel boots. */ - raw_spin_lock(&cache_disable_lock); =20 /* Enter the no-fill (CD=3D1, NW=3D0) cache mode and flush caches. */ --=20 2.48.1