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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 23/29] x86/cacheinfo: Separate leaf 0x2 handling and post-processing logic Date: Mon, 17 Mar 2025 17:47:39 +0100 Message-ID: <20250317164745.4754-24-darwi@linutronix.de> In-Reply-To: <20250317164745.4754-1-darwi@linutronix.de> References: <20250317164745.4754-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The logic of init_intel_cacheinfo() is quite convoluted: it mixes leaf 0x4 parsing, leaf 0x2 parsing, plus some post-processing, in a single place. Begin simplifying its logic by extracting the leaf 0x2 parsing code, and the post-processing logic, into their own functions. While at it, rework the SMT LLC topology ID comment for clarity. Suggested-by: Thomas Gleixner Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 106 +++++++++++++++++--------------- 1 file changed, 58 insertions(+), 48 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 0047a41d8d57..9b29842b20db 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -352,14 +352,56 @@ void init_hygon_cacheinfo(struct cpuinfo_x86 *c) ci->num_leaves =3D find_num_cache_leaves(c); } =20 -void init_intel_cacheinfo(struct cpuinfo_x86 *c) +static void intel_cacheinfo_done(struct cpuinfo_x86 *c, unsigned int l3, + unsigned int l2, unsigned int l1i, unsigned int l1d) +{ + /* + * If llc_id is still unset, then cpuid_level < 4, which implies + * that the only possibility left is SMT. Since CPUID(2) doesn't + * specify any shared caches and SMT shares all caches, we can + * unconditionally set LLC ID to the package ID so that all + * threads share it. + */ + if (c->topo.llc_id =3D=3D BAD_APICID) + c->topo.llc_id =3D c->topo.pkg_id; + + c->x86_cache_size =3D l3 ? l3 : (l2 ? l2 : l1i + l1d); + + if (!l2) + cpu_detect_cache_sizes(c); +} + +/* + * Legacy Intel CPUID(2) path if CPUID(4) is not available. + */ +static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) { - /* Cache sizes */ unsigned int l1i =3D 0, l1d =3D 0, l2 =3D 0, l3 =3D 0; - unsigned int new_l1d =3D 0, new_l1i =3D 0; /* Cache sizes from cpuid(4) */ - unsigned int new_l2 =3D 0, new_l3 =3D 0, i; /* Cache sizes from cpuid(4) = */ - unsigned int l2_id =3D 0, l3_id =3D 0, num_threads_sharing, index_msb; + const struct leaf_0x2_table *entry; + union leaf_0x2_regs regs; + u8 *ptr; + + if (c->cpuid_level < 2) + return; + + cpuid_get_leaf_0x2_regs(®s); + for_each_leaf_0x2_entry(regs, ptr, entry) { + switch (entry->c_type) { + case CACHE_L1_INST: l1i +=3D entry->c_size; break; + case CACHE_L1_DATA: l1d +=3D entry->c_size; break; + case CACHE_L2: l2 +=3D entry->c_size; break; + case CACHE_L3: l3 +=3D entry->c_size; break; + } + } + + intel_cacheinfo_done(c, l3, l2, l1i, l1d); +} + +void init_intel_cacheinfo(struct cpuinfo_x86 *c) +{ struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); + unsigned int l1i =3D 0, l1d =3D 0, l2 =3D 0, l3 =3D 0; + unsigned int l2_id =3D 0, l3_id =3D 0; =20 if (c->cpuid_level > 3) { /* @@ -373,7 +415,8 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) * Whenever possible use cpuid(4), deterministic cache * parameters cpuid leaf to find the cache details */ - for (i =3D 0; i < ci->num_leaves; i++) { + for (int i =3D 0; i < ci->num_leaves; i++) { + unsigned int num_threads_sharing, index_msb; struct _cpuid4_info id4 =3D {}; int retval; =20 @@ -384,18 +427,18 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) switch (id4.eax.split.level) { case 1: if (id4.eax.split.type =3D=3D CTYPE_DATA) - new_l1d =3D id4.size/1024; + l1d =3D id4.size / 1024; else if (id4.eax.split.type =3D=3D CTYPE_INST) - new_l1i =3D id4.size/1024; + l1i =3D id4.size / 1024; break; case 2: - new_l2 =3D id4.size/1024; + l2 =3D id4.size / 1024; num_threads_sharing =3D 1 + id4.eax.split.num_threads_sharing; index_msb =3D get_count_order(num_threads_sharing); l2_id =3D c->topo.apicid & ~((1 << index_msb) - 1); break; case 3: - new_l3 =3D id4.size/1024; + l3 =3D id4.size / 1024; num_threads_sharing =3D 1 + id4.eax.split.num_threads_sharing; index_msb =3D get_count_order(num_threads_sharing); l3_id =3D c->topo.apicid & ~((1 << index_msb) - 1); @@ -408,52 +451,19 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) =20 /* Don't use CPUID(2) if CPUID(4) is supported. */ if (!ci->num_leaves && c->cpuid_level > 1) { - const struct leaf_0x2_table *entry; - union leaf_0x2_regs regs; - u8 *ptr; - - cpuid_get_leaf_0x2_regs(®s); - for_each_leaf_0x2_entry(regs, ptr, entry) { - switch (entry->c_type) { - case CACHE_L1_INST: l1i +=3D entry->c_size; break; - case CACHE_L1_DATA: l1d +=3D entry->c_size; break; - case CACHE_L2: l2 +=3D entry->c_size; break; - case CACHE_L3: l3 +=3D entry->c_size; break; - } - } + intel_cacheinfo_0x2(c); + return; } =20 - if (new_l1d) - l1d =3D new_l1d; - - if (new_l1i) - l1i =3D new_l1i; - - if (new_l2) { - l2 =3D new_l2; + if (l2) { c->topo.llc_id =3D l2_id; c->topo.l2c_id =3D l2_id; } =20 - if (new_l3) { - l3 =3D new_l3; + if (l3) c->topo.llc_id =3D l3_id; - } =20 - /* - * If llc_id is not yet set, this means cpuid_level < 4 which in - * turns means that the only possibility is SMT (as indicated in - * cpuid1). Since cpuid2 doesn't specify shared caches, and we know - * that SMT shares all caches, we can unconditionally set cpu_llc_id to - * c->topo.pkg_id. - */ - if (c->topo.llc_id =3D=3D BAD_APICID) - c->topo.llc_id =3D c->topo.pkg_id; - - c->x86_cache_size =3D l3 ? l3 : (l2 ? l2 : (l1i+l1d)); - - if (!l2) - cpu_detect_cache_sizes(c); + intel_cacheinfo_done(c, l3, l2, l1i, l1d); } =20 static int __cache_amd_cpumap_setup(unsigned int cpu, int index, --=20 2.48.1