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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 18/29] x86/cacheinfo: Use enums for cache descriptor types Date: Mon, 17 Mar 2025 17:47:34 +0100 Message-ID: <20250317164745.4754-19-darwi@linutronix.de> In-Reply-To: <20250317164745.4754-1-darwi@linutronix.de> References: <20250317164745.4754-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The leaf 0x2 one-byte cache descriptor types: CACHE_L1_INST CACHE_L1_DATA CACHE_L2 CACHE_L3 are just discriminators to be used within the cache_table[] mapping. Their specific values are irrelevant. Use enums for such types. Make the enum packed and static assert that its values remain within a single byte so that the cache_table[] array size do not go out of hand. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 13 +++++++++++++ arch/x86/kernel/cpu/cacheinfo.c | 9 ++------- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 864047113e37..a66192f9df4c 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -2,6 +2,7 @@ #ifndef _ASM_X86_CPUID_TYPES_H #define _ASM_X86_CPUID_TYPES_H =20 +#include #include =20 /* @@ -42,4 +43,16 @@ union leaf_0x2_regs { u8 desc[16]; }; =20 +/* + * Leaf 0x2 1-byte descriptors' cache types + * To be used for their mappings at cache_table[] + */ +enum _cache_table_type { + CACHE_L1_INST, + CACHE_L1_DATA, + CACHE_L2, + CACHE_L3 +} __packed; +static_assert(sizeof(enum _cache_table_type) =3D=3D 1); + #endif /* _ASM_X86_CPUID_TYPES_H */ diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 777f95c86e03..9f5bf57fd4fc 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -23,11 +23,6 @@ =20 #include "cpu.h" =20 -#define CACHE_L1_INST 1 -#define CACHE_L1_DATA 2 -#define CACHE_L2 3 -#define CACHE_L3 4 - /* Shared last level cache maps */ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); =20 @@ -41,7 +36,7 @@ unsigned int memory_caching_control __ro_after_init; =20 struct _cache_table { unsigned char descriptor; - char cache_type; + enum _cache_table_type type; short size; }; =20 @@ -517,7 +512,7 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) if (!entry) continue; =20 - switch (entry->cache_type) { + switch (entry->type) { case CACHE_L1_INST: l1i +=3D entry->size; break; case CACHE_L1_DATA: l1d +=3D entry->size; break; case CACHE_L2: l2 +=3D entry->size; break; --=20 2.48.1