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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 10/29] x86/cacheinfo: Standardize _cpuid4_info_regs instance naming Date: Mon, 17 Mar 2025 17:47:26 +0100 Message-ID: <20250317164745.4754-11-darwi@linutronix.de> In-Reply-To: <20250317164745.4754-1-darwi@linutronix.de> References: <20250317164745.4754-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cacheinfo code frequently uses the output registers from CPUID leaf 0x4. Such registers are cached at struct _cpuid4_info_regs, augmented with related information, and are then passed across functions. The naming of these _cpuid4_info_regs instances is confusing at best. Some instances are called "this_leaf", which is vague as "this" lacks context and "leaf" is overly generic given that other CPUID leaves are also processed within cacheinfo. Other _cpuid4_info_regs instances are just called "base", adding further ambiguity. Standardize on id4 for all instances. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 97 +++++++++++++++++---------------- 1 file changed, 49 insertions(+), 48 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 3b97e475b09d..06de593e75e1 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -573,7 +573,7 @@ cache_get_priv_group(struct cacheinfo *ci) return &cache_private_group; } =20 -static void amd_init_l3_cache(struct _cpuid4_info_regs *this_leaf, int ind= ex) +static void amd_init_l3_cache(struct _cpuid4_info_regs *id4, int index) { int node; =20 @@ -582,16 +582,16 @@ static void amd_init_l3_cache(struct _cpuid4_info_reg= s *this_leaf, int index) return; =20 node =3D topology_amd_node_id(smp_processor_id()); - this_leaf->nb =3D node_to_amd_nb(node); - if (this_leaf->nb && !this_leaf->nb->l3_cache.indices) - amd_calc_l3_indices(this_leaf->nb); + id4->nb =3D node_to_amd_nb(node); + if (id4->nb && !id4->nb->l3_cache.indices) + amd_calc_l3_indices(id4->nb); } #else #define amd_init_l3_cache(x, y) #endif /* CONFIG_AMD_NB && CONFIG_SYSFS */ =20 static int -cpuid4_cache_lookup_regs(int index, struct _cpuid4_info_regs *this_leaf) +cpuid4_cache_lookup_regs(int index, struct _cpuid4_info_regs *id4) { union _cpuid4_leaf_eax eax; union _cpuid4_leaf_ebx ebx; @@ -604,11 +604,11 @@ cpuid4_cache_lookup_regs(int index, struct _cpuid4_in= fo_regs *this_leaf) &ebx.full, &ecx.full, &edx); else amd_cpuid4(index, &eax, &ebx, &ecx); - amd_init_l3_cache(this_leaf, index); + amd_init_l3_cache(id4, index); } else if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON) { cpuid_count(0x8000001d, index, &eax.full, &ebx.full, &ecx.full, &edx); - amd_init_l3_cache(this_leaf, index); + amd_init_l3_cache(id4, index); } else { cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx); } @@ -616,13 +616,14 @@ cpuid4_cache_lookup_regs(int index, struct _cpuid4_in= fo_regs *this_leaf) if (eax.split.type =3D=3D CTYPE_NULL) return -EIO; /* better error ? */ =20 - this_leaf->eax =3D eax; - this_leaf->ebx =3D ebx; - this_leaf->ecx =3D ecx; - this_leaf->size =3D (ecx.split.number_of_sets + 1) * - (ebx.split.coherency_line_size + 1) * - (ebx.split.physical_line_partition + 1) * - (ebx.split.ways_of_associativity + 1); + id4->eax =3D eax; + id4->ebx =3D ebx; + id4->ecx =3D ecx; + id4->size =3D (ecx.split.number_of_sets + 1) * + (ebx.split.coherency_line_size + 1) * + (ebx.split.physical_line_partition + 1) * + (ebx.split.ways_of_associativity + 1); + return 0; } =20 @@ -753,29 +754,29 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) * parameters cpuid leaf to find the cache details */ for (i =3D 0; i < ci->num_leaves; i++) { - struct _cpuid4_info_regs this_leaf =3D {}; + struct _cpuid4_info_regs id4 =3D {}; int retval; =20 - retval =3D cpuid4_cache_lookup_regs(i, &this_leaf); + retval =3D cpuid4_cache_lookup_regs(i, &id4); if (retval < 0) continue; =20 - switch (this_leaf.eax.split.level) { + switch (id4.eax.split.level) { case 1: - if (this_leaf.eax.split.type =3D=3D CTYPE_DATA) - new_l1d =3D this_leaf.size/1024; - else if (this_leaf.eax.split.type =3D=3D CTYPE_INST) - new_l1i =3D this_leaf.size/1024; + if (id4.eax.split.type =3D=3D CTYPE_DATA) + new_l1d =3D id4.size/1024; + else if (id4.eax.split.type =3D=3D CTYPE_INST) + new_l1i =3D id4.size/1024; break; case 2: - new_l2 =3D this_leaf.size/1024; - num_threads_sharing =3D 1 + this_leaf.eax.split.num_threads_sharing; + new_l2 =3D id4.size/1024; + num_threads_sharing =3D 1 + id4.eax.split.num_threads_sharing; index_msb =3D get_count_order(num_threads_sharing); l2_id =3D c->topo.apicid & ~((1 << index_msb) - 1); break; case 3: - new_l3 =3D this_leaf.size/1024; - num_threads_sharing =3D 1 + this_leaf.eax.split.num_threads_sharing; + new_l3 =3D id4.size/1024; + num_threads_sharing =3D 1 + id4.eax.split.num_threads_sharing; index_msb =3D get_count_order(num_threads_sharing); l3_id =3D c->topo.apicid & ~((1 << index_msb) - 1); break; @@ -840,7 +841,7 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) } =20 static int __cache_amd_cpumap_setup(unsigned int cpu, int index, - const struct _cpuid4_info_regs *base) + const struct _cpuid4_info_regs *id4) { struct cpu_cacheinfo *this_cpu_ci; struct cacheinfo *ci; @@ -866,7 +867,7 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, i= nt index, } else if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { unsigned int apicid, nshared, first, last; =20 - nshared =3D base->eax.split.num_threads_sharing + 1; + nshared =3D id4->eax.split.num_threads_sharing + 1; apicid =3D cpu_data(cpu).topo.apicid; first =3D apicid - (apicid % nshared); last =3D first + nshared - 1; @@ -897,7 +898,7 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, i= nt index, } =20 static void __cache_cpumap_setup(unsigned int cpu, int index, - const struct _cpuid4_info_regs *base) + const struct _cpuid4_info_regs *id4) { struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); struct cacheinfo *ci, *sibling_ci; @@ -906,12 +907,12 @@ static void __cache_cpumap_setup(unsigned int cpu, in= t index, struct cpuinfo_x86 *c =3D &cpu_data(cpu); =20 if (x86_vendor_amd_or_hygon(c->x86_vendor)) { - if (__cache_amd_cpumap_setup(cpu, index, base)) + if (__cache_amd_cpumap_setup(cpu, index, id4)) return; } =20 ci =3D this_cpu_ci->info_list + index; - num_threads_sharing =3D 1 + base->eax.split.num_threads_sharing; + num_threads_sharing =3D 1 + id4->eax.split.num_threads_sharing; =20 cpumask_set_cpu(cpu, &ci->shared_cpu_map); if (num_threads_sharing =3D=3D 1) @@ -932,18 +933,18 @@ static void __cache_cpumap_setup(unsigned int cpu, in= t index, } =20 static void ci_info_init(struct cacheinfo *ci, - const struct _cpuid4_info_regs *base) + const struct _cpuid4_info_regs *id4) { - ci->id =3D base->id; + ci->id =3D id4->id; ci->attributes =3D CACHE_ID; - ci->level =3D base->eax.split.level; - ci->type =3D cache_type_map[base->eax.split.type]; - ci->coherency_line_size =3D base->ebx.split.coherency_line_size + 1; - ci->ways_of_associativity =3D base->ebx.split.ways_of_associativity + 1; - ci->size =3D base->size; - ci->number_of_sets =3D base->ecx.split.number_of_sets + 1; - ci->physical_line_partition =3D base->ebx.split.physical_line_partition += 1; - ci->priv =3D base->nb; + ci->level =3D id4->eax.split.level; + ci->type =3D cache_type_map[id4->eax.split.type]; + ci->coherency_line_size =3D id4->ebx.split.coherency_line_size + 1; + ci->ways_of_associativity =3D id4->ebx.split.ways_of_associativity + 1; + ci->size =3D id4->size; + ci->number_of_sets =3D id4->ecx.split.number_of_sets + 1; + ci->physical_line_partition =3D id4->ebx.split.physical_line_partition + = 1; + ci->priv =3D id4->nb; } =20 int init_cache_level(unsigned int cpu) @@ -962,15 +963,15 @@ int init_cache_level(unsigned int cpu) * ECX as cache index. Then right shift apicid by the number's order to get * cache id for this cache node. */ -static void get_cache_id(int cpu, struct _cpuid4_info_regs *id4_regs) +static void get_cache_id(int cpu, struct _cpuid4_info_regs *id4) { struct cpuinfo_x86 *c =3D &cpu_data(cpu); unsigned long num_threads_sharing; int index_msb; =20 - num_threads_sharing =3D 1 + id4_regs->eax.split.num_threads_sharing; + num_threads_sharing =3D 1 + id4->eax.split.num_threads_sharing; index_msb =3D get_count_order(num_threads_sharing); - id4_regs->id =3D c->topo.apicid >> index_msb; + id4->id =3D c->topo.apicid >> index_msb; } =20 int populate_cache_leaves(unsigned int cpu) @@ -978,15 +979,15 @@ int populate_cache_leaves(unsigned int cpu) unsigned int idx, ret; struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); struct cacheinfo *ci =3D this_cpu_ci->info_list; - struct _cpuid4_info_regs id4_regs =3D {}; + struct _cpuid4_info_regs id4 =3D {}; =20 for (idx =3D 0; idx < this_cpu_ci->num_leaves; idx++) { - ret =3D cpuid4_cache_lookup_regs(idx, &id4_regs); + ret =3D cpuid4_cache_lookup_regs(idx, &id4); if (ret) return ret; - get_cache_id(cpu, &id4_regs); - ci_info_init(ci++, &id4_regs); - __cache_cpumap_setup(cpu, idx, &id4_regs); + get_cache_id(cpu, &id4); + ci_info_init(ci++, &id4); + __cache_cpumap_setup(cpu, idx, &id4); } this_cpu_ci->cpu_map_populated =3D true; =20 --=20 2.48.1