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Also flag the pages that are mapped as response to a page fault as cached. Signed-off-by: Boris Brezillon Signed-off-by: Ariel D'Alessandro Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_mmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panf= rost/panfrost_mmu.c index b91019cd5acb1..9e6f198ef5c1b 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.c +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c @@ -327,7 +327,7 @@ int panfrost_mmu_map(struct panfrost_gem_mapping *mappi= ng) struct drm_gem_object *obj =3D &shmem->base; struct panfrost_device *pfdev =3D to_panfrost_device(obj->dev); struct sg_table *sgt; - int prot =3D IOMMU_READ | IOMMU_WRITE; + int prot =3D IOMMU_READ | IOMMU_WRITE | IOMMU_CACHE; =20 if (WARN_ON(mapping->active)) return 0; @@ -528,7 +528,7 @@ static int panfrost_mmu_map_fault_addr(struct panfrost_= device *pfdev, int as, goto err_map; =20 mmu_map_sg(pfdev, bomapping->mmu, addr, - IOMMU_WRITE | IOMMU_READ | IOMMU_NOEXEC, sgt); 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Mon, 17 Mar 2025 05:42:49 -0700 (PDT) From: Ariel D'Alessandro To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: boris.brezillon@collabora.com, robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, kernel@collabora.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sjoerd@collabora.com, angelogioacchino.delregno@collabora.com, Ariel D'Alessandro Subject: [PATCH v3 2/6] drm/panfrost: Use GPU_MMU_FEATURES_VA_BITS/PA_BITS macros Date: Mon, 17 Mar 2025 09:40:40 -0300 Message-ID: <20250317124044.16257-3-ariel.dalessandro@collabora.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317124044.16257-1-ariel.dalessandro@collabora.com> References: <20250317124044.16257-1-ariel.dalessandro@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Content-Type: text/plain; charset="utf-8" As done in panthor, define and use these GPU_MMU_FEATURES_* macros, which makes code easier to read and reuse. Signed-off-by: Ariel D'Alessandro Reviewed-by: Boris Brezillon Reviewed-by: Steven Price Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/panfrost/panfrost_mmu.c | 6 ++++-- drivers/gpu/drm/panfrost/panfrost_regs.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panf= rost/panfrost_mmu.c index 9e6f198ef5c1b..294f86b3c25e7 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.c +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c @@ -615,6 +615,8 @@ static void panfrost_drm_mm_color_adjust(const struct d= rm_mm_node *node, =20 struct panfrost_mmu *panfrost_mmu_ctx_create(struct panfrost_device *pfdev) { + u32 va_bits =3D GPU_MMU_FEATURES_VA_BITS(pfdev->features.mmu_features); + u32 pa_bits =3D GPU_MMU_FEATURES_PA_BITS(pfdev->features.mmu_features); struct panfrost_mmu *mmu; =20 mmu =3D kzalloc(sizeof(*mmu), GFP_KERNEL); @@ -633,8 +635,8 @@ struct panfrost_mmu *panfrost_mmu_ctx_create(struct pan= frost_device *pfdev) =20 mmu->pgtbl_cfg =3D (struct io_pgtable_cfg) { .pgsize_bitmap =3D SZ_4K | SZ_2M, - .ias =3D FIELD_GET(0xff, pfdev->features.mmu_features), - .oas =3D FIELD_GET(0xff00, pfdev->features.mmu_features), + .ias =3D va_bits, + .oas =3D pa_bits, .coherent_walk =3D pfdev->coherent, .tlb =3D &mmu_tlb_ops, .iommu_dev =3D pfdev->dev, diff --git a/drivers/gpu/drm/panfrost/panfrost_regs.h b/drivers/gpu/drm/pan= frost/panfrost_regs.h index c7bba476ab3f3..b5f279a19a084 100644 --- a/drivers/gpu/drm/panfrost/panfrost_regs.h +++ b/drivers/gpu/drm/panfrost/panfrost_regs.h @@ -16,6 +16,8 @@ #define GROUPS_L2_COHERENT BIT(0) /* Cores groups are l2 coherent */ =20 #define GPU_MMU_FEATURES 0x014 /* (RO) MMU features */ +#define GPU_MMU_FEATURES_VA_BITS(x) ((x) & GENMASK(7, 0)) +#define GPU_MMU_FEATURES_PA_BITS(x) (((x) >> 8) & GENMASK(7, 0)) #define GPU_AS_PRESENT 0x018 /* (RO) Address space slots present */ #define GPU_JS_PRESENT 0x01C /* (RO) Job slots present */ =20 --=20 2.47.2 From nobody Wed Dec 17 13:55:41 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8DFA239082 for ; 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charset="utf-8" Set this feature flag on all Mali Bifrost platforms as the MMU supports AARCH64 4K page table format. Signed-off-by: Ariel D'Alessandro Reviewed-by: Boris Brezillon Reviewed-by: Steven Price Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/panfrost/panfrost_features.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_features.h b/drivers/gpu/drm= /panfrost/panfrost_features.h index 7ed0cd3ea2d4c..52f9d69f6db9d 100644 --- a/drivers/gpu/drm/panfrost/panfrost_features.h +++ b/drivers/gpu/drm/panfrost/panfrost_features.h @@ -54,6 +54,7 @@ enum panfrost_hw_feature { BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \ BIT_ULL(HW_FEATURE_FLUSH_REDUCTION) | \ BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \ + BIT_ULL(HW_FEATURE_AARCH64_MMU) | \ BIT_ULL(HW_FEATURE_COHERENCY_REG)) =20 #define hw_features_g72 (\ @@ -64,6 +65,7 @@ enum panfrost_hw_feature { BIT_ULL(HW_FEATURE_FLUSH_REDUCTION) | \ BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \ BIT_ULL(HW_FEATURE_PROTECTED_DEBUG_MODE) | \ + BIT_ULL(HW_FEATURE_AARCH64_MMU) | \ BIT_ULL(HW_FEATURE_COHERENCY_REG)) =20 #define hw_features_g51 hw_features_g72 @@ -77,6 +79,7 @@ enum panfrost_hw_feature { BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \ BIT_ULL(HW_FEATURE_PROTECTED_DEBUG_MODE) | \ BIT_ULL(HW_FEATURE_IDVS_GROUP_SIZE) | \ + BIT_ULL(HW_FEATURE_AARCH64_MMU) | \ BIT_ULL(HW_FEATURE_COHERENCY_REG)) =20 #define hw_features_g76 (\ --=20 2.47.2 From nobody Wed Dec 17 13:55:41 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17DE923C8C8 for ; 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charset="utf-8" Currently, Panfrost only supports MMU configuration in "LEGACY" (as Bifrost calls it) mode, a (modified) version of LPAE "Large Physical Address Extension", which in Linux we've called "mali_lpae". This commit adds support for conditionally enabling AARCH64_4K page table format. To achieve that, a "GPU optional quirks" field was added to `struct panfrost_features` with the related flag. Note that, in order to enable AARCH64_4K mode, the GPU variant must have the HW_FEATURE_AARCH64_MMU feature flag present. Signed-off-by: Ariel D'Alessandro Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Boris Brezillon --- drivers/gpu/drm/panfrost/panfrost_device.h | 16 +++ drivers/gpu/drm/panfrost/panfrost_mmu.c | 139 +++++++++++++++++++-- drivers/gpu/drm/panfrost/panfrost_regs.h | 34 +++++ 3 files changed, 182 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/p= anfrost/panfrost_device.h index cffcb0ac7c111..ad95f2ed31d9a 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -42,6 +42,14 @@ enum panfrost_gpu_pm { GPU_PM_VREG_OFF, }; =20 +/** + * enum panfrost_gpu_quirks - GPU optional quirks + * @GPU_QUIRK_FORCE_AARCH64_PGTABLE: Use AARCH64_4K page table format + */ +enum panfrost_gpu_quirks { + GPU_QUIRK_FORCE_AARCH64_PGTABLE, +}; + struct panfrost_features { u16 id; u16 revision; @@ -95,6 +103,9 @@ struct panfrost_compatible { =20 /* Allowed PM features */ u8 pm_features; + + /* GPU configuration quirks */ + u8 gpu_quirks; }; =20 struct panfrost_device { @@ -162,6 +173,11 @@ struct panfrost_mmu { int as; atomic_t as_count; struct list_head list; + struct { + u64 transtab; + u64 memattr; + u64 transcfg; + } cfg; }; =20 struct panfrost_engine_usage { diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panf= rost/panfrost_mmu.c index 294f86b3c25e7..e85bd482e7c56 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.c +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c @@ -26,6 +26,48 @@ #define mmu_write(dev, reg, data) writel(data, dev->iomem + reg) #define mmu_read(dev, reg) readl(dev->iomem + reg) =20 +static u64 mair_to_memattr(u64 mair, bool coherent) +{ + u64 memattr =3D 0; + u32 i; + + for (i =3D 0; i < 8; i++) { + u8 in_attr =3D mair >> (8 * i), out_attr; + u8 outer =3D in_attr >> 4, inner =3D in_attr & 0xf; + + /* For caching to be enabled, inner and outer caching policy + * have to be both write-back, if one of them is write-through + * or non-cacheable, we just choose non-cacheable. Device + * memory is also translated to non-cacheable. + */ + if (!(outer & 3) || !(outer & 4) || !(inner & 4)) { + out_attr =3D AS_MEMATTR_AARCH64_INNER_OUTER_NC | + AS_MEMATTR_AARCH64_SH_MIDGARD_INNER | + AS_MEMATTR_AARCH64_INNER_ALLOC_EXPL(false, false); + } else { + out_attr =3D AS_MEMATTR_AARCH64_INNER_OUTER_WB | + AS_MEMATTR_AARCH64_INNER_ALLOC_EXPL(inner & 1, inner & 2); + /* Use SH_MIDGARD_INNER mode when device isn't coherent, + * so SH_IS, which is used when IOMMU_CACHE is set, maps + * to Mali's internal-shareable mode. As per the Mali + * Spec, inner and outer-shareable modes aren't allowed + * for WB memory when coherency is disabled. + * Use SH_CPU_INNER mode when coherency is enabled, so + * that SH_IS actually maps to the standard definition of + * inner-shareable. + */ + if (!coherent) + out_attr |=3D AS_MEMATTR_AARCH64_SH_MIDGARD_INNER; + else + out_attr |=3D AS_MEMATTR_AARCH64_SH_CPU_INNER; + } + + memattr |=3D (u64)out_attr << (8 * i); + } + + return memattr; +} + static int wait_ready(struct panfrost_device *pfdev, u32 as_nr) { int ret; @@ -124,9 +166,9 @@ static int mmu_hw_do_operation(struct panfrost_device *= pfdev, static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panf= rost_mmu *mmu) { int as_nr =3D mmu->as; - struct io_pgtable_cfg *cfg =3D &mmu->pgtbl_cfg; - u64 transtab =3D cfg->arm_mali_lpae_cfg.transtab; - u64 memattr =3D cfg->arm_mali_lpae_cfg.memattr; + u64 transtab =3D mmu->cfg.transtab; + u64 memattr =3D mmu->cfg.memattr; + u64 transcfg =3D mmu->cfg.transcfg; =20 mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM); =20 @@ -139,6 +181,9 @@ static void panfrost_mmu_enable(struct panfrost_device = *pfdev, struct panfrost_m mmu_write(pfdev, AS_MEMATTR_LO(as_nr), lower_32_bits(memattr)); mmu_write(pfdev, AS_MEMATTR_HI(as_nr), upper_32_bits(memattr)); =20 + mmu_write(pfdev, AS_TRANSCFG_LO(as_nr), lower_32_bits(transcfg)); + mmu_write(pfdev, AS_TRANSCFG_HI(as_nr), upper_32_bits(transcfg)); + write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE); } =20 @@ -152,9 +197,66 @@ static void panfrost_mmu_disable(struct panfrost_devic= e *pfdev, u32 as_nr) mmu_write(pfdev, AS_MEMATTR_LO(as_nr), 0); mmu_write(pfdev, AS_MEMATTR_HI(as_nr), 0); =20 + mmu_write(pfdev, AS_TRANSCFG_LO(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED); + mmu_write(pfdev, AS_TRANSCFG_HI(as_nr), 0); + write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE); } =20 +static int mmu_cfg_init_mali_lpae(struct panfrost_mmu *mmu) +{ + struct io_pgtable_cfg *pgtbl_cfg =3D &mmu->pgtbl_cfg; + + /* TODO: The following fields are duplicated between the MMU and Page + * Table config structs. Ideally, should be kept in one place. + */ + mmu->cfg.transtab =3D pgtbl_cfg->arm_mali_lpae_cfg.transtab; + mmu->cfg.memattr =3D pgtbl_cfg->arm_mali_lpae_cfg.memattr; + mmu->cfg.transcfg =3D AS_TRANSCFG_ADRMODE_LEGACY; + + return 0; +} + +static int mmu_cfg_init_aarch64_4k(struct panfrost_mmu *mmu) +{ + struct io_pgtable_cfg *pgtbl_cfg =3D &mmu->pgtbl_cfg; + struct panfrost_device *pfdev =3D mmu->pfdev; + + if (drm_WARN_ON(pfdev->ddev, pgtbl_cfg->arm_lpae_s1_cfg.ttbr & + ~AS_TRANSTAB_AARCH64_4K_ADDR_MASK)) + return -EINVAL; + + mmu->cfg.transtab =3D pgtbl_cfg->arm_lpae_s1_cfg.ttbr; + + mmu->cfg.memattr =3D mair_to_memattr(pgtbl_cfg->arm_lpae_s1_cfg.mair, + pgtbl_cfg->coherent_walk); + + mmu->cfg.transcfg =3D AS_TRANSCFG_PTW_MEMATTR_WB | + AS_TRANSCFG_PTW_RA | + AS_TRANSCFG_ADRMODE_AARCH64_4K | + AS_TRANSCFG_INA_BITS(55 - pgtbl_cfg->ias); + if (pgtbl_cfg->coherent_walk) + mmu->cfg.transcfg |=3D AS_TRANSCFG_PTW_SH_OS; + + return 0; +} + +static int panfrost_mmu_cfg_init(struct panfrost_mmu *mmu, + enum io_pgtable_fmt fmt) +{ + struct panfrost_device *pfdev =3D mmu->pfdev; + + switch (fmt) { + case ARM_64_LPAE_S1: + return mmu_cfg_init_aarch64_4k(mmu); + case ARM_MALI_LPAE: + return mmu_cfg_init_mali_lpae(mmu); + default: + /* This should never happen */ + return drm_WARN_ON(pfdev->ddev, -EINVAL); + } +} + u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu= *mmu) { int as; @@ -618,6 +720,19 @@ struct panfrost_mmu *panfrost_mmu_ctx_create(struct pa= nfrost_device *pfdev) u32 va_bits =3D GPU_MMU_FEATURES_VA_BITS(pfdev->features.mmu_features); u32 pa_bits =3D GPU_MMU_FEATURES_PA_BITS(pfdev->features.mmu_features); struct panfrost_mmu *mmu; + enum io_pgtable_fmt fmt; + int ret; + + if (pfdev->comp->gpu_quirks & BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE)) { + if (!panfrost_has_hw_feature(pfdev, HW_FEATURE_AARCH64_MMU)) { + dev_err_once(pfdev->dev, + "AARCH64_4K page table not supported\n"); + return ERR_PTR(-EINVAL); + } + fmt =3D ARM_64_LPAE_S1; + } else { + fmt =3D ARM_MALI_LPAE; + } =20 mmu =3D kzalloc(sizeof(*mmu), GFP_KERNEL); if (!mmu) @@ -642,16 +757,26 @@ struct panfrost_mmu *panfrost_mmu_ctx_create(struct p= anfrost_device *pfdev) .iommu_dev =3D pfdev->dev, }; =20 - mmu->pgtbl_ops =3D alloc_io_pgtable_ops(ARM_MALI_LPAE, &mmu->pgtbl_cfg, - mmu); + mmu->pgtbl_ops =3D alloc_io_pgtable_ops(fmt, &mmu->pgtbl_cfg, mmu); if (!mmu->pgtbl_ops) { - kfree(mmu); - return ERR_PTR(-EINVAL); + ret =3D -EINVAL; + goto err_free_mmu; } =20 + ret =3D panfrost_mmu_cfg_init(mmu, fmt); + if (ret) + goto err_free_io_pgtable; + kref_init(&mmu->refcount); =20 return mmu; + +err_free_io_pgtable: + free_io_pgtable_ops(mmu->pgtbl_ops); + +err_free_mmu: + kfree(mmu); + return ERR_PTR(ret); } =20 static const char *access_type_name(struct panfrost_device *pfdev, diff --git a/drivers/gpu/drm/panfrost/panfrost_regs.h b/drivers/gpu/drm/pan= frost/panfrost_regs.h index b5f279a19a084..2b8f1617b8369 100644 --- a/drivers/gpu/drm/panfrost/panfrost_regs.h +++ b/drivers/gpu/drm/panfrost/panfrost_regs.h @@ -301,6 +301,17 @@ #define AS_TRANSTAB_HI(as) (MMU_AS(as) + 0x04) /* (RW) Translation Table = Base Address for address space n, high word */ #define AS_MEMATTR_LO(as) (MMU_AS(as) + 0x08) /* (RW) Memory attributes f= or address space n, low word. */ #define AS_MEMATTR_HI(as) (MMU_AS(as) + 0x0C) /* (RW) Memory attributes f= or address space n, high word. */ +#define AS_MEMATTR_AARCH64_INNER_ALLOC_IMPL (2 << 2) +#define AS_MEMATTR_AARCH64_INNER_ALLOC_EXPL(w, r) ((3 << 2) | \ + ((w) ? BIT(0) : 0) | \ + ((r) ? BIT(1) : 0)) +#define AS_MEMATTR_AARCH64_SH_MIDGARD_INNER (0 << 4) +#define AS_MEMATTR_AARCH64_SH_CPU_INNER (1 << 4) +#define AS_MEMATTR_AARCH64_SH_CPU_INNER_SHADER_COH (2 << 4) +#define AS_MEMATTR_AARCH64_SHARED (0 << 6) +#define AS_MEMATTR_AARCH64_INNER_OUTER_NC (1 << 6) +#define AS_MEMATTR_AARCH64_INNER_OUTER_WB (2 << 6) +#define AS_MEMATTR_AARCH64_FAULT (3 << 6) #define AS_LOCKADDR_LO(as) (MMU_AS(as) + 0x10) /* (RW) Lock region addres= s for address space n, low word */ #define AS_LOCKADDR_HI(as) (MMU_AS(as) + 0x14) /* (RW) Lock region addres= s for address space n, high word */ #define AS_COMMAND(as) (MMU_AS(as) + 0x18) /* (WO) MMU command register = for address space n */ @@ -311,6 +322,24 @@ /* Additional Bifrost AS registers */ #define AS_TRANSCFG_LO(as) (MMU_AS(as) + 0x30) /* (RW) Translation table = configuration for address space n, low word */ #define AS_TRANSCFG_HI(as) (MMU_AS(as) + 0x34) /* (RW) Translation table = configuration for address space n, high word */ +#define AS_TRANSCFG_ADRMODE_LEGACY (0 << 0) +#define AS_TRANSCFG_ADRMODE_UNMAPPED (1 << 0) +#define AS_TRANSCFG_ADRMODE_IDENTITY (2 << 0) +#define AS_TRANSCFG_ADRMODE_AARCH64_4K (6 << 0) +#define AS_TRANSCFG_ADRMODE_AARCH64_64K (8 << 0) +#define AS_TRANSCFG_INA_BITS(x) ((x) << 6) +#define AS_TRANSCFG_OUTA_BITS(x) ((x) << 14) +#define AS_TRANSCFG_SL_CONCAT BIT(22) +#define AS_TRANSCFG_PTW_MEMATTR_NC (1 << 24) +#define AS_TRANSCFG_PTW_MEMATTR_WB (2 << 24) +#define AS_TRANSCFG_PTW_SH_NS (0 << 28) +#define AS_TRANSCFG_PTW_SH_OS (2 << 28) +#define AS_TRANSCFG_PTW_SH_IS (3 << 28) +#define AS_TRANSCFG_PTW_RA BIT(30) +#define AS_TRANSCFG_DISABLE_HIER_AP BIT(33) +#define AS_TRANSCFG_DISABLE_AF_FAULT BIT(34) +#define AS_TRANSCFG_WXN BIT(35) +#define AS_TRANSCFG_XREADABLE BIT(36) #define AS_FAULTEXTRA_LO(as) (MMU_AS(as) + 0x38) /* (RO) Secondary fault = address for address space n, low word */ #define AS_FAULTEXTRA_HI(as) (MMU_AS(as) + 0x3C) /* (RO) Secondary fault = address for address space n, high word */ =20 @@ -326,6 +355,11 @@ #define AS_TRANSTAB_LPAE_READ_INNER BIT(2) #define AS_TRANSTAB_LPAE_SHARE_OUTER BIT(4) =20 +/* + * Begin AARCH64_4K MMU TRANSTAB register values + */ +#define AS_TRANSTAB_AARCH64_4K_ADDR_MASK 0xfffffffffffffff0 + #define AS_STATUS_AS_ACTIVE 0x01 =20 #define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3 << 8) --=20 2.47.2 From nobody Wed Dec 17 13:55:41 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 123771DF990 for ; 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charset="utf-8" MediaTek MT8188 SoC has an ARM Mali-G57 MC3 GPU (Valhall-JM), which constantly faults with the current panfrost support. For instance, running `glmark2-es2-drm` benchmark test: ``` [ 79.617461] panfrost 13000000.gpu: js fault, js=3D1, status=3DJOB_BUS_FA= ULT, head=3D0xaadc380, tail=3D0xaadc380 [ 80.119811] panfrost 13000000.gpu: gpu sched timeout, js=3D0, config=3D0= x7300, status=3D0x58, head=3D0xaaca180, tail=3D0xaaca180, sched_job=3D00000= 0002fd03ccc [ 80.129083] panfrost 13000000.gpu: Unhandled Page fault in AS0 at VA 0x0= 000000000000000 [ 80.129083] Reason: TODO [ 80.129083] raw fault status: 0x1C2 [ 80.129083] decoded fault status: SLAVE FAULT [ 80.129083] exception type 0xC2: TRANSLATION_FAULT_2 [ 80.129083] access type 0x1: EXECUTE [ 80.129083] source id 0x0 ``` Note that current panfrost mode (Mali LPAE - LEGACY) only allows to specify write-cache or implementation-defined as the caching policy, probably not matching the right configuration. As depicted in the source code: drivers/iommu/io-pgtable-arm.c: ``` * MEMATTR: Mali has no actual notion of a non-cacheable type, so the * best we can do is mimic the out-of-tree driver and hope that the * "implementation-defined caching policy" is good enough... ``` Now that Panfrost supports AARCH64_4K page table format, let's enable it on Mediatek MT8188 and configure the cache/shareability policies properly. Signed-off-by: Ariel D'Alessandro Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Boris Brezillon --- drivers/gpu/drm/panfrost/panfrost_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panf= rost/panfrost_drv.c index 0f3935556ac76..e854f290858f9 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -824,6 +824,7 @@ static const struct panfrost_compatible mediatek_mt8188= _data =3D { .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8183_pm_domains), .pm_domain_names =3D mediatek_mt8183_pm_domains, .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), + .gpu_quirks =3D BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE), }; =20 static const char * const mediatek_mt8192_supplies[] =3D { "mali", NULL }; --=20 2.47.2 From nobody Wed Dec 17 13:55:41 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9000A23BD0B for ; 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charset="utf-8" MediaTek MT8192 SoC has an ARM Mali-G57 MC5 GPU (Valhall-JM). Now that Panfrost supports AARCH64_4K page table format, let's enable it on this SoC. Running glmark2-es2-drm [0] benchmark, reported the same performance score on both modes Mali LPAE (LEGACY) vs. AARCH64_4K, before and after this commit. Tested on a Mediatek (MT8395) Genio 1200 EVK board. [0] https://github.com/glmark2/glmark2 Signed-off-by: Ariel D'Alessandro Reviewed-by: Boris Brezillon Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/panfrost/panfrost_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panf= rost/panfrost_drv.c index e854f290858f9..ef30d314b2281 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -836,6 +836,7 @@ static const struct panfrost_compatible mediatek_mt8192= _data =3D { .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8192_pm_domains), .pm_domain_names =3D mediatek_mt8192_pm_domains, .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), + .gpu_quirks =3D BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE), }; =20 static const struct of_device_id dt_match[] =3D { --=20 2.47.2