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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2025 12:00:19.5619 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d38a87e5-28f6-48c2-bec6-08dd654b4a1f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D5.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8334 Content-Type: text/plain; charset="utf-8" IOMMU driver sends command to IOMMU hardware via command buffer. In cases where IOMMU hardware fails to process commands in command buffer, dumping it is a valuable input to debug the issue. IOMMU hardware processes command buffer entry at offset equals to the head pointer. Dumping just the entry at the head pointer may not always be useful. The current head may not be pointing to the entry of the command buffer which is causing the issue. IOMMU Hardware may have processed the entry and updated the head pointer. So dumping the entire command buffer gives a broad understanding of what hardware was/is doing. The command buffer dump will have all entries from start to end of the command buffer. Along with that, it will have a head and tail command buffer pointer register dump to facilitate where the IOMMU driver and hardware are in the command buffer for injecting and processing the entries respectively. Command buffer is a per IOMMU data structure. So dumping on per IOMMU basis. eg. -> To get command buffer dump for iommu (say, iommu00) #cat /sys/kernel/debug/iommu/amd/iommu00/cmdbuf Signed-off-by: Dheeraj Kumar Srivastava --- drivers/iommu/amd/amd_iommu_types.h | 7 +++++++ drivers/iommu/amd/debugfs.c | 26 ++++++++++++++++++++++++++ drivers/iommu/amd/iommu.c | 7 ------- 3 files changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 23caea22f8dc..022e32f0a877 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -893,6 +893,13 @@ struct dev_table_entry { }; }; =20 +/* + * Structure defining one entry in the command buffer + */ +struct iommu_cmd { + u32 data[4]; +}; + /* * Structure to sture persistent DTE flags from IVHD */ diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index 33ffa1c7a511..d211c1343f93 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -107,6 +107,30 @@ static int iommu_capability_show(struct seq_file *m, v= oid *unused) } DEFINE_SHOW_STORE_ATTRIBUTE(iommu_capability); =20 +static int iommu_cmdbuf_show(struct seq_file *m, void *unused) +{ + struct amd_iommu *iommu =3D m->private; + struct iommu_cmd *cmd; + unsigned long flag; + u32 head, tail; + int i; + + raw_spin_lock_irqsave(&iommu->lock, flag); + head =3D readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); + tail =3D readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); + seq_printf(m, "CMD Buffer Head Offset:%d Tail Offset:%d\n", + (head >> 4) & 0x7fff, (tail >> 4) & 0x7fff); + for (i =3D 0; i < CMD_BUFFER_ENTRIES; i++) { + cmd =3D (struct iommu_cmd *)(iommu->cmd_buf + i * sizeof(*cmd)); + seq_printf(m, "%3d: %08x %08x %08x %08x\n", i, cmd->data[0], + cmd->data[1], cmd->data[2], cmd->data[3]); + } + raw_spin_unlock_irqrestore(&iommu->lock, flag); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(iommu_cmdbuf); + void amd_iommu_debugfs_setup(void) { struct amd_iommu *iommu; @@ -122,5 +146,7 @@ void amd_iommu_debugfs_setup(void) &iommu_mmio_fops); debugfs_create_file("capability", 0644, iommu->debugfs, iommu, &iommu_capability_fops); + debugfs_create_file("cmdbuf", 0444, iommu->debugfs, iommu, + &iommu_cmdbuf_fops); } } diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index cd5116d8c3b2..5c51ffe7c956 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -62,13 +62,6 @@ static const struct iommu_dirty_ops amd_dirty_ops; =20 int amd_iommu_max_glx_val =3D -1; =20 -/* - * general struct to manage commands send to an IOMMU - */ -struct iommu_cmd { - u32 data[4]; -}; - /* * AMD IOMMU allows up to 2^16 different protection domains. This is a bit= map * to know which ones are already in use. --=20 2.25.1