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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2025 11:59:56.3146 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d01c40e-b901-4ca0-7f8f-08dd654b3c44 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D4.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7989 Content-Type: text/plain; charset="utf-8" IOMMU Capability registers defines capabilities of IOMMU and information needed for initialising MMIO registers and device table. This is useful to dump these registers for debugging IOMMU related issues. e.g. -> To get capability registers value at offset 0x10 for iommu (say, iommu00) # echo "0x10" > /sys/kernel/debug/iommu/amd/iommu00/capability # cat /sys/kernel/debug/iommu/amd/iommu00/capability Signed-off-by: Dheeraj Kumar Srivastava --- drivers/iommu/amd/debugfs.c | 49 +++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index c61d52420c5f..33ffa1c7a511 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -18,6 +18,7 @@ static struct dentry *amd_iommu_debugfs; #define OFS_IN_SZ 8 =20 static int mmio_offset =3D -1; +static int cap_offset =3D -1; =20 static ssize_t iommu_mmio_write(struct file *filp, const char __user *ubuf, size_t cnt, loff_t *ppos) @@ -60,6 +61,52 @@ static int iommu_mmio_show(struct seq_file *m, void *unu= sed) } DEFINE_SHOW_STORE_ATTRIBUTE(iommu_mmio); =20 +static ssize_t iommu_capability_write(struct file *filp, const char __user= *ubuf, + size_t cnt, loff_t *ppos) +{ + int ret; + + cap_offset =3D -1; + + if (cnt > OFS_IN_SZ) + return -EINVAL; + + ret =3D kstrtou32_from_user(ubuf, cnt, 0, &cap_offset); + if (ret) + return ret; + + /* Capability register at offset 0x14 is the last IOMMU capability regist= er. */ + if (cap_offset > 0x14) { + cap_offset =3D -1; + return -EINVAL; + } + + return cnt; +} + +static int iommu_capability_show(struct seq_file *m, void *unused) +{ + struct amd_iommu *iommu =3D m->private; + u32 value; + int err; + + if (cap_offset < 0) { + seq_puts(m, "Please provide capability register's offset in the range [0= x00 - 0x14]\n"); + return 0; + } + + err =3D pci_read_config_dword(iommu->dev, iommu->cap_ptr + cap_offset, &v= alue); + if (err) { + seq_printf(m, "Not able to read capability register at 0x%x\n", cap_offs= et); + return 0; + } + + seq_printf(m, "Offset:0x%x Value:0x%08x\n", cap_offset, value); + + return 0; +} +DEFINE_SHOW_STORE_ATTRIBUTE(iommu_capability); + void amd_iommu_debugfs_setup(void) { struct amd_iommu *iommu; @@ -73,5 +120,7 @@ void amd_iommu_debugfs_setup(void) =20 debugfs_create_file("mmio", 0644, iommu->debugfs, iommu, &iommu_mmio_fops); + debugfs_create_file("capability", 0644, iommu->debugfs, iommu, + &iommu_capability_fops); } } --=20 2.25.1