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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1ffb6292sm84692335e9.1.2025.03.16.11.56.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Mar 2025 11:56:44 -0700 (PDT) From: Alexander Sverdlin To: sophgo@lists.linux.dev, soc@lists.linux.dev Cc: Alexander Sverdlin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Catalin Marinas , Will Deacon , Arnd Bergmann , Jisheng Zhang , Haylen Chu , Chao Wei , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files Date: Sun, 16 Mar 2025 19:56:31 +0100 Message-ID: <20250316185640.3750873-2-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> References: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make the peripheral device tree re-usable on ARM64 platform by moving CPU core and interrupt controllers' parts into new cv18xx-cpu.dtsi and cv18xx-intc.dtsi. Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering into "plic" interrupt-controller numbering. Signed-off-by: Alexander Sverdlin --- Changelog: v5: v4: - cleanups dropped - cv18xx-cpu-intc.dtsi instead of cv18xx-cpu.dtsi+cv18xx-intc.dtsi v3: - &cpus node has been moved into cv18xx-cpu.dtsi, &plic and &clint nodes were moved into cv18xx-intc.dtsi to reduce code duplication; v2: - instead of carving out peripherals' part, carve out ARCH-specifics (CPU core, interrupt controllers) and spread them among 3 SoC .dtsi files which included cv18xx.dtsi; - define a label for the "soc" node and use it in the newly introduced DTs; arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 5 + arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 5 + arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +- .../boot/dts/sophgo/cv18xx-cpu-intc.dtsi | 54 +++++++++++ arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 91 +++++-------------- arch/riscv/boot/dts/sophgo/sg2002.dtsi | 5 + 6 files changed, 93 insertions(+), 69 deletions(-) create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu-intc.dtsi diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/= sophgo/cv1800b.dtsi index aa1f5df100f0..e5494f0f1f45 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -3,8 +3,11 @@ * Copyright (C) 2023 Jisheng Zhang */ =20 +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + #include #include "cv18xx.dtsi" +#include "cv18xx-cpu-intc.dtsi" =20 / { compatible =3D "sophgo,cv1800b"; @@ -15,6 +18,8 @@ memory@80000000 { }; =20 soc { + dma-noncoherent; + pinctrl: pinctrl@3001000 { compatible =3D "sophgo,cv1800b-pinctrl"; reg =3D <0x03001000 0x1000>, diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/= sophgo/cv1812h.dtsi index 8a1b95c5116b..96e1a2f14d3e 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi @@ -3,9 +3,12 @@ * Copyright (C) 2023 Inochi Amaoto */ =20 +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + #include #include #include "cv18xx.dtsi" +#include "cv18xx-cpu-intc.dtsi" #include "cv181x.dtsi" =20 / { @@ -17,6 +20,8 @@ memory@80000000 { }; =20 soc { + dma-noncoherent; + pinctrl: pinctrl@3001000 { compatible =3D "sophgo,cv1812h-pinctrl"; reg =3D <0x03001000 0x1000>, diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/s= ophgo/cv181x.dtsi index 5fd14dd1b14f..bbdb30653e9a 100644 --- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi @@ -11,7 +11,7 @@ soc { emmc: mmc@4300000 { compatible =3D "sophgo,cv1800b-dwcmshc"; reg =3D <0x4300000 0x1000>; - interrupts =3D <34 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_AXI4_EMMC>, <&clk CLK_EMMC>; clock-names =3D "core", "bus"; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-cpu-intc.dtsi b/arch/riscv/b= oot/dts/sophgo/cv18xx-cpu-intc.dtsi new file mode 100644 index 000000000000..5e5d163e79d4 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv18xx-cpu-intc.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang + * Copyright (C) 2023 Inochi Amaoto + */ + +/ { + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <25000000>; + + cpu0: cpu@0 { + compatible =3D "thead,c906", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <512>; + d-cache-size =3D <65536>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <32768>; + mmu-type =3D "riscv,sv39"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + }; +}; + +&soc { + interrupt-parent =3D <&plic>; + + plic: interrupt-controller@70000000 { + reg =3D <0x70000000 0x4000000>; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + riscv,ndev =3D <101>; + }; + + clint: timer@74000000 { + reg =3D <0x74000000 0x10000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/s= ophgo/cv18xx.dtsi index c18822ec849f..62c1464a0490 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -12,47 +12,16 @@ / { #address-cells =3D <1>; #size-cells =3D <1>; =20 - cpus: cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - timebase-frequency =3D <25000000>; - - cpu0: cpu@0 { - compatible =3D "thead,c906", "riscv"; - device_type =3D "cpu"; - reg =3D <0>; - d-cache-block-size =3D <64>; - d-cache-sets =3D <512>; - d-cache-size =3D <65536>; - i-cache-block-size =3D <64>; - i-cache-sets =3D <128>; - i-cache-size =3D <32768>; - mmu-type =3D "riscv,sv39"; - riscv,isa =3D "rv64imafdc"; - riscv,isa-base =3D "rv64i"; - riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", - "zifencei", "zihpm"; - - cpu0_intc: interrupt-controller { - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells =3D <1>; - }; - }; - }; - osc: oscillator { compatible =3D "fixed-clock"; clock-output-names =3D "osc_25m"; #clock-cells =3D <0>; }; =20 - soc { + soc: soc { compatible =3D "simple-bus"; - interrupt-parent =3D <&plic>; #address-cells =3D <1>; #size-cells =3D <1>; - dma-noncoherent; ranges; =20 clk: clock-controller@3002000 { @@ -75,7 +44,7 @@ porta: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <60 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -93,7 +62,7 @@ portb: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <61 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -111,7 +80,7 @@ portc: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <62 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -129,7 +98,7 @@ portd: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <63 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -137,7 +106,7 @@ saradc: adc@30f0000 { compatible =3D "sophgo,cv1800b-saradc"; reg =3D <0x030f0000 0x1000>; clocks =3D <&clk CLK_SARADC>; - interrupts =3D <100 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -162,7 +131,7 @@ i2c0: i2c@4000000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; clock-names =3D "ref", "pclk"; - interrupts =3D <49 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -173,7 +142,7 @@ i2c1: i2c@4010000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; clock-names =3D "ref", "pclk"; - interrupts =3D <50 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -184,7 +153,7 @@ i2c2: i2c@4020000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; clock-names =3D "ref", "pclk"; - interrupts =3D <51 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -195,7 +164,7 @@ i2c3: i2c@4030000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; clock-names =3D "ref", "pclk"; - interrupts =3D <52 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -206,14 +175,14 @@ i2c4: i2c@4040000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; clock-names =3D "ref", "pclk"; - interrupts =3D <53 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 uart0: serial@4140000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04140000 0x100>; - interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART0>, <&clk CLK_APB_UART0>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -224,7 +193,7 @@ uart0: serial@4140000 { uart1: serial@4150000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04150000 0x100>; - interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART1>, <&clk CLK_APB_UART1>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -235,7 +204,7 @@ uart1: serial@4150000 { uart2: serial@4160000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04160000 0x100>; - interrupts =3D <46 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART2>, <&clk CLK_APB_UART2>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -246,7 +215,7 @@ uart2: serial@4160000 { uart3: serial@4170000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04170000 0x100>; - interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART3>, <&clk CLK_APB_UART3>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -261,7 +230,7 @@ spi0: spi@4180000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <54 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -272,7 +241,7 @@ spi1: spi@4190000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <55 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -283,7 +252,7 @@ spi2: spi@41a0000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <56 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -294,14 +263,14 @@ spi3: spi@41b0000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <57 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 uart4: serial@41c0000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x041c0000 0x100>; - interrupts =3D <48 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART4>, <&clk CLK_APB_UART4>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -312,7 +281,7 @@ uart4: serial@41c0000 { sdhci0: mmc@4310000 { compatible =3D "sophgo,cv1800b-dwcmshc"; reg =3D <0x4310000 0x1000>; - interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_AXI4_SD0>, <&clk CLK_SD0>; clock-names =3D "core", "bus"; @@ -322,7 +291,7 @@ sdhci0: mmc@4310000 { sdhci1: mmc@4320000 { compatible =3D "sophgo,cv1800b-dwcmshc"; reg =3D <0x4320000 0x1000>; - interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_AXI4_SD1>, <&clk CLK_SD1>; clock-names =3D "core", "bus"; @@ -332,7 +301,7 @@ sdhci1: mmc@4320000 { dmac: dma-controller@4330000 { compatible =3D "snps,axi-dma-1.01a"; reg =3D <0x04330000 0x1000>; - interrupts =3D <29 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>; clock-names =3D "core-clk", "cfgr-clk"; #dma-cells =3D <1>; @@ -344,19 +313,5 @@ dmac: dma-controller@4330000 { snps,data-width =3D <4>; status =3D "disabled"; }; - - plic: interrupt-controller@70000000 { - reg =3D <0x70000000 0x4000000>; - interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <2>; - riscv,ndev =3D <101>; - }; - - clint: timer@74000000 { - reg =3D <0x74000000 0x10000>; - interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; - }; }; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2002.dtsi index 7f79de33163c..a0cb8080dfa5 100644 --- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi @@ -3,9 +3,12 @@ * Copyright (C) 2024 Thomas Bonnefille */ =20 +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + #include #include #include "cv18xx.dtsi" +#include "cv18xx-cpu-intc.dtsi" #include "cv181x.dtsi" =20 / { @@ -17,6 +20,8 @@ memory@80000000 { }; =20 soc { + dma-noncoherent; + pinctrl: pinctrl@3001000 { compatible =3D "sophgo,sg2002-pinctrl"; reg =3D <0x03001000 0x1000>, --=20 2.48.1