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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1ffb6292sm84692335e9.1.2025.03.16.11.56.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Mar 2025 11:56:44 -0700 (PDT) From: Alexander Sverdlin To: sophgo@lists.linux.dev, soc@lists.linux.dev Cc: Alexander Sverdlin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Catalin Marinas , Will Deacon , Arnd Bergmann , Jisheng Zhang , Haylen Chu , Chao Wei , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files Date: Sun, 16 Mar 2025 19:56:31 +0100 Message-ID: <20250316185640.3750873-2-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> References: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make the peripheral device tree re-usable on ARM64 platform by moving CPU core and interrupt controllers' parts into new cv18xx-cpu.dtsi and cv18xx-intc.dtsi. Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering into "plic" interrupt-controller numbering. Signed-off-by: Alexander Sverdlin --- Changelog: v5: v4: - cleanups dropped - cv18xx-cpu-intc.dtsi instead of cv18xx-cpu.dtsi+cv18xx-intc.dtsi v3: - &cpus node has been moved into cv18xx-cpu.dtsi, &plic and &clint nodes were moved into cv18xx-intc.dtsi to reduce code duplication; v2: - instead of carving out peripherals' part, carve out ARCH-specifics (CPU core, interrupt controllers) and spread them among 3 SoC .dtsi files which included cv18xx.dtsi; - define a label for the "soc" node and use it in the newly introduced DTs; arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 5 + arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 5 + arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +- .../boot/dts/sophgo/cv18xx-cpu-intc.dtsi | 54 +++++++++++ arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 91 +++++-------------- arch/riscv/boot/dts/sophgo/sg2002.dtsi | 5 + 6 files changed, 93 insertions(+), 69 deletions(-) create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu-intc.dtsi diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/= sophgo/cv1800b.dtsi index aa1f5df100f0..e5494f0f1f45 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -3,8 +3,11 @@ * Copyright (C) 2023 Jisheng Zhang */ =20 +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + #include #include "cv18xx.dtsi" +#include "cv18xx-cpu-intc.dtsi" =20 / { compatible =3D "sophgo,cv1800b"; @@ -15,6 +18,8 @@ memory@80000000 { }; =20 soc { + dma-noncoherent; + pinctrl: pinctrl@3001000 { compatible =3D "sophgo,cv1800b-pinctrl"; reg =3D <0x03001000 0x1000>, diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/= sophgo/cv1812h.dtsi index 8a1b95c5116b..96e1a2f14d3e 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi @@ -3,9 +3,12 @@ * Copyright (C) 2023 Inochi Amaoto */ =20 +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + #include #include #include "cv18xx.dtsi" +#include "cv18xx-cpu-intc.dtsi" #include "cv181x.dtsi" =20 / { @@ -17,6 +20,8 @@ memory@80000000 { }; =20 soc { + dma-noncoherent; + pinctrl: pinctrl@3001000 { compatible =3D "sophgo,cv1812h-pinctrl"; reg =3D <0x03001000 0x1000>, diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/s= ophgo/cv181x.dtsi index 5fd14dd1b14f..bbdb30653e9a 100644 --- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi @@ -11,7 +11,7 @@ soc { emmc: mmc@4300000 { compatible =3D "sophgo,cv1800b-dwcmshc"; reg =3D <0x4300000 0x1000>; - interrupts =3D <34 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_AXI4_EMMC>, <&clk CLK_EMMC>; clock-names =3D "core", "bus"; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-cpu-intc.dtsi b/arch/riscv/b= oot/dts/sophgo/cv18xx-cpu-intc.dtsi new file mode 100644 index 000000000000..5e5d163e79d4 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv18xx-cpu-intc.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang + * Copyright (C) 2023 Inochi Amaoto + */ + +/ { + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <25000000>; + + cpu0: cpu@0 { + compatible =3D "thead,c906", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <512>; + d-cache-size =3D <65536>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <32768>; + mmu-type =3D "riscv,sv39"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + }; +}; + +&soc { + interrupt-parent =3D <&plic>; + + plic: interrupt-controller@70000000 { + reg =3D <0x70000000 0x4000000>; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + riscv,ndev =3D <101>; + }; + + clint: timer@74000000 { + reg =3D <0x74000000 0x10000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/s= ophgo/cv18xx.dtsi index c18822ec849f..62c1464a0490 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -12,47 +12,16 @@ / { #address-cells =3D <1>; #size-cells =3D <1>; =20 - cpus: cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - timebase-frequency =3D <25000000>; - - cpu0: cpu@0 { - compatible =3D "thead,c906", "riscv"; - device_type =3D "cpu"; - reg =3D <0>; - d-cache-block-size =3D <64>; - d-cache-sets =3D <512>; - d-cache-size =3D <65536>; - i-cache-block-size =3D <64>; - i-cache-sets =3D <128>; - i-cache-size =3D <32768>; - mmu-type =3D "riscv,sv39"; - riscv,isa =3D "rv64imafdc"; - riscv,isa-base =3D "rv64i"; - riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", - "zifencei", "zihpm"; - - cpu0_intc: interrupt-controller { - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells =3D <1>; - }; - }; - }; - osc: oscillator { compatible =3D "fixed-clock"; clock-output-names =3D "osc_25m"; #clock-cells =3D <0>; }; =20 - soc { + soc: soc { compatible =3D "simple-bus"; - interrupt-parent =3D <&plic>; #address-cells =3D <1>; #size-cells =3D <1>; - dma-noncoherent; ranges; =20 clk: clock-controller@3002000 { @@ -75,7 +44,7 @@ porta: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <60 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -93,7 +62,7 @@ portb: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <61 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -111,7 +80,7 @@ portc: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <62 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -129,7 +98,7 @@ portd: gpio-controller@0 { reg =3D <0>; interrupt-controller; #interrupt-cells =3D <2>; - interrupts =3D <63 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; }; }; =20 @@ -137,7 +106,7 @@ saradc: adc@30f0000 { compatible =3D "sophgo,cv1800b-saradc"; reg =3D <0x030f0000 0x1000>; clocks =3D <&clk CLK_SARADC>; - interrupts =3D <100 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -162,7 +131,7 @@ i2c0: i2c@4000000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; clock-names =3D "ref", "pclk"; - interrupts =3D <49 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -173,7 +142,7 @@ i2c1: i2c@4010000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; clock-names =3D "ref", "pclk"; - interrupts =3D <50 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -184,7 +153,7 @@ i2c2: i2c@4020000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; clock-names =3D "ref", "pclk"; - interrupts =3D <51 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -195,7 +164,7 @@ i2c3: i2c@4030000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; clock-names =3D "ref", "pclk"; - interrupts =3D <52 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -206,14 +175,14 @@ i2c4: i2c@4040000 { #size-cells =3D <0>; clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; clock-names =3D "ref", "pclk"; - interrupts =3D <53 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 uart0: serial@4140000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04140000 0x100>; - interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART0>, <&clk CLK_APB_UART0>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -224,7 +193,7 @@ uart0: serial@4140000 { uart1: serial@4150000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04150000 0x100>; - interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART1>, <&clk CLK_APB_UART1>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -235,7 +204,7 @@ uart1: serial@4150000 { uart2: serial@4160000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04160000 0x100>; - interrupts =3D <46 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART2>, <&clk CLK_APB_UART2>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -246,7 +215,7 @@ uart2: serial@4160000 { uart3: serial@4170000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x04170000 0x100>; - interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART3>, <&clk CLK_APB_UART3>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -261,7 +230,7 @@ spi0: spi@4180000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <54 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -272,7 +241,7 @@ spi1: spi@4190000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <55 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -283,7 +252,7 @@ spi2: spi@41a0000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <56 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 @@ -294,14 +263,14 @@ spi3: spi@41b0000 { #size-cells =3D <0>; clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; clock-names =3D "ssi_clk", "pclk"; - interrupts =3D <57 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; status =3D "disabled"; }; =20 uart4: serial@41c0000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x041c0000 0x100>; - interrupts =3D <48 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_UART4>, <&clk CLK_APB_UART4>; clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; @@ -312,7 +281,7 @@ uart4: serial@41c0000 { sdhci0: mmc@4310000 { compatible =3D "sophgo,cv1800b-dwcmshc"; reg =3D <0x4310000 0x1000>; - interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_AXI4_SD0>, <&clk CLK_SD0>; clock-names =3D "core", "bus"; @@ -322,7 +291,7 @@ sdhci0: mmc@4310000 { sdhci1: mmc@4320000 { compatible =3D "sophgo,cv1800b-dwcmshc"; reg =3D <0x4320000 0x1000>; - interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_AXI4_SD1>, <&clk CLK_SD1>; clock-names =3D "core", "bus"; @@ -332,7 +301,7 @@ sdhci1: mmc@4320000 { dmac: dma-controller@4330000 { compatible =3D "snps,axi-dma-1.01a"; reg =3D <0x04330000 0x1000>; - interrupts =3D <29 IRQ_TYPE_LEVEL_HIGH>; + interrupts =3D ; clocks =3D <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>; clock-names =3D "core-clk", "cfgr-clk"; #dma-cells =3D <1>; @@ -344,19 +313,5 @@ dmac: dma-controller@4330000 { snps,data-width =3D <4>; status =3D "disabled"; }; - - plic: interrupt-controller@70000000 { - reg =3D <0x70000000 0x4000000>; - interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <2>; - riscv,ndev =3D <101>; - }; - - clint: timer@74000000 { - reg =3D <0x74000000 0x10000>; - interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; - }; }; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2002.dtsi index 7f79de33163c..a0cb8080dfa5 100644 --- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi @@ -3,9 +3,12 @@ * Copyright (C) 2024 Thomas Bonnefille */ =20 +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + #include #include #include "cv18xx.dtsi" +#include "cv18xx-cpu-intc.dtsi" #include "cv181x.dtsi" =20 / { @@ -17,6 +20,8 @@ memory@80000000 { }; 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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1ffb6292sm84692335e9.1.2025.03.16.11.56.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Mar 2025 11:56:45 -0700 (PDT) From: Alexander Sverdlin To: sophgo@lists.linux.dev, soc@lists.linux.dev Cc: Alexander Sverdlin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Catalin Marinas , Will Deacon , Arnd Bergmann , Jisheng Zhang , Haylen Chu , Chao Wei , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Conor Dooley Subject: [PATCH v5 2/7] dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 Date: Sun, 16 Mar 2025 19:56:32 +0100 Message-ID: <20250316185640.3750873-3-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> References: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move sophgo.yaml from riscv into soc/sophgo so that it can be shared for all SoCs containing ARM cores as well. This already applies to SG2002. Add SG2000 SoC, Milk-V Duo Module 01 and Milk-V Module 01 EVB. Reviewed-by: Chen Wang Acked-by: Conor Dooley Signed-off-by: Alexander Sverdlin --- Changelog: v5: v4: v3: v2: - patch introduced .../devicetree/bindings/{riscv =3D> soc/sophgo}/sophgo.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) rename Documentation/devicetree/bindings/{riscv =3D> soc/sophgo}/sophgo.ya= ml (80%) diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Document= ation/devicetree/bindings/soc/sophgo/sophgo.yaml similarity index 80% rename from Documentation/devicetree/bindings/riscv/sophgo.yaml rename to Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml index a14cb10ff3f0..5d73d0ccc547 100644 --- a/Documentation/devicetree/bindings/riscv/sophgo.yaml +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/riscv/sophgo.yaml# +$id: http://devicetree.org/schemas/soc/sophgo/sophgo.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Sophgo SoC-based boards @@ -26,6 +26,11 @@ properties: - enum: - sophgo,huashan-pi - const: sophgo,cv1812h + - items: + - enum: + - milkv,duo-module-01-evb + - const: milkv,duo-module-01 + - const: sophgo,sg2000 - items: - enum: - sipeed,licheerv-nano-b --=20 2.48.1 From nobody Wed Dec 17 17:25:56 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85D061E1E1B; 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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1ffb6292sm84692335e9.1.2025.03.16.11.56.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Mar 2025 11:56:46 -0700 (PDT) From: Alexander Sverdlin To: sophgo@lists.linux.dev, soc@lists.linux.dev Cc: Alexander Sverdlin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Catalin Marinas , Will Deacon , Arnd Bergmann , Jisheng Zhang , Haylen Chu , Chao Wei , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 3/7] arm64: dts: sophgo: Add initial SG2000 SoC device tree Date: Sun, 16 Mar 2025 19:56:33 +0100 Message-ID: <20250316185640.3750873-4-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> References: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV). Signed-off-by: Alexander Sverdlin --- Changelog: v5: - PSCI node and enable-method v4: v3: v2: - relocated "memory" node according to DT coding style; - moved GIC node into "soc"; - referring "soc" by label; arch/arm64/boot/dts/sophgo/sg2000.dtsi | 81 ++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/s= ophgo/sg2000.dtsi new file mode 100644 index 000000000000..7051007ec7ea --- /dev/null +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr) + +#include +#include +#include + +/ { + compatible =3D "sophgo,sg2000"; + interrupt-parent =3D <&gic>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + reg =3D <0>; + enable-method =3D "psci"; + i-cache-size =3D <32768>; + d-cache-size =3D <32768>; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x20000>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x80000000 0x20000000>; /* 512MiB */ + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D , + ; + }; + + psci { + compatible =3D "arm,psci-0.2", "arm,psci"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + always-on; + clock-frequency =3D <25000000>; + }; +}; + +&soc { + gic: interrupt-controller@1f01000 { + compatible =3D "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells =3D <3>; + reg =3D <0x01f01000 0x1000>, + <0x01f02000 0x2000>; + }; + + pinctrl: pinctrl@3001000 { + compatible =3D "sophgo,sg2000-pinctrl"; + reg =3D <0x03001000 0x1000>, + <0x05027000 0x1000>; + reg-names =3D "sys", "rtc"; + }; +}; + +&clk { + compatible =3D "sophgo,sg2000-clk"; +}; --=20 2.48.1 From nobody Wed Dec 17 17:25:56 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8038C1EEA29; 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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1ffb6292sm84692335e9.1.2025.03.16.11.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Mar 2025 11:56:47 -0700 (PDT) From: Alexander Sverdlin To: sophgo@lists.linux.dev, soc@lists.linux.dev Cc: Alexander Sverdlin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Catalin Marinas , Will Deacon , Arnd Bergmann , Jisheng Zhang , Haylen Chu , Chao Wei , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 4/7] arm64: dts: sophgo: Add Duo Module 01 Date: Sun, 16 Mar 2025 19:56:34 +0100 Message-ID: <20250316185640.3750873-5-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> References: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Duo Module 01 is a compact module with integrated SG2000, WI-FI6/BTDM5.4, and eMMC. Add only support for UART and SDHCI. Signed-off-by: Alexander Sverdlin --- Changelog: v5: v4: v3: v2: - sorted all nodes according to DT coding style; - added "compatible" property; - renamed the new .dtsi not to use underscores; - added status =3D "okay" instead of deleting it; .../sophgo/sg2000-milkv-duo-module-01.dtsi | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.d= tsi diff --git a/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi b/a= rch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi new file mode 100644 index 000000000000..bb52cdad990a --- /dev/null +++ b/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include +#include "sg2000.dtsi" + +/ { + model =3D "Milk-V Duo Module 01"; + compatible =3D "milkv,duo-module-01", "sophgo,sg2000"; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + serial3 =3D &uart3; + serial4 =3D &uart4; + }; +}; + +&osc { + clock-frequency =3D <25000000>; +}; + +&pinctrl { + sdhci0_cfg: sdhci0-cfg { + sdhci0-cd-pins { + pinmux =3D ; + bias-pull-up; + drive-strength-microamp =3D <10800>; + power-source =3D <3300>; + }; + + sdhci0-clk-pins { + pinmux =3D ; + bias-pull-up; + drive-strength-microamp =3D <16100>; + power-source =3D <3300>; + }; + + sdhci0-cmd-pins { + pinmux =3D ; + bias-pull-up; + drive-strength-microamp =3D <10800>; + power-source =3D <3300>; + }; + + sdhci0-data-pins { + pinmux =3D , + , + , + ; + bias-pull-up; + drive-strength-microamp =3D <10800>; + power-source =3D <3300>; + }; + }; + + uart0_cfg: uart0-cfg { + uart0-pins { + pinmux =3D , + ; + bias-pull-up; + drive-strength-microamp =3D <10800>; + power-source =3D <3300>; + }; + }; +}; + +&emmc { + bus-width =3D <4>; + no-1-8-v; + cap-mmc-hw-reset; + no-sd; + no-sdio; + non-removable; + status =3D "okay"; +}; + +/* Wi-Fi */ +&sdhci1 { + bus-width =3D <4>; + cap-sdio-irq; + no-mmc; + no-sd; + non-removable; +}; --=20 2.48.1 From nobody Wed Dec 17 17:25:56 2025 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 533BA1F4170; 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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1ffb6292sm84692335e9.1.2025.03.16.11.56.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Mar 2025 11:56:48 -0700 (PDT) From: Alexander Sverdlin To: sophgo@lists.linux.dev, soc@lists.linux.dev Cc: Alexander Sverdlin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Catalin Marinas , Will Deacon , Arnd Bergmann , Jisheng Zhang , Haylen Chu , Chao Wei , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 5/7] arm64: dts: sophgo: Add Duo Module 01 Evaluation Board Date: Sun, 16 Mar 2025 19:56:35 +0100 Message-ID: <20250316185640.3750873-6-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> References: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Duo Module 01 Evaluation Board contains Sophgo Duo Module 01 SMD SoM, Ethernet+USB switch, microSD slot, etc... Add only support for UART0 (console) and microSD slot. Signed-off-by: Alexander Sverdlin --- Changelog: v5: v4: v3: v2: - sorted all nodes according to DT coding style; - added "compatible" property; - renamed the new .dts not to use underscores; - added status =3D "okay" instead of deleting it; arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/sophgo/Makefile | 2 ++ .../sophgo/sg2000-milkv-duo-module-01-evb.dts | 31 +++++++++++++++++++ 3 files changed, 34 insertions(+) create mode 100644 arch/arm64/boot/dts/sophgo/Makefile create mode 100644 arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-e= vb.dts diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 79b73a21ddc2..3a32b157ac8c 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -28,6 +28,7 @@ subdir-y +=3D realtek subdir-y +=3D renesas subdir-y +=3D rockchip subdir-y +=3D socionext +subdir-y +=3D sophgo subdir-y +=3D sprd subdir-y +=3D st subdir-y +=3D synaptics diff --git a/arch/arm64/boot/dts/sophgo/Makefile b/arch/arm64/boot/dts/soph= go/Makefile new file mode 100644 index 000000000000..94f52cd7d994 --- /dev/null +++ b/arch/arm64/boot/dts/sophgo/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SOPHGO) +=3D sg2000-milkv-duo-module-01-evb.dtb diff --git a/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts = b/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts new file mode 100644 index 000000000000..b1f8a5787861 --- /dev/null +++ b/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; 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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1ffb6292sm84692335e9.1.2025.03.16.11.56.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Mar 2025 11:56:49 -0700 (PDT) From: Alexander Sverdlin To: sophgo@lists.linux.dev, soc@lists.linux.dev Cc: Alexander Sverdlin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Catalin Marinas , Will Deacon , Arnd Bergmann , Jisheng Zhang , Haylen Chu , Chao Wei , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 6/7] arm64: Add SOPHGO SOC family Kconfig support Date: Sun, 16 Mar 2025 19:56:36 +0100 Message-ID: <20250316185640.3750873-7-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> References: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" First user will be Aarch64 core within SG2000 SoC. Reviewed-by: Chen Wang Signed-off-by: Alexander Sverdlin --- Changelog: v5: v4: v3: v2: - shortened the help message (mirrored from RiscV ARCH now); - select ARCH_HAS_RESET_CONTROLLER instead of RESET_CONTROLLER; - moved CLK_SOPHGO_CV1800 selection into defconfig; arch/arm64/Kconfig.platforms | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 8b76821f190f..af74bcc3c861 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -307,6 +307,12 @@ config ARCH_INTEL_SOCFPGA Stratix 10 (ex. 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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1ffb6292sm84692335e9.1.2025.03.16.11.56.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Mar 2025 11:56:50 -0700 (PDT) From: Alexander Sverdlin To: sophgo@lists.linux.dev, soc@lists.linux.dev Cc: Alexander Sverdlin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Catalin Marinas , Will Deacon , Arnd Bergmann , Jisheng Zhang , Haylen Chu , Chao Wei , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski Subject: [PATCH v5 7/7] arm64: defconfig: Enable rudimentary Sophgo SG2000 support Date: Sun, 16 Mar 2025 19:56:37 +0100 Message-ID: <20250316185640.3750873-8-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> References: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable ARCH_SOPHGO, pinctrl (built-in, required to boot), ADC as module. This defconfig is able to boot from SD card on Milk-V Duo Module 01 evalboard. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexander Sverdlin --- Changelog: v5: v4: v3: v2: - moved CLK_SOPHGO_CV1800 from Kconfig.platforms here; arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index bde1287ad9a7..9c01f5333f0f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -66,6 +66,7 @@ CONFIG_ARCH_RENESAS=3Dy CONFIG_ARCH_ROCKCHIP=3Dy CONFIG_ARCH_SEATTLE=3Dy CONFIG_ARCH_INTEL_SOCFPGA=3Dy +CONFIG_ARCH_SOPHGO=3Dy CONFIG_ARCH_STM32=3Dy CONFIG_ARCH_SYNQUACER=3Dy CONFIG_ARCH_TEGRA=3Dy @@ -652,6 +653,7 @@ CONFIG_PINCTRL_SM8450_LPASS_LPI=3Dm CONFIG_PINCTRL_SC8280XP_LPASS_LPI=3Dm CONFIG_PINCTRL_SM8550_LPASS_LPI=3Dm CONFIG_PINCTRL_SM8650_LPASS_LPI=3Dm +CONFIG_PINCTRL_SOPHGO_SG2000=3Dy CONFIG_GPIO_ALTERA=3Dm CONFIG_GPIO_DAVINCI=3Dy CONFIG_GPIO_DWAPB=3Dy @@ -1409,6 +1411,7 @@ CONFIG_QCOM_HFPLL=3Dy CONFIG_CLK_GFM_LPASS_SM8250=3Dm CONFIG_CLK_RCAR_USB2_CLOCK_SEL=3Dy CONFIG_CLK_RENESAS_VBATTB=3Dm +CONFIG_CLK_SOPHGO_CV1800=3Dy CONFIG_HWSPINLOCK=3Dy CONFIG_HWSPINLOCK_QCOM=3Dy CONFIG_TEGRA186_TIMER=3Dy @@ -1528,6 +1531,7 @@ CONFIG_QCOM_SPMI_VADC=3Dm CONFIG_QCOM_SPMI_ADC5=3Dm CONFIG_ROCKCHIP_SARADC=3Dm CONFIG_RZG2L_ADC=3Dm +CONFIG_SOPHGO_CV1800B_ADC=3Dm CONFIG_TI_ADS1015=3Dm CONFIG_TI_AM335X_ADC=3Dm CONFIG_IIO_CROS_EC_SENSORS_CORE=3Dm --=20 2.48.1