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([182.48.208.77]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30153631fa8sm3141753a91.33.2025.03.15.13.40.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Mar 2025 13:40:41 -0700 (PDT) From: Sahil Siddiq X-Google-Original-From: Sahil Siddiq To: jonas@southpole.se, stefan.kristiansson@saunalahti.fi, shorne@gmail.com Cc: linux-openrisc@vger.kernel.org, linux-kernel@vger.kernel.org, Sahil Siddiq Subject: [PATCH v2] openrisc: Add cacheinfo support Date: Sun, 16 Mar 2025 02:09:37 +0530 Message-ID: <20250315203937.77017-1-sahilcdq@proton.me> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add cacheinfo support for OpenRISC. Currently, a few CPU cache attributes pertaining to OpenRISC processors are exposed along with other unrelated CPU attributes in the procfs file system (/proc/cpuinfo). However, a few cache attributes remain unexposed. An attempt is also made to pull these CPU cache attributes without detecting if the relevant cache exists. This patch provides a mechanism that the generic cacheinfo infrastructure can employ to expose these attributes via the sysfs file system. These attributes are exposed in /sys/devices/system/cpu/cpuX/cache/indexN. Cache attributes are pulled only when the cache component is detected. The implementation to pull cache attributes from the processor's registers has been moved from arch/openrisc/kernel/setup.c with a few modifications. The patch also moves cache-related fields out of struct cpuinfo_or1k and into its own struct to keep the implementation straightforward. This reduces duplication of cache-related fields while keeping cpuinfo_or1k extensible in case more cache descriptors are added in the future. This implementation is based on similar work done for MIPS and LoongArch. Signed-off-by: Sahil Siddiq --- Changes from v1 -> v2: - Changed patch prefix from RFC to PATCH. - cacheinfo.c: Print number of sets. Remove integer padding. - dma.c (page_set_nocache): Access cache attributes only if component exists. (arch_sync_dma_for_device): Likewise. - cache.c: Likewise. - init.c: Likewise. arch/openrisc/include/asm/cpuinfo.h | 16 +++-- arch/openrisc/kernel/Makefile | 2 +- arch/openrisc/kernel/cacheinfo.c | 106 ++++++++++++++++++++++++++++ arch/openrisc/kernel/dma.c | 22 +++--- arch/openrisc/kernel/setup.c | 45 ------------ arch/openrisc/mm/cache.c | 11 ++- arch/openrisc/mm/init.c | 8 ++- 7 files changed, 144 insertions(+), 66 deletions(-) create mode 100644 arch/openrisc/kernel/cacheinfo.c diff --git a/arch/openrisc/include/asm/cpuinfo.h b/arch/openrisc/include/as= m/cpuinfo.h index 5e4744153d0e..82f5d4c06314 100644 --- a/arch/openrisc/include/asm/cpuinfo.h +++ b/arch/openrisc/include/asm/cpuinfo.h @@ -15,16 +15,18 @@ #ifndef __ASM_OPENRISC_CPUINFO_H #define __ASM_OPENRISC_CPUINFO_H =20 +struct cache_desc { + u32 size; + u32 sets; + u32 block_size; + u32 ways; +}; + struct cpuinfo_or1k { u32 clock_frequency; =20 - u32 icache_size; - u32 icache_block_size; - u32 icache_ways; - - u32 dcache_size; - u32 dcache_block_size; - u32 dcache_ways; + struct cache_desc icache; + struct cache_desc dcache; =20 u16 coreid; }; diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile index 79129161f3e0..e4c7d9bdd598 100644 --- a/arch/openrisc/kernel/Makefile +++ b/arch/openrisc/kernel/Makefile @@ -7,7 +7,7 @@ extra-y :=3D vmlinux.lds =20 obj-y :=3D head.o setup.o or32_ksyms.o process.o dma.o \ traps.o time.o irq.o entry.o ptrace.o signal.o \ - sys_call_table.o unwinder.o + sys_call_table.o unwinder.o cacheinfo.o =20 obj-$(CONFIG_SMP) +=3D smp.o sync-timer.o obj-$(CONFIG_STACKTRACE) +=3D stacktrace.o diff --git a/arch/openrisc/kernel/cacheinfo.c b/arch/openrisc/kernel/cachei= nfo.c new file mode 100644 index 000000000000..6bb81e246f7e --- /dev/null +++ b/arch/openrisc/kernel/cacheinfo.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * OpenRISC cacheinfo support + * + * Based on work done for MIPS and LoongArch. All original copyrights + * apply as per the original source declaration. + * + * OpenRISC implementation: + * Copyright (C) 2025 Sahil Siddiq + */ + +#include +#include +#include +#include + +static inline void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_ty= pe type, + unsigned int level, struct cache_desc *cache, int cpu) +{ + this_leaf->type =3D type; + this_leaf->level =3D level; + this_leaf->coherency_line_size =3D cache->block_size; + this_leaf->number_of_sets =3D cache->sets; + this_leaf->ways_of_associativity =3D cache->ways; + this_leaf->size =3D cache->size; + cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map); +} + +int init_cache_level(unsigned int cpu) +{ + struct cpuinfo_or1k *cpuinfo =3D &cpuinfo_or1k[smp_processor_id()]; + struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); + int leaves =3D 0, levels =3D 0; + unsigned long upr =3D mfspr(SPR_UPR); + unsigned long iccfgr, dccfgr; + + if (!(upr & SPR_UPR_UP)) { + printk(KERN_INFO + "-- no UPR register... unable to detect configuration\n"); + return -ENOENT; + } + + if (upr & SPR_UPR_DCP) { + dccfgr =3D mfspr(SPR_DCCFGR); + cpuinfo->dcache.ways =3D 1 << (dccfgr & SPR_DCCFGR_NCW); + cpuinfo->dcache.sets =3D 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); + cpuinfo->dcache.block_size =3D 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7); + cpuinfo->dcache.size =3D + cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_= size; + leaves +=3D 1; + printk(KERN_INFO + "-- dcache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n= ", + cpuinfo->dcache.size, cpuinfo->dcache.block_size, + cpuinfo->dcache.sets, + cpuinfo->dcache.ways); + } else + printk(KERN_INFO "-- dcache disabled\n"); + + if (upr & SPR_UPR_ICP) { + iccfgr =3D mfspr(SPR_ICCFGR); + cpuinfo->icache.ways =3D 1 << (iccfgr & SPR_ICCFGR_NCW); + cpuinfo->icache.sets =3D 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); + cpuinfo->icache.block_size =3D 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7); + cpuinfo->icache.size =3D + cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_= size; + leaves +=3D 1; + printk(KERN_INFO + "-- icache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n= ", + cpuinfo->icache.size, cpuinfo->icache.block_size, + cpuinfo->icache.sets, + cpuinfo->icache.ways); + } else + printk(KERN_INFO "-- icache disabled\n"); + + if (!leaves) + return -ENOENT; + + levels =3D 1; + + this_cpu_ci->num_leaves =3D leaves; + this_cpu_ci->num_levels =3D levels; + + return 0; +} + +int populate_cache_leaves(unsigned int cpu) +{ + struct cpuinfo_or1k *cpuinfo =3D &cpuinfo_or1k[smp_processor_id()]; + struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); + struct cacheinfo *this_leaf =3D this_cpu_ci->info_list; + int level =3D 1; + + if (cpuinfo->dcache.ways) { + ci_leaf_init(this_leaf, CACHE_TYPE_DATA, level, &cpuinfo->dcache, cpu); + this_leaf->attributes =3D ((mfspr(SPR_DCCFGR) & SPR_DCCFGR_CWS) >> 8) ? + CACHE_WRITE_BACK : CACHE_WRITE_THROUGH; + this_leaf++; + } + + if (cpuinfo->icache.ways) + ci_leaf_init(this_leaf, CACHE_TYPE_INST, level, &cpuinfo->icache, cpu); + + this_cpu_ci->cpu_map_populated =3D true; + + return 0; +} diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c index b3edbb33b621..ffb161e41e9d 100644 --- a/arch/openrisc/kernel/dma.c +++ b/arch/openrisc/kernel/dma.c @@ -36,8 +36,10 @@ page_set_nocache(pte_t *pte, unsigned long addr, flush_tlb_kernel_range(addr, addr + PAGE_SIZE); =20 /* Flush page out of dcache */ - for (cl =3D __pa(addr); cl < __pa(next); cl +=3D cpuinfo->dcache_block_si= ze) - mtspr(SPR_DCBFR, cl); + if (cpuinfo->dcache.ways) { + for (cl =3D __pa(addr); cl < __pa(next); cl +=3D cpuinfo->dcache.block_s= ize) + mtspr(SPR_DCBFR, cl); + } =20 return 0; } @@ -104,15 +106,19 @@ void arch_sync_dma_for_device(phys_addr_t addr, size_= t size, switch (dir) { case DMA_TO_DEVICE: /* Flush the dcache for the requested range */ - for (cl =3D addr; cl < addr + size; - cl +=3D cpuinfo->dcache_block_size) - mtspr(SPR_DCBFR, cl); + if (cpuinfo->dcache.ways) { + for (cl =3D addr; cl < addr + size; + cl +=3D cpuinfo->dcache.block_size) + mtspr(SPR_DCBFR, cl); + } break; case DMA_FROM_DEVICE: /* Invalidate the dcache for the requested range */ - for (cl =3D addr; cl < addr + size; - cl +=3D cpuinfo->dcache_block_size) - mtspr(SPR_DCBIR, cl); + if (cpuinfo->dcache.ways) { + for (cl =3D addr; cl < addr + size; + cl +=3D cpuinfo->dcache.block_size) + mtspr(SPR_DCBIR, cl); + } break; default: /* diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c index be56eaafc8b9..38172c0989cf 100644 --- a/arch/openrisc/kernel/setup.c +++ b/arch/openrisc/kernel/setup.c @@ -107,27 +107,6 @@ static void print_cpuinfo(void) printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n", version, revision, cpuinfo->clock_frequency / 1000000); =20 - if (!(upr & SPR_UPR_UP)) { - printk(KERN_INFO - "-- no UPR register... unable to detect configuration\n"); - return; - } - - if (upr & SPR_UPR_DCP) - printk(KERN_INFO - "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n", - cpuinfo->dcache_size, cpuinfo->dcache_block_size, - cpuinfo->dcache_ways); - else - printk(KERN_INFO "-- dcache disabled\n"); - if (upr & SPR_UPR_ICP) - printk(KERN_INFO - "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n", - cpuinfo->icache_size, cpuinfo->icache_block_size, - cpuinfo->icache_ways); - else - printk(KERN_INFO "-- icache disabled\n"); - if (upr & SPR_UPR_DMP) printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n", 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2), @@ -155,8 +134,6 @@ static void print_cpuinfo(void) void __init setup_cpuinfo(void) { struct device_node *cpu; - unsigned long iccfgr, dccfgr; - unsigned long cache_set_size; int cpu_id =3D smp_processor_id(); struct cpuinfo_or1k *cpuinfo =3D &cpuinfo_or1k[cpu_id]; =20 @@ -164,20 +141,6 @@ void __init setup_cpuinfo(void) if (!cpu) panic("Couldn't find CPU%d in device tree...\n", cpu_id); =20 - iccfgr =3D mfspr(SPR_ICCFGR); - cpuinfo->icache_ways =3D 1 << (iccfgr & SPR_ICCFGR_NCW); - cache_set_size =3D 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); - cpuinfo->icache_block_size =3D 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7); - cpuinfo->icache_size =3D - cache_set_size * cpuinfo->icache_ways * cpuinfo->icache_block_size; - - dccfgr =3D mfspr(SPR_DCCFGR); - cpuinfo->dcache_ways =3D 1 << (dccfgr & SPR_DCCFGR_NCW); - cache_set_size =3D 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); - cpuinfo->dcache_block_size =3D 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7); - cpuinfo->dcache_size =3D - cache_set_size * cpuinfo->dcache_ways * cpuinfo->dcache_block_size; - if (of_property_read_u32(cpu, "clock-frequency", &cpuinfo->clock_frequency)) { printk(KERN_WARNING @@ -320,14 +283,6 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV); } seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ); - seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache_size); - seq_printf(m, "dcache block size\t: %d bytes\n", - cpuinfo->dcache_block_size); - seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache_ways); - seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache_size); - seq_printf(m, "icache block size\t: %d bytes\n", - cpuinfo->icache_block_size); - seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache_ways); seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n", 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2), 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW)); diff --git a/arch/openrisc/mm/cache.c b/arch/openrisc/mm/cache.c index eb43b73f3855..acdf2dc256bf 100644 --- a/arch/openrisc/mm/cache.c +++ b/arch/openrisc/mm/cache.c @@ -16,10 +16,15 @@ #include #include =20 -static __always_inline void cache_loop(struct page *page, const unsigned i= nt reg) +static __always_inline void cache_loop(struct page *page, const unsigned i= nt reg, + const unsigned int cache_type) { unsigned long paddr =3D page_to_pfn(page) << PAGE_SHIFT; unsigned long line =3D paddr & ~(L1_CACHE_BYTES - 1); + unsigned long upr =3D mfspr(SPR_UPR); + + if (!(upr & SPR_UPR_UP & cache_type)) + return; =20 while (line < paddr + PAGE_SIZE) { mtspr(reg, line); @@ -29,13 +34,13 @@ static __always_inline void cache_loop(struct page *pag= e, const unsigned int reg =20 void local_dcache_page_flush(struct page *page) { - cache_loop(page, SPR_DCBFR); + cache_loop(page, SPR_DCBFR, SPR_UPR_DCP); } EXPORT_SYMBOL(local_dcache_page_flush); =20 void local_icache_page_inv(struct page *page) { - cache_loop(page, SPR_ICBIR); + cache_loop(page, SPR_ICBIR, SPR_UPR_ICP); } EXPORT_SYMBOL(local_icache_page_inv); =20 diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c index d0cb1a0126f9..bbe16546c5b9 100644 --- a/arch/openrisc/mm/init.c +++ b/arch/openrisc/mm/init.c @@ -124,6 +124,7 @@ static void __init map_ram(void) void __init paging_init(void) { int i; + unsigned long upr; =20 printk(KERN_INFO "Setting up paging and PTEs.\n"); =20 @@ -176,8 +177,11 @@ void __init paging_init(void) barrier(); =20 /* Invalidate instruction caches after code modification */ - mtspr(SPR_ICBIR, 0x900); - mtspr(SPR_ICBIR, 0xa00); + upr =3D mfspr(SPR_UPR); + if (upr & SPR_UPR_UP & SPR_UPR_ICP) { + mtspr(SPR_ICBIR, 0x900); + mtspr(SPR_ICBIR, 0xa00); + } =20 /* New TLB miss handlers and kernel page tables are in now place. * Make sure that page flags get updated for all pages in TLB by --=20 2.48.1