From nobody Tue Dec 16 12:34:16 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A400B2066DA; Sat, 15 Mar 2025 20:16:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742069774; cv=none; b=twdR/ATV2/8pJ+TsKEV9oda6nQ8e5SuhFgG2hgZOxTYNHJLYWAlNkguzLU/LDexEIY7vgYaL7QPbxeCWwxTIEep658L02tZ5AEGy+rOPSMuFcx86B68KofFqgnnRRiOkn8H+opVOLecIDJiVGffzh8BEZTZsBl3uJddxYPymRIA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742069774; c=relaxed/simple; bh=XAdlaYzjQoosyPBD0jLktaFmMhD16smqlC6i/QRL9zQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gnrsE06y6iIrqnRDHcsZm9xS98J8urBj72dqa/EFbtG3b0Qp9HVJdfLSyZIMZ5fdfwUfkDCsht2nLVQB9xZpXh9D6vJTw6dLgmSDs5Z1IWxo2NkuHxaFqfrLvmWngtRNTBHs9ChuD6QX2olouV13yWe6TOB7lrJfzoeJPWAjcGM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Z3FvEGl8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Z3FvEGl8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5F1BDC4CEE5; Sat, 15 Mar 2025 20:16:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742069774; bh=XAdlaYzjQoosyPBD0jLktaFmMhD16smqlC6i/QRL9zQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z3FvEGl81nS7A40m+2KG5ZddWD1/06Svf1mmASBOyFwaUhXZ7ZRj9OF1XJCf/3/q4 5Kk00axEgxfhKLY9Lr729RByry0acwrXCEbA2sogmqpyNI1SExTwOUIBC361pmOjFj +aVNVNQcOTCKOvJXwe8RK7klRXAQN7xEKCD5db+YK5DryoBVipbmfnm1cc4RQriBg3 djHZ9L/NeoqRMM/ljEQzgMtM44CHEpYSsajRYG2NhIXsq7kslzErl6crWcMcWjvuJV TL3dmjsvaQ89osskOFroM7I6wc8GLV4RVsEuNDPWNt60Pa5joSSElwhWXdv2KA/AWa cIXiW943rMAfQ== From: Bjorn Helgaas To: Frank Li Cc: Rob Herring , Saravana Kannan , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Fabio Estevam , Niklas Cassel , Pengutronix Kernel Team , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, Bjorn Helgaas Subject: [PATCH v12 12/13] PCI: dwc: Use parent_bus_offset to remove need for .cpu_addr_fixup() Date: Sat, 15 Mar 2025 15:15:47 -0500 Message-Id: <20250315201548.858189-13-helgaas@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250315201548.858189-1-helgaas@kernel.org> References: <20250315201548.858189-1-helgaas@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Frank Li We know the parent_bus_offset, either computed from a DT reg property (the offset is the CPU physical addr - the 'config'/'addr_space' address on the parent bus) or from a .cpu_addr_fixup() (which may have used a host bridge window offset). Apply that parent_bus_offset instead of calling .cpu_addr_fixup() when programming the ATU. This assumes all intermediate addresses are at the same offset from the CPU physical addresses. Link: https://lore.kernel.org/r/20250313-pci_fixup_addr-v11-9-01d2313502ab@= nxp.com Signed-off-by: Frank Li [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas --- drivers/pci/controller/dwc/pcie-designware-ep.c | 5 +++-- drivers/pci/controller/dwc/pcie-designware-host.c | 12 ++++++------ drivers/pci/controller/dwc/pcie-designware.c | 3 --- 3 files changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 2ef9964fa080..c1feaadb046a 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -314,7 +314,8 @@ static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, = u8 func_no, u8 vfunc_no, struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); =20 - ret =3D dw_pcie_find_index(ep, addr, &atu_index); + ret =3D dw_pcie_find_index(ep, addr - pci->parent_bus_offset, + &atu_index); if (ret < 0) return; =20 @@ -333,7 +334,7 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 = func_no, u8 vfunc_no, =20 atu.func_no =3D func_no; atu.type =3D PCIE_ATU_TYPE_MEM; - atu.parent_bus_addr =3D addr; + atu.parent_bus_addr =3D addr - pci->parent_bus_offset; atu.pci_addr =3D pci_addr; atu.size =3D size; ret =3D dw_pcie_ep_outbound_atu(ep, &atu); diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 9e38ac7d1bcb..d760abcbb785 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -635,7 +635,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct = pci_bus *bus, type =3D PCIE_ATU_TYPE_CFG1; =20 atu.type =3D type; - atu.parent_bus_addr =3D pp->cfg0_base; + atu.parent_bus_addr =3D pp->cfg0_base - pci->parent_bus_offset; atu.pci_addr =3D busdev; atu.size =3D pp->cfg0_size; =20 @@ -660,7 +660,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, u= nsigned int devfn, =20 if (pp->cfg0_io_shared) { atu.type =3D PCIE_ATU_TYPE_IO; - atu.parent_bus_addr =3D pp->io_base; + atu.parent_bus_addr =3D pp->io_base - pci->parent_bus_offset; atu.pci_addr =3D pp->io_bus_addr; atu.size =3D pp->io_size; =20 @@ -686,7 +686,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, u= nsigned int devfn, =20 if (pp->cfg0_io_shared) { atu.type =3D PCIE_ATU_TYPE_IO; - atu.parent_bus_addr =3D pp->io_base; + atu.parent_bus_addr =3D pp->io_base - pci->parent_bus_offset; atu.pci_addr =3D pp->io_bus_addr; atu.size =3D pp->io_size; =20 @@ -755,7 +755,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) =20 atu.index =3D i; atu.type =3D PCIE_ATU_TYPE_MEM; - atu.parent_bus_addr =3D entry->res->start; + atu.parent_bus_addr =3D entry->res->start - pci->parent_bus_offset; atu.pci_addr =3D entry->res->start - entry->offset; =20 /* Adjust iATU size if MSG TLP region was allocated before */ @@ -777,7 +777,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) if (pci->num_ob_windows > ++i) { atu.index =3D i; atu.type =3D PCIE_ATU_TYPE_IO; - atu.parent_bus_addr =3D pp->io_base; + atu.parent_bus_addr =3D pp->io_base - pci->parent_bus_offset; atu.pci_addr =3D pp->io_bus_addr; atu.size =3D pp->io_size; =20 @@ -921,7 +921,7 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) atu.size =3D resource_size(pci->pp.msg_res); atu.index =3D pci->pp.msg_atu_index; =20 - atu.parent_bus_addr =3D pci->pp.msg_res->start; + atu.parent_bus_addr =3D pci->pp.msg_res->start - pci->parent_bus_offset; =20 ret =3D dw_pcie_prog_outbound_atu(pci, &atu); if (ret) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 985264c88b92..d9d2090f380c 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -475,9 +475,6 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u32 retries, val; u64 limit_addr; =20 - if (pci->ops && pci->ops->cpu_addr_fixup) - parent_bus_addr =3D pci->ops->cpu_addr_fixup(pci, parent_bus_addr); - limit_addr =3D parent_bus_addr + atu->size - 1; =20 if ((limit_addr & ~pci->region_limit) !=3D (parent_bus_addr & ~pci->regio= n_limit) || --=20 2.34.1