From nobody Wed Dec 17 20:59:45 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68CB6204C1B for ; Fri, 14 Mar 2025 17:40:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741974029; cv=pass; b=daJme/WnsJG+iAbzUS7fGLhqc4GGfbX80wql1kPTcas3ybTUdzaJPH9RU2KLMlAS+mjGoZbgLIYMAcTu8PP82hLw0/I7VPDIr9n+31/P4dtf7TBlU0f50MLl6cVfhcOYw/z0kNk4GhFxcitf5YGM26D9PyaKlmshrKztmyDFKK8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741974029; c=relaxed/simple; bh=7UTfBAh6W8ZjE7uIa2/12wzqhz3gjNHpfworaZRIunA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sSGlQkuI2XQ87ulCk3xn8JWS3ROjflmXbcGKQyHBHvxXPInf4ep+T0T5VuuQ21oWsixeA0N7rwTdUvMB6oORzzjRc99akkYvjOLAreZ2CEmuI5VVOsps4v7zlN0ztKLJi0QDgxJ/bjWNtOYqjdZe7Sn/M8ZcR5i4pexun6ygb8c= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=ariel.dalessandro@collabora.com header.b=WEZoHlmp; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=ariel.dalessandro@collabora.com header.b="WEZoHlmp" ARC-Seal: i=1; a=rsa-sha256; t=1741974005; cv=none; d=zohomail.com; s=zohoarc; b=OVx2ZuZb2XbvfWtMGwMg8Yd0k228JvVaahatKEamQAftK+jWRYdQYJQiuZmwj03/+RU9UdJhI0hOGi900yrTgLZuxpk+c52TtBwIMZQXYGX3bJOmrqLj+tntigc07APGB5YBA579ij98U2SEK2U5ZvQLICoyNLDH0e6iYgb/NaI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741974005; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=QlTpBVrKFp8ajXuiOKOxz/qINTtZfJYc0IqswtnjYwY=; b=Zq8MA0MmwqHgLcIGKFtsBK44nimk5YNtztCbczsCyvBJUMf5qJ9a3HYV04Y5yjFaJGnGn7FPTZSp+IcQ+A6/fvD01CN8DIQJKIhBLr9ETezGiftR2vHKxc0ilI9YaPznsO2/oHQJ7U7J1Zb2YnJrumTzFhTWf0t2oY6QfDX849c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=ariel.dalessandro@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1741974005; s=zohomail; d=collabora.com; i=ariel.dalessandro@collabora.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=QlTpBVrKFp8ajXuiOKOxz/qINTtZfJYc0IqswtnjYwY=; b=WEZoHlmpT7Gpb3AMOEo16QBCyqfYyokefO5v5Jlyw1H1P81z8y/Y6X3ebPffM2WX 3KMBELRSMUVrK7tYUY8IAElD9lzHupDodgJqF2iDHJR6lFYQlrC1hsFzc3j3cRiLsIR gPUSFfRaeitpJV4X0Hp6kNK21hHPt93gtXXn0N6M= Received: by mx.zohomail.com with SMTPS id 1741974003843833.6972540225984; Fri, 14 Mar 2025 10:40:03 -0700 (PDT) From: Ariel D'Alessandro To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: boris.brezillon@collabora.com, robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, kernel@collabora.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sjoerd@collabora.com, angelogioacchino.delregno@collabora.com, Ariel D'Alessandro Subject: [PATCH v2 2/6] drm/panfrost: Use GPU_MMU_FEATURES_VA_BITS/PA_BITS macros Date: Fri, 14 Mar 2025 14:38:54 -0300 Message-ID: <20250314173858.212264-3-ariel.dalessandro@collabora.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250314173858.212264-1-ariel.dalessandro@collabora.com> References: <20250314173858.212264-1-ariel.dalessandro@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Content-Type: text/plain; charset="utf-8" As done in panthor, define and use these GPU_MMU_FEATURES_* macros, which makes code easier to read and reuse. Signed-off-by: Ariel D'Alessandro Reviewed-by: Boris Brezillon Reviewed-by: Steven Price Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/panfrost/panfrost_mmu.c | 6 ++++-- drivers/gpu/drm/panfrost/panfrost_regs.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panf= rost/panfrost_mmu.c index 9e6f198ef5c1b..294f86b3c25e7 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.c +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c @@ -615,6 +615,8 @@ static void panfrost_drm_mm_color_adjust(const struct d= rm_mm_node *node, =20 struct panfrost_mmu *panfrost_mmu_ctx_create(struct panfrost_device *pfdev) { + u32 va_bits =3D GPU_MMU_FEATURES_VA_BITS(pfdev->features.mmu_features); + u32 pa_bits =3D GPU_MMU_FEATURES_PA_BITS(pfdev->features.mmu_features); struct panfrost_mmu *mmu; =20 mmu =3D kzalloc(sizeof(*mmu), GFP_KERNEL); @@ -633,8 +635,8 @@ struct panfrost_mmu *panfrost_mmu_ctx_create(struct pan= frost_device *pfdev) =20 mmu->pgtbl_cfg =3D (struct io_pgtable_cfg) { .pgsize_bitmap =3D SZ_4K | SZ_2M, - .ias =3D FIELD_GET(0xff, pfdev->features.mmu_features), - .oas =3D FIELD_GET(0xff00, pfdev->features.mmu_features), + .ias =3D va_bits, + .oas =3D pa_bits, .coherent_walk =3D pfdev->coherent, .tlb =3D &mmu_tlb_ops, .iommu_dev =3D pfdev->dev, diff --git a/drivers/gpu/drm/panfrost/panfrost_regs.h b/drivers/gpu/drm/pan= frost/panfrost_regs.h index c7bba476ab3f3..b5f279a19a084 100644 --- a/drivers/gpu/drm/panfrost/panfrost_regs.h +++ b/drivers/gpu/drm/panfrost/panfrost_regs.h @@ -16,6 +16,8 @@ #define GROUPS_L2_COHERENT BIT(0) /* Cores groups are l2 coherent */ =20 #define GPU_MMU_FEATURES 0x014 /* (RO) MMU features */ +#define GPU_MMU_FEATURES_VA_BITS(x) ((x) & GENMASK(7, 0)) +#define GPU_MMU_FEATURES_PA_BITS(x) (((x) >> 8) & GENMASK(7, 0)) #define GPU_AS_PRESENT 0x018 /* (RO) Address space slots present */ #define GPU_JS_PRESENT 0x01C /* (RO) Job slots present */ =20 --=20 2.47.2