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[2001:1c06:2302:5600:7555:cca3:bbc4:648b]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3146aeadbsm284246966b.29.2025.03.14.16.36.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 16:36:04 -0700 (PDT) From: Bryan O'Donoghue Date: Fri, 14 Mar 2025 23:36:00 +0000 Subject: [PATCH v2 7/7] media: qcom: camss: Add x1e80100 specific support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250314-b4-media-comitters-next-25-03-13-x1e80100-camss-driver-v2-7-d163d66fcc0d@linaro.org> References: <20250314-b4-media-comitters-next-25-03-13-x1e80100-camss-driver-v2-0-d163d66fcc0d@linaro.org> In-Reply-To: <20250314-b4-media-comitters-next-25-03-13-x1e80100-camss-driver-v2-0-d163d66fcc0d@linaro.org> To: Robert Foss , Todor Tomov , Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.14.2 Populate CAMSS with x1e80100 specific hooks. Signed-off-by: Bryan O'Donoghue --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 6 + drivers/media/platform/qcom/camss/camss-vfe.c | 2 + drivers/media/platform/qcom/camss/camss.c | 309 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss.h | 1 + 4 files changed, 318 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index d5f717f6215c45908c4fc5a8650d68c00d544db7..f732a76de93e3e7b787d9553bf7= f31e6c0596c58 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -749,6 +749,7 @@ static bool csiphy_is_gen2(u32 version) case CAMSS_8280XP: case CAMSS_845: case CAMSS_8550: + case CAMSS_X1E80100: ret =3D true; break; } @@ -837,6 +838,11 @@ static int csiphy_init(struct csiphy_device *csiphy) regs->lane_regs =3D &lane_regs_sc8280xp[0]; regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sc8280xp); break; + case CAMSS_X1E80100: + regs->lane_regs =3D &lane_regs_x1e80100[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100); + regs->offset =3D 0x1000; + break; case CAMSS_8550: regs->lane_regs =3D &lane_regs_sm8550[0]; regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8550); diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/= platform/qcom/camss/camss-vfe.c index cf0e8f5c004a20381e05fc8b67e068282fa08c41..33824d66dba6b887228805b2796= dcdc9825af094 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -346,6 +346,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 = sink_code, case CAMSS_8280XP: case CAMSS_845: case CAMSS_8550: + case CAMSS_X1E80100: switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_1X16: { @@ -1973,6 +1974,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) case CAMSS_8280XP: case CAMSS_845: case CAMSS_8550: + case CAMSS_X1E80100: ret =3D 16; break; default: diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 9da74da679a28070b101df06a8412e85efdcffcc..cbe9c660095da0100b36d4937be= e9e13d937a70d 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -2483,6 +2483,299 @@ static const struct resources_icc icc_res_sm8550[] = =3D { }, }; =20 +static const struct camss_subdev_resources csiphy_res_x1e80100[] =3D { + /* CSIPHY0 */ + { + .regulators =3D { "vdd-csiphy-0p8-supply", + "vdd-csiphy-1p2-supply" }, + .clock =3D { "csiphy0", "csiphy0_timer" }, + .clock_rate =3D { { 300000000, 400000000, 480000000 }, + { 266666667, 400000000 } }, + .reg =3D { "csiphy0" }, + .interrupt =3D { "csiphy0" }, + .csiphy =3D { + .id =3D 0, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, + /* CSIPHY1 */ + { + .regulators =3D { "vdd-csiphy-0p8-supply", + "vdd-csiphy-1p2-supply" }, + .clock =3D { "csiphy1", "csiphy1_timer" }, + .clock_rate =3D { { 300000000, 400000000, 480000000 }, + { 266666667, 400000000 } }, + .reg =3D { "csiphy1" }, + .interrupt =3D { "csiphy1" }, + .csiphy =3D { + .id =3D 1, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, + /* CSIPHY2 */ + { + .regulators =3D { "vdd-csiphy-0p8-supply", + "vdd-csiphy-1p2-supply" }, + .clock =3D { "csiphy2", "csiphy2_timer" }, + .clock_rate =3D { { 300000000, 400000000, 480000000 }, + { 266666667, 400000000 } }, + .reg =3D { "csiphy2" }, + .interrupt =3D { "csiphy2" }, + .csiphy =3D { + .id =3D 2, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, + /* CSIPHY4 */ + { + .regulators =3D { "vdd-csiphy-0p8-supply", + "vdd-csiphy-1p2-supply" }, + .clock =3D { "csiphy4", "csiphy4_timer" }, + .clock_rate =3D { { 300000000, 400000000, 480000000 }, + { 266666667, 400000000 } }, + .reg =3D { "csiphy4" }, + .interrupt =3D { "csiphy4" }, + .csiphy =3D { + .id =3D 4, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, +}; + +static const struct camss_subdev_resources csid_res_x1e80100[] =3D { + /* CSID0 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", + "cpas_fast_ahb", "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 64000000, 80000000 }, + { 80000000, 100000000, 200000000, + 300000000, 400000000 }, + { 300000000, 400000000, 480000000 }, + { 300000000, 400000000, 480000000 }, }, + .reg =3D { "csid0" }, + .interrupt =3D { "csid0" }, + .csid =3D { + .hw_ops =3D &csid_ops_680, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + }, + }, + /* CSID1 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", + "cpas_fast_ahb", "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 64000000, 80000000 }, + { 80000000, 100000000, 200000000, + 300000000, 400000000 }, + { 300000000, 400000000, 480000000 }, + { 300000000, 400000000, 480000000 }, }, + .reg =3D { "csid1" }, + .interrupt =3D { "csid1" }, + .csid =3D { + .hw_ops =3D &csid_ops_680, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + }, + }, + /* CSID2 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", + "cpas_fast_ahb", "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 64000000, 80000000 }, + { 80000000, 100000000, 200000000, + 300000000, 400000000 }, + { 300000000, 400000000, 480000000 }, + { 300000000, 400000000, 480000000 }, }, + .reg =3D { "csid2" }, + .interrupt =3D { "csid2" }, + .csid =3D { + .hw_ops =3D &csid_ops_680, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + }, + }, + /* CSID_LITE0 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", + "cpas_fast_ahb", "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 64000000, 80000000 }, + { 80000000, 100000000, 200000000, + 300000000, 400000000 }, + { 300000000, 400000000, 480000000 }, + { 300000000, 400000000, 480000000 }, }, + .reg =3D { "csid_lite0" }, + .interrupt =3D { "csid_lite0" }, + .csid =3D { + .is_lite =3D true, + .hw_ops =3D &csid_ops_680, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID_LITE1 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", + "cpas_fast_ahb", "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 64000000, 80000000 }, + { 80000000, 100000000, 200000000, + 300000000, 400000000 }, + { 300000000, 400000000, 480000000 }, + { 300000000, 400000000, 480000000 }, }, + + .reg =3D { "csid_lite1" }, + .interrupt =3D { "csid_lite1" }, + .csid =3D { + .is_lite =3D true, + .hw_ops =3D &csid_ops_680, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, +}; + +static const struct camss_subdev_resources vfe_res_x1e80100[] =3D { + /* IFE0 */ + { + .regulators =3D {}, + .clock =3D {"camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb", + "cpas_fast_ahb", "cpas_vfe0", "vfe0_fast_ahb", + "vfe0" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 345600000, 432000000, 594000000, 675000000, + 727000000 }, }, + .reg =3D { "vfe0" }, + .interrupt =3D { "vfe0" }, + .vfe =3D { + .line_num =3D 4, + .pd_name =3D "ife0", + .hw_ops =3D &vfe_ops_680, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + }, + }, + /* IFE1 */ + { + .regulators =3D {}, + .clock =3D { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb", + "cpas_fast_ahb", "cpas_vfe1", "vfe1_fast_ahb", + "vfe1" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 345600000, 432000000, 594000000, 675000000, + 727000000 }, }, + .reg =3D { "vfe1" }, + .interrupt =3D { "vfe1" }, + .vfe =3D { + .line_num =3D 4, + .pd_name =3D "ife1", + .hw_ops =3D &vfe_ops_680, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + }, + }, + /* IFE_LITE_0 */ + { + .regulators =3D {}, + .clock =3D { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb", + "vfe_lite_ahb", "cpas_vfe_lite", "vfe_lite", + "vfe_lite_csid" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 266666667, 400000000, 480000000 }, }, + .reg =3D { "vfe_lite0" }, + .interrupt =3D { "vfe_lite0" }, + .vfe =3D { + .is_lite =3D true, + .line_num =3D 4, + .hw_ops =3D &vfe_ops_680, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + }, + }, + /* IFE_LITE_1 */ + { + .regulators =3D {}, + .clock =3D { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb", + "vfe_lite_ahb", "cpas_vfe_lite", "vfe_lite", + "vfe_lite_csid" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 266666667, 400000000, 480000000 }, }, + .reg =3D { "vfe_lite1" }, + .interrupt =3D { "vfe_lite1" }, + .vfe =3D { + .is_lite =3D true, + .line_num =3D 4, + .hw_ops =3D &vfe_ops_680, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + }, + }, +}; + +static const struct resources_icc icc_res_x1e80100[] =3D { + { + .name =3D "ahb", + .icc_bw_tbl.avg =3D 150000, + .icc_bw_tbl.peak =3D 300000, + }, + { + .name =3D "hf_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, + { + .name =3D "sf_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, + { + .name =3D "sf_icp_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, +}; + +static const struct resources_wrapper csid_wrapper_res_x1e80100 =3D { + .reg =3D "csid_wrapper", +}; + /* * camss_add_clock_margin - Add margin to clock frequency rate * @rate: Clock frequency rate @@ -3544,6 +3837,21 @@ static const struct camss_resources sm8550_resources= =3D { .link_entities =3D camss_link_entities }; =20 +static const struct camss_resources x1e80100_resources =3D { + .version =3D CAMSS_X1E80100, + .pd_name =3D "top", + .csiphy_res =3D csiphy_res_x1e80100, + .csid_res =3D csid_res_x1e80100, + .vfe_res =3D vfe_res_x1e80100, + .csid_wrapper_res =3D &csid_wrapper_res_x1e80100, + .icc_res =3D icc_res_x1e80100, + .icc_path_num =3D ARRAY_SIZE(icc_res_x1e80100), + .csiphy_num =3D ARRAY_SIZE(csiphy_res_x1e80100), + .csid_num =3D ARRAY_SIZE(csid_res_x1e80100), + .vfe_num =3D ARRAY_SIZE(vfe_res_x1e80100), + .link_entities =3D camss_link_entities +}; + static const struct of_device_id camss_dt_match[] =3D { { .compatible =3D "qcom,msm8916-camss", .data =3D &msm8916_resources }, { .compatible =3D "qcom,msm8953-camss", .data =3D &msm8953_resources }, @@ -3555,6 +3863,7 @@ static const struct of_device_id camss_dt_match[] =3D= { { .compatible =3D "qcom,sdm845-camss", .data =3D &sdm845_resources }, { .compatible =3D "qcom,sm8250-camss", .data =3D &sm8250_resources }, { .compatible =3D "qcom,sm8550-camss", .data =3D &sm8550_resources }, + { .compatible =3D "qcom,x1e80100-camss", .data =3D &x1e80100_resources }, { } }; =20 diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index b284b910ce421c98df5e77f942f82486342bfcec..63c0afee154a02194820016ccf5= 54620d6521c8b 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -86,6 +86,7 @@ enum camss_version { CAMSS_8280XP, CAMSS_845, CAMSS_8550, + CAMSS_X1E80100, }; =20 enum icc_count { --=20 2.48.1