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Intel SDM 30.3.3.1 EPT Misconfigurations states: An EPT misconfiguration occurs if translation of a guest-physical address encounters an EPT paging-structure entry that meets any of the following conditions: - Bit 0 of the entry is clear (indicating that data reads are not allowed) and any of the following hold: =E2=80=94 Bit 1 is set (indicating that data writes are allowed). =E2=80=94 The processor does not support execute-only translations and either of the following hold: - Bit 2 is set (indicating that instruction fetches are allowed) Note: If the =E2=80=9Cmode-based execute control for EPT=E2=80=9D = VM-execution control is 1, setting bit 2 indicates that instruction fetches are allowed from supervisor-mode linear addresses. - The =E2=80=9Cmode-based execute control for EPT=E2=80=9D VM-execut= ion control is 1 and bit 10 is set (indicating that instruction fetches are allowed from user-mode linear addresses). For LKML Review: SDM 30.3.3.1 also states that "Software should read the VMX capability MSR IA32_VMX_EPT_VPID_CAP to determine whether execute-only translations are supported (see Appendix A.10)." A.10 indicates that this is specified by bit 0; if bit 0 is 1, then the processor supports execute-only transactions by EPT. Searching around a bit, it looks like this bit is checked by vmx/capabilities.h:cpu_has_vmx_ept_execute_only(), which is used only in kvm/vmx/vmx.c:vmx_hardware_setup(), passed as the has_exec_only argument to kvm_mmu_set_ept_masks(), which uses it to set shadow_present_mask. I'm not sure if this actually matters for this change(?), but thought it was at least worth surfacing for others to consider. Signed-off-by: Jon Kohler --- arch/x86/include/asm/vmx.h | 6 ++++-- arch/x86/kvm/mmu/spte.h | 13 +++++++------ 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index 84c5be416f5c..961d37e108b5 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -541,7 +541,8 @@ enum vmcs_field { #define VMX_EPT_SUPPRESS_VE_BIT (1ull << 63) #define VMX_EPT_RWX_MASK (VMX_EPT_READABLE_MASK | = \ VMX_EPT_WRITABLE_MASK | \ - VMX_EPT_EXECUTABLE_MASK) + VMX_EPT_EXECUTABLE_MASK | \ + VMX_EPT_USER_EXECUTABLE_MASK) #define VMX_EPT_MT_MASK (7ull << VMX_EPT_MT_EPTE_SHIFT) =20 static inline u8 vmx_eptp_page_walk_level(u64 eptp) @@ -558,7 +559,8 @@ static inline u8 vmx_eptp_page_walk_level(u64 eptp) =20 /* The mask to use to trigger an EPT Misconfiguration in order to track MM= IO */ #define VMX_EPT_MISCONFIG_WX_VALUE (VMX_EPT_WRITABLE_MASK | \ - VMX_EPT_EXECUTABLE_MASK) + VMX_EPT_EXECUTABLE_MASK | \ + VMX_EPT_USER_EXECUTABLE_MASK) =20 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul =20 diff --git a/arch/x86/kvm/mmu/spte.h b/arch/x86/kvm/mmu/spte.h index dc2f0dc9c46e..1f7b388a56aa 100644 --- a/arch/x86/kvm/mmu/spte.h +++ b/arch/x86/kvm/mmu/spte.h @@ -98,11 +98,11 @@ static_assert(!(EPT_SPTE_MMU_WRITABLE & SHADOW_ACC_TRAC= K_SAVED_MASK)); #undef SHADOW_ACC_TRACK_SAVED_MASK =20 /* - * Due to limited space in PTEs, the MMIO generation is a 19 bit subset of + * Due to limited space in PTEs, the MMIO generation is a 18 bit subset of * the memslots generation and is derived as follows: * - * Bits 0-7 of the MMIO generation are propagated to spte bits 3-10 - * Bits 8-18 of the MMIO generation are propagated to spte bits 52-62 + * Bits 0-6 of the MMIO generation are propagated to spte bits 3-9 + * Bits 7-17 of the MMIO generation are propagated to spte bits 52-62 * * The KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS flag is intentionally not includ= ed in * the MMIO generation number, as doing so would require stealing a bit fr= om @@ -113,7 +113,7 @@ static_assert(!(EPT_SPTE_MMU_WRITABLE & SHADOW_ACC_TRAC= K_SAVED_MASK)); */ =20 #define MMIO_SPTE_GEN_LOW_START 3 -#define MMIO_SPTE_GEN_LOW_END 10 +#define MMIO_SPTE_GEN_LOW_END 9 =20 #define MMIO_SPTE_GEN_HIGH_START 52 #define MMIO_SPTE_GEN_HIGH_END 62 @@ -135,7 +135,8 @@ static_assert(!(SPTE_MMU_PRESENT_MASK & * and so they're off-limits for generation; additional checks ensure the = mask * doesn't overlap legal PA bits), and bit 63 (carved out for future usage= ). */ -#define SPTE_MMIO_ALLOWED_MASK (BIT_ULL(63) | GENMASK_ULL(51, 12) | GENMAS= K_ULL(2, 0)) +#define SPTE_MMIO_ALLOWED_MASK (BIT_ULL(63) | GENMASK_ULL(51, 12) | \ + BIT_ULL(10) | GENMASK_ULL(2, 0)) static_assert(!(SPTE_MMIO_ALLOWED_MASK & (SPTE_MMU_PRESENT_MASK | MMIO_SPTE_GEN_LOW_MASK | MMIO_SPTE_GEN_HIGH_MAS= K))); =20 @@ -143,7 +144,7 @@ static_assert(!(SPTE_MMIO_ALLOWED_MASK & #define MMIO_SPTE_GEN_HIGH_BITS (MMIO_SPTE_GEN_HIGH_END - MMIO_SPTE_GEN_H= IGH_START + 1) =20 /* remember to adjust the comment above as well if you change these */ -static_assert(MMIO_SPTE_GEN_LOW_BITS =3D=3D 8 && MMIO_SPTE_GEN_HIGH_BITS = =3D=3D 11); +static_assert(MMIO_SPTE_GEN_LOW_BITS =3D=3D 7 && MMIO_SPTE_GEN_HIGH_BITS = =3D=3D 11); =20 #define MMIO_SPTE_GEN_LOW_SHIFT (MMIO_SPTE_GEN_LOW_START - 0) #define MMIO_SPTE_GEN_HIGH_SHIFT (MMIO_SPTE_GEN_HIGH_START - MMIO_SPTE_GEN= _LOW_BITS) --=20 2.43.0