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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147efb0csm101370866b.65.2025.03.13.09.51.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 09:51:07 -0700 (PDT) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v4 02/14] iio: accel: adxl345: move INT enable to regmap cache Date: Thu, 13 Mar 2025 16:50:37 +0000 Message-Id: <20250313165049.48305-3-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250313165049.48305-1-l.rubusch@gmail.com> References: <20250313165049.48305-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace the interrupt enable member variable to the regmap cache. This makes the function set_interrupts() obsolete. The interrupt enable register is written when the driver is probed. Thus it is perfectly cacheable. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index 6f337b26999a..10e2da7de17e 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -36,7 +36,6 @@ struct adxl345_state { struct regmap *regmap; bool fifo_delay; /* delay: delay is needed for SPI */ int irq; - u8 int_map; u8 watermark; u8 fifo_mode; __le16 fifo_buf[ADXL345_DIRS * ADXL345_FIFO_SIZE + 1] __aligned(IIO_DMA_M= INALIGN); @@ -114,11 +113,6 @@ static int adxl345_set_measure_en(struct adxl345_state= *st, bool en) return regmap_write(st->regmap, ADXL345_REG_POWER_CTL, val); } =20 -static int adxl345_set_interrupts(struct adxl345_state *st) -{ - return regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, st->int_map); -} - static int adxl345_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -217,7 +211,7 @@ static int adxl345_reg_access(struct iio_dev *indio_dev= , unsigned int reg, static int adxl345_set_watermark(struct iio_dev *indio_dev, unsigned int v= alue) { struct adxl345_state *st =3D iio_priv(indio_dev); - unsigned int fifo_mask =3D 0x1F; + const unsigned int fifo_mask =3D 0x1F, watermark_mask =3D 0x02; int ret; =20 value =3D min(value, ADXL345_FIFO_SIZE - 1); @@ -227,7 +221,10 @@ static int adxl345_set_watermark(struct iio_dev *indio= _dev, unsigned int value) return ret; =20 st->watermark =3D value; - st->int_map |=3D ADXL345_INT_WATERMARK; + ret =3D regmap_update_bits(st->regmap, ADXL345_REG_INT_ENABLE, watermark_= mask, + ADXL345_INT_WATERMARK); + if (ret) + return ret; =20 return 0; } @@ -381,11 +378,6 @@ static void adxl345_fifo_reset(struct adxl345_state *s= t) static int adxl345_buffer_postenable(struct iio_dev *indio_dev) { struct adxl345_state *st =3D iio_priv(indio_dev); - int ret; - - ret =3D adxl345_set_interrupts(st); - if (ret < 0) - return ret; =20 st->fifo_mode =3D ADXL345_FIFO_STREAM; return adxl345_set_fifo(st); @@ -401,8 +393,7 @@ static int adxl345_buffer_predisable(struct iio_dev *in= dio_dev) if (ret < 0) return ret; =20 - st->int_map =3D 0x00; - return adxl345_set_interrupts(st); + return regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, 0x00); } =20 static const struct iio_buffer_setup_ops adxl345_buffer_ops =3D { @@ -524,6 +515,11 @@ int adxl345_core_probe(struct device *dev, struct regm= ap *regmap, indio_dev->num_channels =3D ARRAY_SIZE(adxl345_channels); indio_dev->available_scan_masks =3D adxl345_scan_masks; =20 + /* Reset interrupts at start up */ + ret =3D regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, 0x00); + if (ret) + return ret; + if (setup) { /* Perform optional initial bus specific configuration */ ret =3D setup(dev, st->regmap); --=20 2.39.5