From nobody Sun Feb 8 03:21:33 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39AA0268FDB for ; Thu, 13 Mar 2025 14:31:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741876281; cv=none; b=sNsJhc0nOXZuY7Wsog2yq8zQb8Hpj3UdPq0URf5UxDc3H0axVp2pk/8EZLFPoZsEL1A81jSxw7Kx3Wnr6jYj6zEhKvn1vbR4pnRHT6c8D197xNPuRmppIQ5e2ns6mB2yNc/pLfaFLIG/4jhqxqddWzk3pIQQj998b8L9FhqfmQs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741876281; c=relaxed/simple; bh=fmZM/Tqk1HIzM9b/e4bge9cj6Urf+WrwD6iNfE9s9ZA=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=IT3Moy/jt7yppkBYyDKBlGVDoGZHYBCiYHd7TVSPdQZ8lZ7ml6v4SwWOiyM4wq2Q0Xq+4e5aCkisUJrmSMbQ9emzh/MsDDi8GekBBj9JpkVPfa9An/iOoU5oH/4iSGqldcf7Xajrx4hkX9NkEWvQPKjNoYC65pLpOxasIueCPDQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=1y4psH+T; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ALni7YM0; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="1y4psH+T"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ALni7YM0" Message-ID: <20250313142524.011345765@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741876276; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ln5jjtCvUVe3PK03Um5y8ZdmP9RcNRi7U0gcE3nH0yU=; b=1y4psH+TdMaT6dXpNkdOVnR0j9WPCM5XPjRcyWaQ6ePpotYmKKs3Jwp0yOIfhUgW7EJkTu Y8Pje/KNR4tSOL9nnHncNyWLXJQfVTy6IltxE9QUTF54J3DQmfGKINoN4A9Dt08wHGhit0 g8L9OB6xejdq0ZVWJNw/RHGF8Cloa68iCt9D2qT3KWczIvDO+pUSXnrkV0x+Zv2L6WM5ex X1oAP6BHs3NLD2rUnyrlN36R2rPo1vyvfWKyupCPPudErTnYhYRcbK/YwtoEQ1yNMnAwxa IbCstOW7Kik15Gn+v+UR1MTXrmOWcW2KEW8B42Ko2hRRzu/KqD7uoSSFIZqphg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741876276; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ln5jjtCvUVe3PK03Um5y8ZdmP9RcNRi7U0gcE3nH0yU=; b=ALni7YM0mzBSHlDPF4fVPeR7fy6Mc6J7uS+9HkBM5h1oTsj+1fCvUkcT8cEuFWHyDmguNx NxvNry07RwzewzCA== From: Thomas Gleixner To: LKML Cc: Jiri Slaby , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Linus Walleij , Bartosz Golaszewski , Talel Shenhar , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Florian Fainelli , Guo Ren , Herve Codina , Huacai Chen , Jiaxun Yang , Maxime Coquelin , Alexandre Torgue , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Subject: [patch 1/7] genirq/generic-chip: Make locking unconditional References: <20250313142404.896902416@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Thu, 13 Mar 2025 15:31:15 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SMP conditional wrappers around raw_spin_[un]lock() have no real value. On !SMP kernels the lock operations are NOOPs except for a preempt_disable/enable() pair on PREEMPT enabled kernels, which are not really worth to optimize for. Aside of that this evades lockdep on !SMP kernels. Remove the !SMP stubs and make it unconditional. No functional change. Signed-off-by: Thomas Gleixner --- include/linux/irq.h | 5 ----- 1 file changed, 5 deletions(-) --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -1219,7 +1219,6 @@ static inline struct irq_chip_type *irq_ =20 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) =20 -#ifdef CONFIG_SMP static inline void irq_gc_lock(struct irq_chip_generic *gc) { raw_spin_lock(&gc->lock); @@ -1229,10 +1228,6 @@ static inline void irq_gc_unlock(struct { raw_spin_unlock(&gc->lock); } -#else -static inline void irq_gc_lock(struct irq_chip_generic *gc) { } -static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } -#endif =20 /* * The irqsave variants are for usage in non interrupt code. Do not use From nobody Sun Feb 8 03:21:33 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49A46268FE2 for ; Thu, 13 Mar 2025 14:31:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741876282; cv=none; b=YnAYvx0b0OS4aI6ZHbvs2oqP/ptnWK4d9o/bKrTDFCAq4GbMpH2xBhYJk+wKSZny1sGkeRh46OJySAT9WAh1wZ6Do4PEzGJaOraAmd0YYcQBgULP+JKEyyjtoFDQGcEnnoEkszD9urwLJN2Tw7ubuNCNT0cY3gKkjA78NtKH53k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741876282; c=relaxed/simple; bh=T7XQKx+q8ClaipQug0jIEZIEuJpDA9f/d9I3/ZBzCJk=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=ngHbjRRMKO6pL7jsRNV9if6FpA4X6SHsBS7D6lyTzgiVcCjXMXYGdxwRSyps5TZpdUqeMGVaZaWDpf1aa+bGAQxaTp/yD25v9oCjWcT31M3FrHbKYw64JA6Ja1Qmdvb5yBhc9QKoKmqAIc8ib5v0K0w8TtkbYJEz1OSpb7VGtzA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Xgxsboqb; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=xE6ajUEU; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Xgxsboqb"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="xE6ajUEU" Message-ID: <20250313142524.073826193@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741876278; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=b6xi2K4qzElaL97ZoIu4lP2Q0gu96SOJ6XZrZdkCrVc=; b=XgxsboqbA48WXi5Vt1RrHkC+tgHT4Q1XqzVcXnbW5Uo4xqlzNhHk3cCDf2F85bcGx7j5ul yqzhXL9fSSjO3tU0ir9hQSOQBfoAyo6w3gjGuSeY9DNAOJsxeucO+ra/xwU+g9ZDq+qm1C 2A0nYRgLHs4Rj8FNObsmoQ/7BzJtOkrlNIxU4lfxPKN8WbthcfTAEyK2GnzWPBXJPl1Ltq 1si+BOJgxbFgI0y1Lgs0tFdrF6kt/aHFpGAEFD3Tfdo+7QeYelOZakolCev8crJe9Nyk8r bQwWdqUT5rfjjbN60VnOhwk/PK5Zd14OTG4AsBfDhFJWjSOdRghVz4vC/tJSxw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741876278; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=b6xi2K4qzElaL97ZoIu4lP2Q0gu96SOJ6XZrZdkCrVc=; b=xE6ajUEUYzmG5dnkXw67ssobNneky5pg8qGkWixSv+RaVNPsqUZ1scxPF65isGNYdq+T0w 7uYW2PfymRSr6HBQ== From: Thomas Gleixner To: LKML Cc: Jiri Slaby , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Linus Walleij , Bartosz Golaszewski , Talel Shenhar , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Florian Fainelli , Guo Ren , Herve Codina , Huacai Chen , Jiaxun Yang , Maxime Coquelin , Alexandre Torgue , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Subject: [patch 2/7] genirq/generic-chip: Convert core code to lock guards References: <20250313142404.896902416@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Thu, 13 Mar 2025 15:31:17 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace the irq_gc_lock/unlock() pairs with guards. There is no point to implement a guard wrapper for them as they just wrap around raw_spin_lock*(= ). Switch the other lock instances in the core code to guards as well. Conversion was done with Coccinelle plus manual fixups. No functional change. Signed-off-by: Thomas Gleixner Reviewed-by: Linus Walleij --- kernel/irq/generic-chip.c | 47 +++++++++++++++--------------------------= ----- 1 file changed, 16 insertions(+), 31 deletions(-) --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -40,10 +40,9 @@ void irq_gc_mask_disable_reg(struct irq_ struct irq_chip_type *ct =3D irq_data_get_chip_type(d); u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); irq_reg_writel(gc, mask, ct->regs.disable); *ct->mask_cache &=3D ~mask; - irq_gc_unlock(gc); } EXPORT_SYMBOL_GPL(irq_gc_mask_disable_reg); =20 @@ -60,10 +59,9 @@ void irq_gc_mask_set_bit(struct irq_data struct irq_chip_type *ct =3D irq_data_get_chip_type(d); u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); *ct->mask_cache |=3D mask; irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); - irq_gc_unlock(gc); } EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit); =20 @@ -80,10 +78,9 @@ void irq_gc_mask_clr_bit(struct irq_data struct irq_chip_type *ct =3D irq_data_get_chip_type(d); u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); *ct->mask_cache &=3D ~mask; irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); - irq_gc_unlock(gc); } EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit); =20 @@ -100,10 +97,9 @@ void irq_gc_unmask_enable_reg(struct irq struct irq_chip_type *ct =3D irq_data_get_chip_type(d); u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); irq_reg_writel(gc, mask, ct->regs.enable); *ct->mask_cache |=3D mask; - irq_gc_unlock(gc); } EXPORT_SYMBOL_GPL(irq_gc_unmask_enable_reg); =20 @@ -117,9 +113,8 @@ void irq_gc_ack_set_bit(struct irq_data struct irq_chip_type *ct =3D irq_data_get_chip_type(d); u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); irq_reg_writel(gc, mask, ct->regs.ack); - irq_gc_unlock(gc); } EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit); =20 @@ -133,9 +128,8 @@ void irq_gc_ack_clr_bit(struct irq_data struct irq_chip_type *ct =3D irq_data_get_chip_type(d); u32 mask =3D ~d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); irq_reg_writel(gc, mask, ct->regs.ack); - irq_gc_unlock(gc); } =20 /** @@ -156,11 +150,10 @@ void irq_gc_mask_disable_and_ack_set(str struct irq_chip_type *ct =3D irq_data_get_chip_type(d); u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); irq_reg_writel(gc, mask, ct->regs.disable); *ct->mask_cache &=3D ~mask; irq_reg_writel(gc, mask, ct->regs.ack); - irq_gc_unlock(gc); } EXPORT_SYMBOL_GPL(irq_gc_mask_disable_and_ack_set); =20 @@ -174,9 +167,8 @@ void irq_gc_eoi(struct irq_data *d) struct irq_chip_type *ct =3D irq_data_get_chip_type(d); u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); irq_reg_writel(gc, mask, ct->regs.eoi); - irq_gc_unlock(gc); } =20 /** @@ -196,12 +188,11 @@ int irq_gc_set_wake(struct irq_data *d, if (!(mask & gc->wake_enabled)) return -EINVAL; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); if (on) gc->wake_active |=3D mask; else gc->wake_active &=3D ~mask; - irq_gc_unlock(gc); return 0; } EXPORT_SYMBOL_GPL(irq_gc_set_wake); @@ -288,7 +279,6 @@ int irq_domain_alloc_generic_chips(struc { struct irq_domain_chip_generic *dgc; struct irq_chip_generic *gc; - unsigned long flags; int numchips, i; size_t dgc_sz; size_t gc_sz; @@ -340,9 +330,8 @@ int irq_domain_alloc_generic_chips(struc goto err; } =20 - raw_spin_lock_irqsave(&gc_lock, flags); - list_add_tail(&gc->list, &gc_list); - raw_spin_unlock_irqrestore(&gc_lock, flags); + scoped_guard (raw_spinlock, &gc_lock) + list_add_tail(&gc->list, &gc_list); /* Calc pointer to the next generic chip */ tmp +=3D gc_sz; } @@ -459,7 +448,6 @@ int irq_map_generic_chip(struct irq_doma struct irq_chip_generic *gc; struct irq_chip_type *ct; struct irq_chip *chip; - unsigned long flags; int idx; =20 gc =3D __irq_get_domain_generic_chip(d, hw_irq); @@ -479,9 +467,8 @@ int irq_map_generic_chip(struct irq_doma =20 /* We only init the cache for the first mapping of a generic chip */ if (!gc->installed) { - raw_spin_lock_irqsave(&gc->lock, flags); + guard(raw_spinlock_irq)(&gc->lock); irq_gc_init_mask_cache(gc, dgc->gc_flags); - raw_spin_unlock_irqrestore(&gc->lock, flags); } =20 /* Mark the interrupt as installed */ @@ -548,9 +535,8 @@ void irq_setup_generic_chip(struct irq_c struct irq_chip *chip =3D &ct->chip; unsigned int i; =20 - raw_spin_lock(&gc_lock); - list_add_tail(&gc->list, &gc_list); - raw_spin_unlock(&gc_lock); + scoped_guard (raw_spinlock, &gc_lock) + list_add_tail(&gc->list, &gc_list); =20 irq_gc_init_mask_cache(gc, flags); =20 @@ -616,9 +602,8 @@ void irq_remove_generic_chip(struct irq_ { unsigned int i, virq; =20 - raw_spin_lock(&gc_lock); - list_del(&gc->list); - raw_spin_unlock(&gc_lock); + scoped_guard (raw_spinlock, &gc_lock) + list_del(&gc->list); =20 for (i =3D 0; msk; msk >>=3D 1, i++) { if (!(msk & 0x01)) From nobody Sun Feb 8 03:21:33 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A18EA26AAAB for ; Thu, 13 Mar 2025 14:31:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741876285; cv=none; b=ftb9vQheXv5TD+djR+OziccuQyGtZ2Yh0J99S+AcvVitQ5mW3k7lzQb3qZwZOwlLcF8e5LMrLFmwB+j/K9JL8Xjbr4z9F1vHMmqmmiKZik8uX/Ow0rwJOquEpzXfE7wBk383FTDLyIYMgQIrpbTjt8de2fmpG66K0TTxb6/Z/So= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741876285; c=relaxed/simple; bh=+JB9Ocsn0N2uorbOemG2UPiOduyPmgQApN2d3X4aVhc=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=AVavji2VgHhgXWjf7Qa5KXBNZKT75karzmEtMVmbad6TtMWyE4nilj0HG84tuNGtMXNxw9qLosyGl97mNh57yvosG+UnyVLZMsoZUkyIJeAbvSiOfsOr1QNdsWvCeRu9ECttXM/dUKI5vS1tkqgI02oZtite0Jv8+eNGcdywioo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=4BJHWMMF; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=+JGC1e/W; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="4BJHWMMF"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="+JGC1e/W" Message-ID: <20250313142524.137040686@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741876282; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=A0Y3nQwiTGknc15vMfS4EhndGBYyh9HpDOM/blEDOO8=; b=4BJHWMMF1BibSWqsqWwwwIkIeOgtpoIKyLp8vCqCOPkSH3VRooBO9yvW3jT9rMmniQL9kb 8Prbik/3KXSG/E4QOYOAmOBwk869G/z1yYP0J6bsl5Gsg/EAfGF2LohcHYaUBizQTxzrcP Dkk9n7EEIGmQyGBLRPkyalyCre2NwzzRFfivJY+kG8qzyo1+ix/xIgA17CrRE3gAik/U6U zRh5y4pgqfP7qWT+6mf30e5//cBN2DQUkXPbRfF4RYOq3/jVysZy6/McWOEQFs7s9pJb/l IrDCOBqlCXLi+rVZNoMX8z+8OeYU+mhpJy3KoUwxB3HOG9w+l2izbjn0iSLuCg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741876282; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=A0Y3nQwiTGknc15vMfS4EhndGBYyh9HpDOM/blEDOO8=; b=+JGC1e/WpkbKDC9sqX/LxiseXYyGxcyX7WP/rsYpG/2vhvmsry4CmlTDysCCyCsqa6jJIU OX8IqURgqfRusiAw== From: Thomas Gleixner To: LKML Cc: Jiri Slaby , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Linus Walleij , Bartosz Golaszewski , Talel Shenhar , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Florian Fainelli , Guo Ren , Herve Codina , Huacai Chen , Jiaxun Yang , Maxime Coquelin , Alexandre Torgue , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Subject: [patch 3/7] soc: dove: Convert generic irqchip locking to guard() References: <20250313142404.896902416@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Thu, 13 Mar 2025 15:31:21 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Conversion was done with Coccinelle. No functional change. Signed-off-by: Thomas Gleixner Cc: Andrew Lunn Cc: Sebastian Hesselbarth Cc: Gregory Clement Reviewed-by: Andrew Lunn Reviewed-by: Linus Walleij --- drivers/soc/dove/pmu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) --- a/drivers/soc/dove/pmu.c +++ b/drivers/soc/dove/pmu.c @@ -257,10 +257,9 @@ static void pmu_irq_handler(struct irq_d * So, let's structure the code so that the window is as small as * possible. */ - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); done &=3D readl_relaxed(base + PMC_IRQ_CAUSE); writel_relaxed(done, base + PMC_IRQ_CAUSE); - irq_gc_unlock(gc); } =20 static int __init dove_init_pmu_irq(struct pmu_data *pmu, int irq) From nobody Sun Feb 8 03:21:33 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C199926B09A for ; Thu, 13 Mar 2025 14:31:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741876287; cv=none; b=JyFg1touD/SydRGA4Vaagg/rx/jZ4D+gSYOldxuD0bQxJviwJpJpfFJl9zyECqiwMqZh5mVoxD/sZTP8uaG39h4qahkVIJqbAn/XjXoG+Kdjz5shm6FeYYapEvHMgzvxMOyZN2vZqBTGK+kc6TERTKpH6nKtV7aZabKotnue79M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741876287; c=relaxed/simple; bh=WzPlEzkz/4dQUiaViKPTEHdTWix1qz0LninNbgUeLCo=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=OOMXzzG3pXRKkGXr+g2spEjSABqw3iCguMxkp0Nism4IdhyK3rDnh7IsqdTf59aO/CpAYig5ZHgzFFDe977d3IMYaYAmF8asMY1XODD5zqkTJ/mniZYDC2qz/QPGu5dw80XH6JcL7bFCUgb+Oih9w74hYkaksvJ9bNTpwFQ1Z7M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=zRHDiLUY; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=+/GR2xJn; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="zRHDiLUY"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="+/GR2xJn" Message-ID: <20250313142524.200515896@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741876284; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=BRHGQxdmButnD0h4dgcR8icVvakqQ54h6/za0dNjYUA=; b=zRHDiLUYoBHQXxxJZE/2IiT1bLCMS+q07ZuZkCbzUKrUvLldZbPUjDVj3JHakG0LNWAlwC SdZgZkoC8QjRnMboem96wPQLAkWxYYbhF7OupzcsineIheYVGrE8foXnNldt4u2gcnxkP4 6y8mUlOAv4dUJ4Ini3y3c9YSBenyFj58vzQPeRO+kFkDlFwM46ZtJ9sE9e+dQqXbqzQ4oD BLp8tZjprFGQu8XvZ08LY3fjWGAQXr/XWz3Vm2w2Qjr08Z7obgiuo7QKcTGloWiqi6JqjN 409aMhQTg0nUnpz10vavLuKEYntZ5Z0JfSwwII3zFC+epm2QHxsMSGMlMFFnbQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741876284; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=BRHGQxdmButnD0h4dgcR8icVvakqQ54h6/za0dNjYUA=; b=+/GR2xJnrmclNdX+D20Qx/CkKzQDjKWLYK9EWpHpVkcWOXjCYoMWF7z4w8rRtbRJSwRwRd 9loOJYxVi9uV48DQ== From: Thomas Gleixner To: LKML Cc: Jiri Slaby , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Linus Walleij , Bartosz Golaszewski , Talel Shenhar , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Florian Fainelli , Guo Ren , Herve Codina , Huacai Chen , Jiaxun Yang , Maxime Coquelin , Alexandre Torgue , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Subject: [patch 4/7] ARM: orion/gpio:: Convert generic irqchip locking to guard() References: <20250313142404.896902416@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Thu, 13 Mar 2025 15:31:23 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Conversion was done with Coccinelle. No functional change. Signed-off-by: Thomas Gleixner Cc: Andrew Lunn Cc: Sebastian Hesselbarth Cc: Gregory Clement Reviewed-by: Linus Walleij --- arch/arm/plat-orion/gpio.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -496,11 +496,10 @@ static void orion_gpio_unmask_irq(struct u32 reg_val; u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); reg_val =3D irq_reg_readl(gc, ct->regs.mask); reg_val |=3D mask; irq_reg_writel(gc, reg_val, ct->regs.mask); - irq_gc_unlock(gc); } =20 static void orion_gpio_mask_irq(struct irq_data *d) @@ -510,11 +509,10 @@ static void orion_gpio_mask_irq(struct i u32 mask =3D d->mask; u32 reg_val; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); reg_val =3D irq_reg_readl(gc, ct->regs.mask); reg_val &=3D ~mask; irq_reg_writel(gc, reg_val, ct->regs.mask); - irq_gc_unlock(gc); } =20 void __init orion_gpio_init(int gpio_base, int ngpio, From nobody Sun Feb 8 03:21:33 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2F742690D7 for ; Thu, 13 Mar 2025 14:31:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741876289; cv=none; b=Eg2MOUke0leaGt7vqsQGT/zqaz6DhS9x4/cIzWNl37Rp5+sAFnh6nt58XPKE4fSuaxeQgQIbMiAxtSzsWqeicif3RkVf1lLYRDPSINvFwh+hHSaoOvpCmAmyJbj0FlX45d2rVhzW6j1APhKzVTOMJ5ytYuuxH4PB/zdkG46UAYs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741876289; c=relaxed/simple; bh=R/tbVQX4irVKizht3N6CAf60t+XpVFHCf8549iWeQ2c=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=AzQvlxe6vcC+vVkqwLXDdba5Glg19NSLILkO/Veb86RMnwkKpQvDUaGB0F+v0v/+BmKgAIRZc4cIzSPa1gSuyJhmI76pyOsTwBP/2ZicGxje1/PwfN1nX0Xu8ZGBdNfPFbUsAFeaoBree6Fmsqg68PDRgvXFnJWl7Ibhvf6SzcQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=QBZeRW88; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=3nLa01jS; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="QBZeRW88"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="3nLa01jS" Message-ID: <20250313142524.262678485@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741876286; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=2M7Q8pgd1DfVFDda6qhY86N7xmWT5erMVHn5T+YvIAA=; b=QBZeRW88RUJNNZ1vDnn0AXalgTOfQpECA35V7KXyZ+fPasH6FFZOUPMf9N2Gs9BJnPMJah ksmk7Foet2NeSPIgeHbZEnjN1EfhDWhEAYePRqEfe1b92BNLtHBTEYRRnizNFjhBzd/s6k seUCg6JlOAPU3OQ02sZAxGdBVwNwRGNVcgwNtqOd3t1nyiT9qj3si+m21GDFSdzi+Azdfh 8ayKvlplKf+2idyzO9UtN6oYEHo5DmHREVKmWF9RiNyS9NuXSrcFG8lJm4cBOXP7na1gVP dYlQpIJ3lOtqtah8v5nRyVRAN86fF7d8krxbmvMtmdl2BI7L2w4SGTIMOpxONA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741876286; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=2M7Q8pgd1DfVFDda6qhY86N7xmWT5erMVHn5T+YvIAA=; b=3nLa01jSlUdlKK1L/ejOZJ7Cu4JE2q0ujmnyskgNILBCbC9HKh9ytBGSfUCyZBLT8991OC fMCmlYrU3DQd/2Dw== From: Thomas Gleixner To: LKML Cc: Jiri Slaby , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Linus Walleij , Bartosz Golaszewski , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Talel Shenhar , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Florian Fainelli , Guo Ren , Herve Codina , Huacai Chen , Jiaxun Yang , Maxime Coquelin , Alexandre Torgue , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Subject: [patch 5/7] gpio: mvebu: Convert generic irqchip locking to guard() References: <20250313142404.896902416@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Date: Thu, 13 Mar 2025 15:31:25 +0100 (CET) Content-Transfer-Encoding: quoted-printable Signed-off-by: Thomas Gleixner Cc: "Uwe Kleine-K=C3=B6nig" Cc: Linus Walleij Cc: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-mvebu.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) --- a/drivers/gpio/gpio-mvebu.c +++ b/drivers/gpio/gpio-mvebu.c @@ -407,9 +407,8 @@ static void mvebu_gpio_irq_ack(struct ir struct mvebu_gpio_chip *mvchip =3D gc->private; u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); mvebu_gpio_write_edge_cause(mvchip, ~mask); - irq_gc_unlock(gc); } =20 static void mvebu_gpio_edge_irq_mask(struct irq_data *d) @@ -419,10 +418,9 @@ static void mvebu_gpio_edge_irq_mask(str struct irq_chip_type *ct =3D irq_data_get_chip_type(d); u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); ct->mask_cache_priv &=3D ~mask; mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); - irq_gc_unlock(gc); } =20 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) @@ -432,11 +430,10 @@ static void mvebu_gpio_edge_irq_unmask(s struct irq_chip_type *ct =3D irq_data_get_chip_type(d); u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); mvebu_gpio_write_edge_cause(mvchip, ~mask); ct->mask_cache_priv |=3D mask; mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); - irq_gc_unlock(gc); } =20 static void mvebu_gpio_level_irq_mask(struct irq_data *d) @@ -446,10 +443,9 @@ static void mvebu_gpio_level_irq_mask(st struct irq_chip_type *ct =3D irq_data_get_chip_type(d); u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); ct->mask_cache_priv &=3D ~mask; mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); - irq_gc_unlock(gc); } =20 static void mvebu_gpio_level_irq_unmask(struct irq_data *d) @@ -459,10 +455,9 @@ static void mvebu_gpio_level_irq_unmask( struct irq_chip_type *ct =3D irq_data_get_chip_type(d); u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); ct->mask_cache_priv |=3D mask; mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); - irq_gc_unlock(gc); } =20 /*************************************************************************= **** From nobody Sun Feb 8 03:21:33 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C40826B2B7 for ; Thu, 13 Mar 2025 14:31:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741876291; cv=none; b=FAGdW47Vpt0GElV8zdnMBPioyu6wECFpwzqQGXa1/vSWxOCZrojI5fM2lWvG0NLdi49LiLQFgguPpx8HBrplFkYTuLRqtLufZjMgyPYpMl2F/g+tnc167//B/IycbZft8+8e0YJGxeqae0mGPF1J2ec/XZtwO+ueQnDcK8ZS30o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741876291; c=relaxed/simple; bh=87joYPqm/q8/AgvHEJQ/63GelvWJvARZHw6jtUZe2eU=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=W9xhsjT9Ie7dh4NinlioF2qPGd89dW5Nh+1B0LrWvYElJt001oEhypDbsRGfjMDdzMeZCMi0pTGxznP4ppq7c4CzJD5oD2uLnoFUKrQJwLkID56BlAPR1S+CrhfzXffkePPlEmVibDXMwn8mGhx+vUoHAYvalbdvBapcSYC0d3M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=OtAkI/WN; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=z3Tp3vN/; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="OtAkI/WN"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="z3Tp3vN/" Message-ID: <20250313142524.325627746@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741876287; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=pE722dPMNjtzGAJQa5Zko2sjXVH9GjulNjaBBb5Ewas=; b=OtAkI/WN4cdagJEsy5+AuTCsOWitqSk8Xc9hgNugfSElngEaTUJGsjC0M0Nc1d3Zw594d5 GjYaHqTwwrZYMMyYnP+WO2O2Ev3FSK5kMIQI37ZMvBsa/WBCsuqNBlpc5E5R0fORmEWHzN ztcrymXWVHZni/SH+UeXGsTC3USo/B6tXkOLkFdK+koNWem4ns0RqEWiNVUT1zzUesKR0B GiETHj3O3EDIsFrvueFmJsxKFOL4J+7+O11sOQbsYQJ6tH2lSXNIGfe9M0Cpe7eqM06MNE HdZCbv1mZMwM+4QUv3pp5tCX8PGas1qprxquvV5xCXJa6Ko0g+NHxqVSge7Mkg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741876287; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=pE722dPMNjtzGAJQa5Zko2sjXVH9GjulNjaBBb5Ewas=; b=z3Tp3vN/uVTynTGyLhfYDR//Qums7dCdlFLV9y/HKgEaTlxt/q9dh+DTdj9jZCYtYaju2b A+CL/KxZZUniMaAg== From: Thomas Gleixner To: LKML Cc: Jiri Slaby , Talel Shenhar , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Florian Fainelli , Guo Ren , Herve Codina , Huacai Chen , Jiaxun Yang , Maxime Coquelin , Alexandre Torgue , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Linus Walleij , Bartosz Golaszewski Subject: [patch 6/7] irqchip: Convert generic irqchip locking to guards References: <20250313142404.896902416@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Thu, 13 Mar 2025 15:31:27 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Conversion was done with Coccinelle and a few manual fixups. In a few interrupt chip callbacks this changes replaces raw_spin_lock_irqsave() with a guard(raw_spinlock). That's intended and correct because those interrupt chip callbacks are invoked with the interrupt descriptor lock held and interrupts disabled. No point in using the irqsave variant. No functional change. Signed-off-by: Thomas Gleixner Cc: Talel Shenhar Cc: Nicolas Ferre Cc: Alexandre Belloni Cc: Claudiu Beznea Cc: Florian Fainelli Cc: Guo Ren Cc: Herve Codina Cc: Huacai Chen Cc: Jiaxun Yang Cc: Maxime Coquelin Cc: Alexandre Torgue Cc: Chen-Yu Tsai Cc: Jernej Skrabec Cc: Samuel Holland Reviewed-by: Linus Walleij --- drivers/irqchip/irq-al-fic.c | 18 +++++------------- drivers/irqchip/irq-atmel-aic.c | 19 ++++++------------- drivers/irqchip/irq-atmel-aic5.c | 28 ++++++++-------------------- drivers/irqchip/irq-bcm7120-l2.c | 22 +++++++++------------- drivers/irqchip/irq-brcmstb-l2.c | 8 ++------ drivers/irqchip/irq-csky-apb-intc.c | 3 +-- drivers/irqchip/irq-dw-apb-ictl.c | 3 +-- drivers/irqchip/irq-ingenic-tcu.c | 9 +++------ drivers/irqchip/irq-lan966x-oic.c | 18 +++++++----------- drivers/irqchip/irq-loongson-liointc.c | 9 ++------- drivers/irqchip/irq-mscc-ocelot.c | 3 +-- drivers/irqchip/irq-stm32-exti.c | 21 ++++++--------------- drivers/irqchip/irq-sunxi-nmi.c | 9 ++------- drivers/irqchip/irq-tb10x.c | 13 +++---------- 14 files changed, 56 insertions(+), 127 deletions(-) --- a/drivers/irqchip/irq-al-fic.c +++ b/drivers/irqchip/irq-al-fic.c @@ -65,15 +65,13 @@ static int al_fic_irq_set_type(struct ir struct irq_chip_generic *gc =3D irq_data_get_irq_chip_data(data); struct al_fic *fic =3D gc->private; enum al_fic_state new_state; - int ret =3D 0; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); =20 if (((flow_type & IRQ_TYPE_SENSE_MASK) !=3D IRQ_TYPE_LEVEL_HIGH) && ((flow_type & IRQ_TYPE_SENSE_MASK) !=3D IRQ_TYPE_EDGE_RISING)) { pr_debug("fic doesn't support flow type %d\n", flow_type); - ret =3D -EINVAL; - goto err; + return -EINVAL; } =20 new_state =3D (flow_type & IRQ_TYPE_LEVEL_HIGH) ? @@ -91,16 +89,10 @@ static int al_fic_irq_set_type(struct ir if (fic->state =3D=3D AL_FIC_UNCONFIGURED) { al_fic_set_trigger(fic, gc, new_state); } else if (fic->state !=3D new_state) { - pr_debug("fic %s state already configured to %d\n", - fic->name, fic->state); - ret =3D -EINVAL; - goto err; + pr_debug("fic %s state already configured to %d\n", fic->name, fic->stat= e); + return -EINVAL; } - -err: - irq_gc_unlock(gc); - - return ret; + return 0; } =20 static void al_fic_irq_handler(struct irq_desc *desc) --- a/drivers/irqchip/irq-atmel-aic.c +++ b/drivers/irqchip/irq-atmel-aic.c @@ -78,9 +78,8 @@ static int aic_retrigger(struct irq_data struct irq_chip_generic *gc =3D irq_data_get_irq_chip_data(d); =20 /* Enable interrupt on AIC5 */ - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); irq_reg_writel(gc, d->mask, AT91_AIC_ISCR); - irq_gc_unlock(gc); =20 return 1; } @@ -106,30 +105,27 @@ static void aic_suspend(struct irq_data { struct irq_chip_generic *gc =3D irq_data_get_irq_chip_data(d); =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IDCR); irq_reg_writel(gc, gc->wake_active, AT91_AIC_IECR); - irq_gc_unlock(gc); } =20 static void aic_resume(struct irq_data *d) { struct irq_chip_generic *gc =3D irq_data_get_irq_chip_data(d); =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); irq_reg_writel(gc, gc->wake_active, AT91_AIC_IDCR); irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IECR); - irq_gc_unlock(gc); } =20 static void aic_pm_shutdown(struct irq_data *d) { struct irq_chip_generic *gc =3D irq_data_get_irq_chip_data(d); =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR); irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR); - irq_gc_unlock(gc); } #else #define aic_suspend NULL @@ -175,10 +171,8 @@ static int aic_irq_domain_xlate(struct i { struct irq_domain_chip_generic *dgc =3D d->gc; struct irq_chip_generic *gc; - unsigned long flags; unsigned smr; - int idx; - int ret; + int idx, ret; =20 if (!dgc) return -EINVAL; @@ -194,11 +188,10 @@ static int aic_irq_domain_xlate(struct i =20 gc =3D dgc->gc[idx]; =20 - irq_gc_lock_irqsave(gc, flags); + guard(raw_spinlock_irq)(&gc->lock); smr =3D irq_reg_readl(gc, AT91_AIC_SMR(*out_hwirq)); aic_common_set_priority(intspec[2], &smr); irq_reg_writel(gc, smr, AT91_AIC_SMR(*out_hwirq)); - irq_gc_unlock_irqrestore(gc, flags); =20 return ret; } --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -92,11 +92,10 @@ static void aic5_mask(struct irq_data *d * Disable interrupt on AIC5. We always take the lock of the * first irq chip as all chips share the same registers. */ - irq_gc_lock(bgc); + guard(raw_spinlock)(&bgc->lock); irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR); irq_reg_writel(gc, 1, AT91_AIC5_IDCR); gc->mask_cache &=3D ~d->mask; - irq_gc_unlock(bgc); } =20 static void aic5_unmask(struct irq_data *d) @@ -109,11 +108,10 @@ static void aic5_unmask(struct irq_data * Enable interrupt on AIC5. We always take the lock of the * first irq chip as all chips share the same registers. */ - irq_gc_lock(bgc); + guard(raw_spinlock)(&bgc->lock); irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR); irq_reg_writel(gc, 1, AT91_AIC5_IECR); gc->mask_cache |=3D d->mask; - irq_gc_unlock(bgc); } =20 static int aic5_retrigger(struct irq_data *d) @@ -122,11 +120,9 @@ static int aic5_retrigger(struct irq_dat struct irq_chip_generic *bgc =3D irq_get_domain_generic_chip(domain, 0); =20 /* Enable interrupt on AIC5 */ - irq_gc_lock(bgc); + guard(raw_spinlock)(&bgc->lock); irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR); irq_reg_writel(bgc, 1, AT91_AIC5_ISCR); - irq_gc_unlock(bgc); - return 1; } =20 @@ -137,14 +133,12 @@ static int aic5_set_type(struct irq_data unsigned int smr; int ret; =20 - irq_gc_lock(bgc); + guard(raw_spinlock)(&bgc->lock); irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR); smr =3D irq_reg_readl(bgc, AT91_AIC5_SMR); ret =3D aic_common_set_type(d, type, &smr); if (!ret) irq_reg_writel(bgc, smr, AT91_AIC5_SMR); - irq_gc_unlock(bgc); - return ret; } =20 @@ -166,7 +160,7 @@ static void aic5_suspend(struct irq_data smr_cache[i] =3D irq_reg_readl(bgc, AT91_AIC5_SMR); } =20 - irq_gc_lock(bgc); + guard(raw_spinlock)(&bgc->lock); for (i =3D 0; i < dgc->irqs_per_chip; i++) { mask =3D 1 << i; if ((mask & gc->mask_cache) =3D=3D (mask & gc->wake_active)) @@ -178,7 +172,6 @@ static void aic5_suspend(struct irq_data else irq_reg_writel(bgc, 1, AT91_AIC5_IDCR); } - irq_gc_unlock(bgc); } =20 static void aic5_resume(struct irq_data *d) @@ -190,7 +183,7 @@ static void aic5_resume(struct irq_data int i; u32 mask; =20 - irq_gc_lock(bgc); + guard(raw_spinlock)(&bgc->lock); =20 if (smr_cache) { irq_reg_writel(bgc, 0xffffffff, AT91_AIC5_SPU); @@ -214,7 +207,6 @@ static void aic5_resume(struct irq_data else irq_reg_writel(bgc, 1, AT91_AIC5_IDCR); } - irq_gc_unlock(bgc); } =20 static void aic5_pm_shutdown(struct irq_data *d) @@ -225,13 +217,12 @@ static void aic5_pm_shutdown(struct irq_ struct irq_chip_generic *gc =3D irq_data_get_irq_chip_data(d); int i; =20 - irq_gc_lock(bgc); + guard(raw_spinlock)(&bgc->lock); for (i =3D 0; i < dgc->irqs_per_chip; i++) { irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR); irq_reg_writel(bgc, 1, AT91_AIC5_IDCR); irq_reg_writel(bgc, 1, AT91_AIC5_ICCR); } - irq_gc_unlock(bgc); } #else #define aic5_suspend NULL @@ -277,7 +268,6 @@ static int aic5_irq_domain_xlate(struct unsigned int *out_type) { struct irq_chip_generic *bgc =3D irq_get_domain_generic_chip(d, 0); - unsigned long flags; unsigned smr; int ret; =20 @@ -289,13 +279,11 @@ static int aic5_irq_domain_xlate(struct if (ret) return ret; =20 - irq_gc_lock_irqsave(bgc, flags); + guard(raw_spinlock_irq)(&bgc->lock); irq_reg_writel(bgc, *out_hwirq, AT91_AIC5_SSR); smr =3D irq_reg_readl(bgc, AT91_AIC5_SMR); aic_common_set_priority(intspec[2], &smr); irq_reg_writel(bgc, smr, AT91_AIC5_SMR); - irq_gc_unlock_irqrestore(bgc, flags); - return ret; } =20 --- a/drivers/irqchip/irq-bcm7120-l2.c +++ b/drivers/irqchip/irq-bcm7120-l2.c @@ -63,16 +63,15 @@ static void bcm7120_l2_intc_irq_handle(s =20 for (idx =3D 0; idx < b->n_words; idx++) { int base =3D idx * IRQS_PER_WORD; - struct irq_chip_generic *gc =3D - irq_get_domain_generic_chip(b->domain, base); + struct irq_chip_generic *gc; unsigned long pending; int hwirq; =20 - irq_gc_lock(gc); - pending =3D irq_reg_readl(gc, b->stat_offset[idx]) & - gc->mask_cache & - data->irq_map_mask[idx]; - irq_gc_unlock(gc); + gc =3D irq_get_domain_generic_chip(b->domain, base); + scoped_guard (raw_spinlock, &gc->lock) { + pending =3D irq_reg_readl(gc, b->stat_offset[idx]) & gc->mask_cache & + data->irq_map_mask[idx]; + } =20 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) generic_handle_domain_irq(b->domain, base + hwirq); @@ -86,11 +85,9 @@ static void bcm7120_l2_intc_suspend(stru struct bcm7120_l2_intc_data *b =3D gc->private; struct irq_chip_type *ct =3D gc->chip_types; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); if (b->can_wake) - irq_reg_writel(gc, gc->mask_cache | gc->wake_active, - ct->regs.mask); - irq_gc_unlock(gc); + irq_reg_writel(gc, gc->mask_cache | gc->wake_active, ct->regs.mask); } =20 static void bcm7120_l2_intc_resume(struct irq_chip_generic *gc) @@ -98,9 +95,8 @@ static void bcm7120_l2_intc_resume(struc struct irq_chip_type *ct =3D gc->chip_types; =20 /* Restore the saved mask */ - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); irq_reg_writel(gc, gc->mask_cache, ct->regs.mask); - irq_gc_unlock(gc); } =20 static int bcm7120_l2_intc_init_one(struct device_node *dn, --- a/drivers/irqchip/irq-brcmstb-l2.c +++ b/drivers/irqchip/irq-brcmstb-l2.c @@ -97,9 +97,8 @@ static void __brcmstb_l2_intc_suspend(st struct irq_chip_generic *gc =3D irq_data_get_irq_chip_data(d); struct irq_chip_type *ct =3D irq_data_get_chip_type(d); struct brcmstb_l2_intc_data *b =3D gc->private; - unsigned long flags; =20 - irq_gc_lock_irqsave(gc, flags); + guard(raw_spinlock_irqsave)(&gc->lock); /* Save the current mask */ if (save) b->saved_mask =3D irq_reg_readl(gc, ct->regs.mask); @@ -109,7 +108,6 @@ static void __brcmstb_l2_intc_suspend(st irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable); irq_reg_writel(gc, gc->wake_active, ct->regs.enable); } - irq_gc_unlock_irqrestore(gc, flags); } =20 static void brcmstb_l2_intc_shutdown(struct irq_data *d) @@ -127,9 +125,8 @@ static void brcmstb_l2_intc_resume(struc struct irq_chip_generic *gc =3D irq_data_get_irq_chip_data(d); struct irq_chip_type *ct =3D irq_data_get_chip_type(d); struct brcmstb_l2_intc_data *b =3D gc->private; - unsigned long flags; =20 - irq_gc_lock_irqsave(gc, flags); + guard(raw_spinlock_irqsave)(&gc->lock); if (ct->chip.irq_ack) { /* Clear unmasked non-wakeup interrupts */ irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active, @@ -139,7 +136,6 @@ static void brcmstb_l2_intc_resume(struc /* Restore the saved mask */ irq_reg_writel(gc, b->saved_mask, ct->regs.disable); irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable); - irq_gc_unlock_irqrestore(gc, flags); } =20 static int __init brcmstb_l2_intc_of_init(struct device_node *np, --- a/drivers/irqchip/irq-csky-apb-intc.c +++ b/drivers/irqchip/irq-csky-apb-intc.c @@ -50,11 +50,10 @@ static void irq_ck_mask_set_bit(struct i unsigned long ifr =3D ct->regs.mask - 8; u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); *ct->mask_cache |=3D mask; irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); irq_reg_writel(gc, irq_reg_readl(gc, ifr) & ~mask, ifr); - irq_gc_unlock(gc); } =20 static void __init ck_set_gc(struct device_node *node, void __iomem *reg_b= ase, --- a/drivers/irqchip/irq-dw-apb-ictl.c +++ b/drivers/irqchip/irq-dw-apb-ictl.c @@ -101,10 +101,9 @@ static void dw_apb_ictl_resume(struct ir struct irq_chip_generic *gc =3D irq_data_get_irq_chip_data(d); struct irq_chip_type *ct =3D irq_data_get_chip_type(d); =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); writel_relaxed(~0, gc->reg_base + ct->regs.enable); writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask); - irq_gc_unlock(gc); } #else #define dw_apb_ictl_resume NULL --- a/drivers/irqchip/irq-ingenic-tcu.c +++ b/drivers/irqchip/irq-ingenic-tcu.c @@ -52,11 +52,10 @@ static void ingenic_tcu_gc_unmask_enable struct regmap *map =3D gc->private; u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); regmap_write(map, ct->regs.ack, mask); regmap_write(map, ct->regs.enable, mask); *ct->mask_cache |=3D mask; - irq_gc_unlock(gc); } =20 static void ingenic_tcu_gc_mask_disable_reg(struct irq_data *d) @@ -66,10 +65,9 @@ static void ingenic_tcu_gc_mask_disable_ struct regmap *map =3D gc->private; u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); regmap_write(map, ct->regs.disable, mask); *ct->mask_cache &=3D ~mask; - irq_gc_unlock(gc); } =20 static void ingenic_tcu_gc_mask_disable_reg_and_ack(struct irq_data *d) @@ -79,10 +77,9 @@ static void ingenic_tcu_gc_mask_disable_ struct regmap *map =3D gc->private; u32 mask =3D d->mask; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); regmap_write(map, ct->regs.ack, mask); regmap_write(map, ct->regs.disable, mask); - irq_gc_unlock(gc); } =20 static int __init ingenic_tcu_irq_init(struct device_node *np, --- a/drivers/irqchip/irq-lan966x-oic.c +++ b/drivers/irqchip/irq-lan966x-oic.c @@ -71,14 +71,12 @@ static unsigned int lan966x_oic_irq_star struct lan966x_oic_chip_regs *chip_regs =3D gc->private; u32 map; =20 - irq_gc_lock(gc); - - /* Map the source interrupt to the destination */ - map =3D irq_reg_readl(gc, chip_regs->reg_off_map); - map |=3D data->mask; - irq_reg_writel(gc, map, chip_regs->reg_off_map); - - irq_gc_unlock(gc); + scoped_guard (raw_spinlock, &gc->lock) { + /* Map the source interrupt to the destination */ + map =3D irq_reg_readl(gc, chip_regs->reg_off_map); + map |=3D data->mask; + irq_reg_writel(gc, map, chip_regs->reg_off_map); + } =20 ct->chip.irq_ack(data); ct->chip.irq_unmask(data); @@ -95,14 +93,12 @@ static void lan966x_oic_irq_shutdown(str =20 ct->chip.irq_mask(data); =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); =20 /* Unmap the interrupt */ map =3D irq_reg_readl(gc, chip_regs->reg_off_map); map &=3D ~data->mask; irq_reg_writel(gc, map, chip_regs->reg_off_map); - - irq_gc_unlock(gc); } =20 static int lan966x_oic_irq_set_type(struct irq_data *data, --- a/drivers/irqchip/irq-loongson-liointc.c +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -116,9 +116,8 @@ static int liointc_set_type(struct irq_d { struct irq_chip_generic *gc =3D irq_data_get_irq_chip_data(data); u32 mask =3D data->mask; - unsigned long flags; =20 - irq_gc_lock_irqsave(gc, flags); + guard(raw_spinlock)(&gc->lock); switch (type) { case IRQ_TYPE_LEVEL_HIGH: liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false); @@ -137,10 +136,8 @@ static int liointc_set_type(struct irq_d liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); break; default: - irq_gc_unlock_irqrestore(gc, flags); return -EINVAL; } - irq_gc_unlock_irqrestore(gc, flags); =20 irqd_set_trigger_type(data, type); return 0; @@ -157,10 +154,9 @@ static void liointc_suspend(struct irq_c static void liointc_resume(struct irq_chip_generic *gc) { struct liointc_priv *priv =3D gc->private; - unsigned long flags; int i; =20 - irq_gc_lock_irqsave(gc, flags); + guard(raw_spinlock_irqsave)(&gc->lock); /* Disable all at first */ writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE); /* Restore map cache */ @@ -170,7 +166,6 @@ static void liointc_resume(struct irq_ch writel(priv->int_edge, gc->reg_base + LIOINTC_REG_INTC_EDGE); /* Restore mask cache */ writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE); - irq_gc_unlock_irqrestore(gc, flags); } =20 static int parent_irq[LIOINTC_NUM_PARENT]; --- a/drivers/irqchip/irq-mscc-ocelot.c +++ b/drivers/irqchip/irq-mscc-ocelot.c @@ -83,7 +83,7 @@ static void ocelot_irq_unmask(struct irq unsigned int mask =3D data->mask; u32 val; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); /* * Clear sticky bits for edge mode interrupts. * Serval has only one trigger register replication, but the adjacent @@ -97,7 +97,6 @@ static void ocelot_irq_unmask(struct irq =20 *ct->mask_cache &=3D ~mask; irq_reg_writel(gc, mask, p->reg_off_ena_set); - irq_gc_unlock(gc); } =20 static void ocelot_irq_handler(struct irq_desc *desc) --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -169,22 +169,18 @@ static int stm32_irq_set_type(struct irq u32 rtsr, ftsr; int err; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); =20 rtsr =3D irq_reg_readl(gc, stm32_bank->rtsr_ofst); ftsr =3D irq_reg_readl(gc, stm32_bank->ftsr_ofst); =20 err =3D stm32_exti_set_type(d, type, &rtsr, &ftsr); if (err) - goto unlock; + return err; =20 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); - -unlock: - irq_gc_unlock(gc); - - return err; + return 0; } =20 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data, @@ -217,18 +213,16 @@ static void stm32_irq_suspend(struct irq { struct stm32_exti_chip_data *chip_data =3D gc->private; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); stm32_chip_suspend(chip_data, gc->wake_active); - irq_gc_unlock(gc); } =20 static void stm32_irq_resume(struct irq_chip_generic *gc) { struct stm32_exti_chip_data *chip_data =3D gc->private; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); stm32_chip_resume(chip_data, gc->mask_cache); - irq_gc_unlock(gc); } =20 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, @@ -265,11 +259,8 @@ static void stm32_irq_ack(struct irq_dat struct stm32_exti_chip_data *chip_data =3D gc->private; const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; =20 - irq_gc_lock(gc); - + guard(raw_spinlock)(&gc->lock); irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst); - - irq_gc_unlock(gc); } =20 static struct --- a/drivers/irqchip/irq-sunxi-nmi.c +++ b/drivers/irqchip/irq-sunxi-nmi.c @@ -102,7 +102,7 @@ static int sunxi_sc_nmi_set_type(struct unsigned int src_type; unsigned int i; =20 - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); =20 switch (flow_type & IRQF_TRIGGER_MASK) { case IRQ_TYPE_EDGE_FALLING: @@ -119,9 +119,7 @@ static int sunxi_sc_nmi_set_type(struct src_type =3D SUNXI_SRC_TYPE_LEVEL_LOW; break; default: - irq_gc_unlock(gc); - pr_err("Cannot assign multiple trigger modes to IRQ %d.\n", - data->irq); + pr_err("Cannot assign multiple trigger modes to IRQ %d.\n", data->irq); return -EBADR; } =20 @@ -136,9 +134,6 @@ static int sunxi_sc_nmi_set_type(struct src_type_reg &=3D ~SUNXI_NMI_SRC_TYPE_MASK; src_type_reg |=3D src_type; sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg); - - irq_gc_unlock(gc); - return IRQ_SET_MASK_OK; } =20 --- a/drivers/irqchip/irq-tb10x.c +++ b/drivers/irqchip/irq-tb10x.c @@ -41,11 +41,9 @@ static inline u32 ab_irqctl_readreg(stru static int tb10x_irq_set_type(struct irq_data *data, unsigned int flow_typ= e) { struct irq_chip_generic *gc =3D irq_data_get_irq_chip_data(data); - uint32_t im, mod, pol; + uint32_t mod, pol, im =3D data->mask; =20 - im =3D data->mask; - - irq_gc_lock(gc); + guard(raw_spinlock)(&gc->lock); =20 mod =3D ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) | im; pol =3D ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im; @@ -67,9 +65,7 @@ static int tb10x_irq_set_type(struct irq case IRQ_TYPE_EDGE_RISING: break; default: - irq_gc_unlock(gc); - pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n", - __func__, data->irq); + pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n", __func__= , data->irq); return -EBADR; } =20 @@ -79,9 +75,6 @@ static int tb10x_irq_set_type(struct irq ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod); ab_irqctl_writereg(gc, AB_IRQCTL_SRC_POLARITY, pol); ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, im); - - irq_gc_unlock(gc); - return IRQ_SET_MASK_OK; } From nobody Sun Feb 8 03:21:33 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0586D2690F2 for ; Thu, 13 Mar 2025 14:31:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741876292; cv=none; b=GfdP1Fuyu5cw7Kx0QMH+ZRPrw1fY51D+lefA64mhlRvEDwKKgqnpz418gP+WDVm2Rfh4n28ie45XSA26l0Q4BHsfkRi7rLO+FGd5ZUqPMh4Vrhpp9d+RNd5TnG5J7nugpnJbIbUb0WxmgA7clfEEZA886Adkb7d3rMGS1ANwaNU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741876292; c=relaxed/simple; bh=/n7UFatUWhhDG6gWk2aqwLzi8C71lUdmuy1s5219+V0=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=f+RHPWaMj+BkUt2szrW0GCHoKrqlJ4GcG8y3XOxrDwxLygyUODqKCt4ubki1c66822E1vTBQ/+yNqD1BkxgqRWJuF/afcs/LdnLW74I65tbRMrJJJ0aMjbRkG09FG0GSDcnurfeC5jD71LvVoCmch2IuO6PTsuPmDQZgsxjwFWg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=LcWs1qo/; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=z/AqjbRo; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="LcWs1qo/"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="z/AqjbRo" Message-ID: <20250313142524.388478168@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741876289; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=9K3rlwZ6R2wtcFYBYUF2pVbOdk2NEUcnH+sSO8N4g8k=; b=LcWs1qo/7WUfowKYc3icjlFFzgWCcLR6KXL+tDhu2X3UtOSVU2zJLhEesGT7xML6m5gkc+ rQdIhETQOv/tJesYFWAPSF3OlG6B5sBVxEFiOUqxJb2uNUD+LayuMPYwraf7bMNRPQq1pl aZPUniN3DMnNLsC/3C5HJE+TcVj7wBbp3XByY7ScZaSxmr7oe0YaRMjBEviv5HZV8UNmx/ Y44JF6vO2G8Ujdw8Ahnj9a0t5UNDyrtTq1w7ElQwmgKorn1WMkRYta03eYPG5XZUNHP3+d 2oZgPdo+5cW/9w4ws6/r6FZVfbwyie8lGrkOdXa+2+C/h0yZmfq6nEMp7MR6ew== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741876289; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=9K3rlwZ6R2wtcFYBYUF2pVbOdk2NEUcnH+sSO8N4g8k=; b=z/AqjbRoEdwztgh4byLUaTe9lyrxpbgumk8BtxfzdYH+EkjJ+g4PBYQbPkSp0CC58+BtMn bHFXWJ2IYWm0oKCA== From: Thomas Gleixner To: LKML Cc: Jiri Slaby , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Linus Walleij , Bartosz Golaszewski , Talel Shenhar , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Florian Fainelli , Guo Ren , Herve Codina , Huacai Chen , Jiaxun Yang , Maxime Coquelin , Alexandre Torgue , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Subject: [patch 7/7] genirq/generic-chip: Remove unused lock wrappers References: <20250313142404.896902416@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Thu, 13 Mar 2025 15:31:28 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All users are converted to lock guards. Signed-off-by: Thomas Gleixner --- include/linux/irq.h | 20 -------------------- 1 file changed, 20 deletions(-) --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -1219,26 +1219,6 @@ static inline struct irq_chip_type *irq_ =20 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) =20 -static inline void irq_gc_lock(struct irq_chip_generic *gc) -{ - raw_spin_lock(&gc->lock); -} - -static inline void irq_gc_unlock(struct irq_chip_generic *gc) -{ - raw_spin_unlock(&gc->lock); -} - -/* - * The irqsave variants are for usage in non interrupt code. Do not use - * them in irq_chip callbacks. Use irq_gc_lock() instead. - */ -#define irq_gc_lock_irqsave(gc, flags) \ - raw_spin_lock_irqsave(&(gc)->lock, flags) - -#define irq_gc_unlock_irqrestore(gc, flags) \ - raw_spin_unlock_irqrestore(&(gc)->lock, flags) - static inline void irq_reg_writel(struct irq_chip_generic *gc, u32 val, int reg_offset) {