From nobody Fri Dec 19 03:14:22 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FEB21FA164; Thu, 13 Mar 2025 05:17:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741843029; cv=none; b=ts5icf0XUaPmO8iIpHLHUfiGdZx4Pdgrw3aUV0F3xnA46ccud+tZwhcWCkL/v8R4ofvsBTTYI0s8Xcehkpo5OUaibSrWNHD3y6f1c97iHQAVgoK+2koiu1EHHq0hghAIEkap4FT8kPyFV90M3Iq+yJmDa4kmyB4X8NUOB9DwoHU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741843029; c=relaxed/simple; bh=sMnUF4P+QvolmJ6Mu/3KsiP8NQWgHD1+6HkW5E1Q3eU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WppNEeRWst7d1jf/AKJtRE9ajFNtSZDTjL9RCWs11IARNL+gSL6+AcWXEw4YH6JAuZ5CLBk3/FMEhh81hAXjI8wPu4E3zgT9meAds6uYFJYy0YWKcpxlu2tbxCGKowCyG6uKFngU1sXRjBu1DC0I7qb3qKvqjPsTtX8t7erMkhQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Tg0Qg/GY; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Tg0Qg/GY" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52D031DY003523; Thu, 13 Mar 2025 05:17:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to; s=qcppdkim1; bh=6X2FD+cgZIjMAfXzsNR5UvkK ZOy5HIgnUT7umMaDOtg=; b=Tg0Qg/GY/iY/byTe3qjBwgH32H0JL108+gy49dYp RkCVwbRFVAsMDd7CMJBKJBrtnBEtJCiz64LDOcbhnpsJppNwiuzWJy9mcIW2frtt /3yDoh4mrfbyI9wkfR2FuVMUL4jHGz2SDqISDVUq3vHarhZW9bCo1sRWcC6WtJxD Tk+3LrC2FnP31J9/kRFgzquCJIypIZdMK+qCl8y6xBj/gKPdqSLdoxFoATNxtsyp pAGhb2mlDBj70E73HCelmh6VH8+yf826iLCGjuxlq2/veCDML/Nir0B12Kbh6tXh 1OrtyjceAsujl1Zb9f/ITk2OmxZOY0iGfVTs6JYoN5cHZA== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45b96yag0m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Mar 2025 05:17:03 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52D5H3Tf003784 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Mar 2025 05:17:03 GMT Received: from hu-mapa-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 12 Mar 2025 22:17:00 -0700 From: Manish Pandey To: Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" CC: , , , , , Subject: [PATCH V3 1/3] scsi: ufs-qcom: Add support for dumping HW and SW hibern8 count Date: Thu, 13 Mar 2025 10:46:33 +0530 Message-ID: <20250313051635.22073-2-quic_mapa@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250313051635.22073-1-quic_mapa@quicinc.com> References: <20250313051635.22073-1-quic_mapa@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: NbuoeTZSEPC13ENJQU3Fnn3fcEHor5eP X-Authority-Analysis: v=2.4 cv=I+llRMgg c=1 sm=1 tr=0 ts=67d26a4f cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=MS9SOmDhS3Yx0VQUj3wA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: NbuoeTZSEPC13ENJQU3Fnn3fcEHor5eP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_02,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=799 lowpriorityscore=0 adultscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 spamscore=0 malwarescore=0 mlxscore=0 suspectscore=0 phishscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130039 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds functionality to dump both hardware and software hibern8 enter counts. This enhancement will aid in monitoring and debugging hibern8 state transitions by providing detailed count information. Signed-off-by: Manish Pandey --- drivers/ufs/host/ufs-qcom.c | 9 +++++++++ drivers/ufs/host/ufs-qcom.h | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 1b37449fbffc..f5181773c0e5 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1573,6 +1573,15 @@ static void ufs_qcom_dump_dbg_regs(struct ufs_hba *h= ba) =20 host =3D ufshcd_get_variant(hba); =20 + dev_err(hba->dev, "HW_H8_ENTER_CNT=3D%d\n", ufshcd_readl(hba, REG_UFS_HW_= H8_ENTER_CNT)); + dev_err(hba->dev, "HW_H8_EXIT_CNT=3D%d\n", ufshcd_readl(hba, REG_UFS_HW_H= 8_EXIT_CNT)); + + dev_err(hba->dev, "SW_H8_ENTER_CNT=3D%d\n", ufshcd_readl(hba, REG_UFS_SW_= H8_ENTER_CNT)); + dev_err(hba->dev, "SW_H8_EXIT_CNT=3D%d\n", ufshcd_readl(hba, REG_UFS_SW_H= 8_EXIT_CNT)); + + dev_err(hba->dev, "SW_AFTER_HW_H8_ENTER_CNT=3D%d\n", + ufshcd_readl(hba, REG_UFS_SW_AFTER_HW_H8_ENTER_CNT)); + ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, "HCI Vendor Specific Registers "); =20 diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index d0e6ec9128e7..a41db017009f 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -75,6 +75,15 @@ enum { UFS_UFS_DBG_RD_EDTL_RAM =3D 0x1900, }; =20 +/* Vendor-specific Hibern8 count registers for the QCOM UFS host controlle= r. */ +enum { + REG_UFS_HW_H8_ENTER_CNT =3D 0x2700, + REG_UFS_SW_H8_ENTER_CNT =3D 0x2704, + REG_UFS_SW_AFTER_HW_H8_ENTER_CNT =3D 0x2708, + REG_UFS_HW_H8_EXIT_CNT =3D 0x270C, + REG_UFS_SW_H8_EXIT_CNT =3D 0x2710, +}; + enum { UFS_MEM_CQIS_VS =3D 0x8, }; --=20 2.17.1