From nobody Wed Dec 17 22:45:37 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 215F619005D; Thu, 13 Mar 2025 19:30:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741894232; cv=none; b=G2prOf5w0mz4EqJLkKfUvWeOSQKht6tAivunjkgiqW81567nOEOfpJ831jhtgkYkuL3/M8771Q84nksFUgP09dcawJBTZFvlb4zXO0c4ZVDBfEokoHz0sTAMkOXmJURhdnPiDGhqlAa3OVW1rBbKSp93hMg0RYsmY7hMxm9XH3E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741894232; c=relaxed/simple; bh=N5Oxz1gvys/HGlscRpkT4sgkdpKYAMquiyHmxv5/Wjs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dhVt3+XBWkdt0hOtSvhG3bxomUjVdGOsO8zveJPa7IHiBrXSpCrS43crbb3kWvGCVogTRnrOoPSPicZJx7mhDE59y9kbhQzSc1O+zPLpvd0x1l+08jalIaSLe7uXErRnoAP96OKOsAT3rCBbjYrvQCiJ3A7qKrWW7qEqERu2kYQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DRzPNAe1; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DRzPNAe1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741894230; x=1773430230; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=N5Oxz1gvys/HGlscRpkT4sgkdpKYAMquiyHmxv5/Wjs=; b=DRzPNAe13E1hGEIciH/TxMAeAXnMFBhSlEr62Wg+BfnECeNjBiEmzx8N 8vdreuoBVUWOsAUxBaIIeNPjDp+6Y6C9y6IYV31hVTeTOghO6mouIdB+E F/GtMxs5T8TaYrlaphVkIEBHOGaasMJABd9mtt3exERHczpJOchIGmk5t O+Ouj3QUjJ9auth6Da2bP4AUo12qzEKH/qEpGycmq3ri/PM4/4N63R5yo KERTxpDbsttjcudLrLZ81eL51UI10Bj438FtYHG84tDYSu7Gk8EAAQkGE cVwD4qsUt87E/UlWzsRjA9/MTtBuOu6LoKhQY5ughWOkhpgmCAlhjk4mH w==; X-CSE-ConnectionGUID: F516d4IkS+WKuusstZgT8g== X-CSE-MsgGUID: C8AUlJzwSsGDjs+ExCEGMw== X-IronPort-AV: E=McAfee;i="6700,10204,11372"; a="43237115" X-IronPort-AV: E=Sophos;i="6.14,245,1736841600"; d="scan'208";a="43237115" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2025 12:30:29 -0700 X-CSE-ConnectionGUID: mFkpxdivS6urpwhADcA/hQ== X-CSE-MsgGUID: 3LMCxcmrS12V3FuzAuVPNw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,245,1736841600"; d="scan'208";a="151988215" Received: from vverma7-desk1.amr.corp.intel.com (HELO [192.168.1.200]) ([10.125.108.107]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2025 12:30:28 -0700 From: Vishal Verma Date: Thu, 13 Mar 2025 13:30:01 -0600 Subject: [PATCH 1/4] KVM: TDX: Move apicv_pre_state_restore to posted_intr.c Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250313-vverma7-cleanup_x86_ops-v1-1-0346c8211a0c@intel.com> References: <20250313-vverma7-cleanup_x86_ops-v1-0-0346c8211a0c@intel.com> In-Reply-To: <20250313-vverma7-cleanup_x86_ops-v1-0-0346c8211a0c@intel.com> To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Rick Edgecombe , Vishal Verma X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2963; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=N5Oxz1gvys/HGlscRpkT4sgkdpKYAMquiyHmxv5/Wjs=; b=owGbwMvMwCXGf25diOft7jLG02pJDOmXjYIVl1WXefe2zXziFfhU/vfKTVOOros9mn1G6tmXg PJ/LBlSHaUsDGJcDLJiiix/93xkPCa3PZ8nMMERZg4rE8gQBi5OAZgIxzxGhjU977IX3wp5xHrt gkam/MYXczYVPnxnpv7i3aWVTPETHtQwMrQkX9gx4/3iqHx9m5w1179t+9EyXcx2btCTVOGVMb1 ql9kB X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF In preparation for a cleanup of the x86_ops struct for TDX, which turns several of the ops definitions to macros, move the vt_apicv_pre_state_restore() helper into posted_intr.c. Based on a patch by Sean Christopherson Link: https://lore.kernel.org/kvm/Z6v9yjWLNTU6X90d@google.com/ Cc: Sean Christopherson Cc: Rick Edgecombe Signed-off-by: Vishal Verma Reviewed-by: Binbin Wu --- arch/x86/kvm/vmx/posted_intr.h | 1 + arch/x86/kvm/vmx/main.c | 10 +--------- arch/x86/kvm/vmx/posted_intr.c | 8 ++++++++ 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/x86/kvm/vmx/posted_intr.h b/arch/x86/kvm/vmx/posted_intr.h index 68605ca7ef68..9d0677a2ba0e 100644 --- a/arch/x86/kvm/vmx/posted_intr.h +++ b/arch/x86/kvm/vmx/posted_intr.h @@ -11,6 +11,7 @@ void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu); void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu); void pi_wakeup_handler(void); void __init pi_init_cpu(int cpu); +void pi_apicv_pre_state_restore(struct kvm_vcpu *vcpu); bool pi_has_pending_interrupt(struct kvm_vcpu *vcpu); int vmx_pi_update_irte(struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, bool set); diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index 320c96e1e80a..9d201ddb794a 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -315,14 +315,6 @@ static void vt_set_virtual_apic_mode(struct kvm_vcpu *= vcpu) return vmx_set_virtual_apic_mode(vcpu); } =20 -static void vt_apicv_pre_state_restore(struct kvm_vcpu *vcpu) -{ - struct pi_desc *pi =3D vcpu_to_pi_desc(vcpu); - - pi_clear_on(pi); - memset(pi->pir, 0, sizeof(pi->pir)); -} - static void vt_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) { if (is_td_vcpu(vcpu)) @@ -983,7 +975,7 @@ struct kvm_x86_ops vt_x86_ops __initdata =3D { .set_apic_access_page_addr =3D vt_set_apic_access_page_addr, .refresh_apicv_exec_ctrl =3D vt_refresh_apicv_exec_ctrl, .load_eoi_exitmap =3D vt_load_eoi_exitmap, - .apicv_pre_state_restore =3D vt_apicv_pre_state_restore, + .apicv_pre_state_restore =3D pi_apicv_pre_state_restore, .required_apicv_inhibits =3D VMX_REQUIRED_APICV_INHIBITS, .hwapic_isr_update =3D vt_hwapic_isr_update, .sync_pir_to_irr =3D vt_sync_pir_to_irr, diff --git a/arch/x86/kvm/vmx/posted_intr.c b/arch/x86/kvm/vmx/posted_intr.c index f2ca37b3f606..a140af060bb8 100644 --- a/arch/x86/kvm/vmx/posted_intr.c +++ b/arch/x86/kvm/vmx/posted_intr.c @@ -241,6 +241,14 @@ void __init pi_init_cpu(int cpu) raw_spin_lock_init(&per_cpu(wakeup_vcpus_on_cpu_lock, cpu)); } =20 +void pi_apicv_pre_state_restore(struct kvm_vcpu *vcpu) +{ + struct pi_desc *pi =3D vcpu_to_pi_desc(vcpu); + + pi_clear_on(pi); + memset(pi->pir, 0, sizeof(pi->pir)); +} + bool pi_has_pending_interrupt(struct kvm_vcpu *vcpu) { struct pi_desc *pi_desc =3D vcpu_to_pi_desc(vcpu); --=20 2.48.1 From nobody Wed Dec 17 22:45:37 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E87141EEA27; Thu, 13 Mar 2025 19:30:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741894233; cv=none; b=AFqpgdzsHsWiAy/CBUa9RNhrk/gTgcZ3Xi0jCoIvzmaT3t/l287nAiPytxo8k2/niSr03exN6cg8GtPFHcCZM7QZgBtPyXBLhbftGMC41ansaQGxM0dhgBPHCArmKeCeCcCVB939wO8N0JUOtcsAoE4XjU6aLVrqD0uZ5rO7MfM= ARC-Message-Signature: i=1; a=rsa-sha256; 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d="scan'208";a="151988219" Received: from vverma7-desk1.amr.corp.intel.com (HELO [192.168.1.200]) ([10.125.108.107]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2025 12:30:28 -0700 From: Vishal Verma Date: Thu, 13 Mar 2025 13:30:02 -0600 Subject: [PATCH 2/4] KVM: VMX: Move x86_ops wrappers under CONFIG_KVM_INTEL_TDX Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250313-vverma7-cleanup_x86_ops-v1-2-0346c8211a0c@intel.com> References: <20250313-vverma7-cleanup_x86_ops-v1-0-0346c8211a0c@intel.com> In-Reply-To: <20250313-vverma7-cleanup_x86_ops-v1-0-0346c8211a0c@intel.com> To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Rick Edgecombe , Vishal Verma X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2224; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=STDnxg5RnvsGQfGEYHRsm51VOKb1VgyKotoO/k6K7PM=; b=owGbwMvMwCXGf25diOft7jLG02pJDOmXjYJFJpqarPVuVN98WNJ46j3O2Ysf1PtfX5Sw/97Pr 44S1ueUOkpZGMS4GGTFFFn+7vnIeExuez5PYIIjzBxWJpAhDFycAjCRbd8Z/lnr/Pu9ImDV9U4P jyd9Z3nNmxfHGnceKVC7voS19TyvShgjw9Rvc28USUwss53gUb+xadb8SGveCUs2TX68z71eV1P dghMA X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Rather than have a lot of stubs for x86_ops helpers, simply omit the wrappers when CONFIG_KVM_INTEL_TDX=3Dn. This allows nearly all of vmx/main.c to go under a single #ifdef. That eliminates all the trampolines in the generated code, and almost all of the stubs. Based on a patch by Sean Christopherson Link: https://lore.kernel.org/kvm/Z6v9yjWLNTU6X90d@google.com/ Cc: Sean Christopherson Cc: Rick Edgecombe Signed-off-by: Vishal Verma --- arch/x86/kvm/vmx/tdx.h | 2 +- arch/x86/kvm/vmx/x86_ops.h | 2 +- arch/x86/kvm/vmx/main.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/vmx/tdx.h b/arch/x86/kvm/vmx/tdx.h index 8f8070d0f55e..b43d7a7c8f1c 100644 --- a/arch/x86/kvm/vmx/tdx.h +++ b/arch/x86/kvm/vmx/tdx.h @@ -5,7 +5,7 @@ #include "tdx_arch.h" #include "tdx_errno.h" =20 -#ifdef CONFIG_INTEL_TDX_HOST +#ifdef CONFIG_KVM_INTEL_TDX #include "common.h" =20 int tdx_bringup(void); diff --git a/arch/x86/kvm/vmx/x86_ops.h b/arch/x86/kvm/vmx/x86_ops.h index 19f770b0fc81..4704bed033b1 100644 --- a/arch/x86/kvm/vmx/x86_ops.h +++ b/arch/x86/kvm/vmx/x86_ops.h @@ -121,7 +121,7 @@ void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu); #endif void vmx_setup_mce(struct kvm_vcpu *vcpu); =20 -#ifdef CONFIG_INTEL_TDX_HOST +#ifdef CONFIG_KVM_INTEL_TDX void tdx_disable_virtualization_cpu(void); int tdx_vm_init(struct kvm *kvm); void tdx_mmu_release_hkid(struct kvm *kvm); diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index 9d201ddb794a..ccb81a8b73f7 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -10,9 +10,8 @@ #include "tdx.h" #include "tdx_arch.h" =20 -#ifdef CONFIG_INTEL_TDX_HOST +#ifdef CONFIG_KVM_INTEL_TDX static_assert(offsetof(struct vcpu_vmx, vt) =3D=3D offsetof(struct vcpu_td= x, vt)); -#endif =20 static void vt_disable_virtualization_cpu(void) { @@ -879,6 +878,7 @@ static int vt_gmem_private_max_mapping_level(struct kvm= *kvm, kvm_pfn_t pfn) =20 return 0; } +#endif =20 #define VMX_REQUIRED_APICV_INHIBITS \ (BIT(APICV_INHIBIT_REASON_DISABLED) | \ --=20 2.48.1 From nobody Wed Dec 17 22:45:37 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BCF71F30A8; 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a="43237121" X-IronPort-AV: E=Sophos;i="6.14,245,1736841600"; d="scan'208";a="43237121" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2025 12:30:29 -0700 X-CSE-ConnectionGUID: KaUv7VIzR8aJuhVL1P/8eg== X-CSE-MsgGUID: oz3+vXOqQgiZnbWkz0qpag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,245,1736841600"; d="scan'208";a="151988222" Received: from vverma7-desk1.amr.corp.intel.com (HELO [192.168.1.200]) ([10.125.108.107]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2025 12:30:29 -0700 From: Vishal Verma Date: Thu, 13 Mar 2025 13:30:03 -0600 Subject: [PATCH 3/4] KVM: VMX: Make naming consistent for kvm_complete_insn_gp via define Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250313-vverma7-cleanup_x86_ops-v1-3-0346c8211a0c@intel.com> References: <20250313-vverma7-cleanup_x86_ops-v1-0-0346c8211a0c@intel.com> In-Reply-To: <20250313-vverma7-cleanup_x86_ops-v1-0-0346c8211a0c@intel.com> To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Rick Edgecombe , Vishal Verma X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1817; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=R/nwEuUO6VXcXYOWii2gV/kZVgWoprf8O+FmFkrqFuI=; b=owGbwMvMwCXGf25diOft7jLG02pJDOmXjYL5P7vvvGkZkv2k7KtwWfU8n5R4t8L+RxzhZ2MPJ tsayx7oKGVhEONikBVTZPm75yPjMbnt+TyBCY4wc1iZQIYwcHEKwEQWLWf4zeJdO3mW9dffB/9U dctd39sxt+VEtaUR85wEYb2PPFEsJxgZjm72Wdx7fEGB0403XtMKOPTbF/A/dIzLitz9+srazZJ 8TAA= X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF In preparation for defining x86_ops using macros, make the naming of kvm_complete_insn_gp() in the non TDX case more consistent with other vmx_ops - i.e. use a #define to allow it to be referred as vmx_complete_emulated_msr(). Based on a patch by Sean Christopherson Link: https://lore.kernel.org/kvm/Z6v9yjWLNTU6X90d@google.com/ Cc: Sean Christopherson Cc: Rick Edgecombe Signed-off-by: Vishal Verma --- arch/x86/kvm/vmx/x86_ops.h | 1 + arch/x86/kvm/vmx/main.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/x86_ops.h b/arch/x86/kvm/vmx/x86_ops.h index 4704bed033b1..112dabce83aa 100644 --- a/arch/x86/kvm/vmx/x86_ops.h +++ b/arch/x86/kvm/vmx/x86_ops.h @@ -58,6 +58,7 @@ void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu); void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu); int vmx_get_feature_msr(u32 msr, u64 *data); int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info); +#define vmx_complete_emulated_msr kvm_complete_insn_gp u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg); void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int s= eg); void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int s= eg); diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index ccb81a8b73f7..e46005c81e5f 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -239,7 +239,7 @@ static int vt_complete_emulated_msr(struct kvm_vcpu *vc= pu, int err) if (is_td_vcpu(vcpu)) return tdx_complete_emulated_msr(vcpu, err); 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13 Mar 2025 12:30:29 -0700 From: Vishal Verma Date: Thu, 13 Mar 2025 13:30:04 -0600 Subject: [PATCH 4/4] KVM: VMX: Clean up and macrofy x86_ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250313-vverma7-cleanup_x86_ops-v1-4-0346c8211a0c@intel.com> References: <20250313-vverma7-cleanup_x86_ops-v1-0-0346c8211a0c@intel.com> In-Reply-To: <20250313-vverma7-cleanup_x86_ops-v1-0-0346c8211a0c@intel.com> To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Rick Edgecombe , Vishal Verma X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=14593; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=m9pFossgCGcXjpcoSyY9EZnbRwOUVVstdwWOxCL3+AI=; b=owGbwMvMwCXGf25diOft7jLG02pJDOmXjYIt1wRHtN2qErMPZalyuyWSZ39jpej0O5EHFijPb zp1RepfRykLgxgXg6yYIsvfPR8Zj8ltz+cJTHCEmcPKBDKEgYtTACbioMLI8PbIL5eVn99pnt36 45393j7nhrCNR5oc65w+b8pOSjE5uJCRoVH8K8eLnjdKOYynl9Y6f019Jpn+I/Js89yayFtGcmk vWAA= X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Eliminate a lot of stub definitions by using macros to define the TDX vs non-TDX versions of various x86_ops. This also allows nearly all of vmx/main.c to go under a single #ifdef, eliminating trampolines in the generated code, and almost all of the stubs. For example, with CONFIG_KVM_INTEL_TDX=3Dn, before this cleanup, vt_refresh_apicv_exec_ctrl() would produce: 0000000000036490 : 36490: f3 0f 1e fa endbr64 36494: e8 00 00 00 00 call 36499 36495: R_X86_64_PLT32 __fentry__-0x4 36499: e9 00 00 00 00 jmp 3649e 3649a: R_X86_64_PLT32 vmx_refresh_apicv_exec_ctrl= -0x4 3649e: 66 90 xchg %ax,%ax After this patch, this is completely eliminated. Based on a patch by Sean Christopherson Link: https://lore.kernel.org/kvm/Z6v9yjWLNTU6X90d@google.com/ Cc: Sean Christopherson Cc: Rick Edgecombe Signed-off-by: Vishal Verma --- arch/x86/kvm/vmx/x86_ops.h | 65 ---------------- arch/x86/kvm/vmx/main.c | 190 +++++++++++++++++++++++------------------= ---- 2 files changed, 98 insertions(+), 157 deletions(-) diff --git a/arch/x86/kvm/vmx/x86_ops.h b/arch/x86/kvm/vmx/x86_ops.h index 112dabce83aa..e628318fc3fc 100644 --- a/arch/x86/kvm/vmx/x86_ops.h +++ b/arch/x86/kvm/vmx/x86_ops.h @@ -165,71 +165,6 @@ void tdx_flush_tlb_current(struct kvm_vcpu *vcpu); void tdx_flush_tlb_all(struct kvm_vcpu *vcpu); void tdx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_leve= l); int tdx_gmem_private_max_mapping_level(struct kvm *kvm, kvm_pfn_t pfn); -#else -static inline void tdx_disable_virtualization_cpu(void) {} -static inline int tdx_vm_init(struct kvm *kvm) { return -EOPNOTSUPP; } -static inline void tdx_mmu_release_hkid(struct kvm *kvm) {} -static inline void tdx_vm_destroy(struct kvm *kvm) {} -static inline int tdx_vm_ioctl(struct kvm *kvm, void __user *argp) { retur= n -EOPNOTSUPP; } - -static inline int tdx_vcpu_create(struct kvm_vcpu *vcpu) { return -EOPNOTS= UPP; } -static inline void tdx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) = {} -static inline void tdx_vcpu_free(struct kvm_vcpu *vcpu) {} -static inline void tdx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) {} -static inline int tdx_vcpu_pre_run(struct kvm_vcpu *vcpu) { return -EOPNOT= SUPP; } -static inline fastpath_t tdx_vcpu_run(struct kvm_vcpu *vcpu, bool force_im= mediate_exit) -{ - return EXIT_FASTPATH_NONE; -} -static inline void tdx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) {} -static inline void tdx_vcpu_put(struct kvm_vcpu *vcpu) {} -static inline bool tdx_protected_apic_has_interrupt(struct kvm_vcpu *vcpu)= { return false; } -static inline int tdx_handle_exit(struct kvm_vcpu *vcpu, - enum exit_fastpath_completion fastpath) { return 0; } - -static inline void tdx_deliver_interrupt(struct kvm_lapic *apic, int deliv= ery_mode, - int trig_mode, int vector) {} -static inline void tdx_inject_nmi(struct kvm_vcpu *vcpu) {} -static inline void tdx_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason, u= 64 *info1, - u64 *info2, u32 *intr_info, u32 *error_code) {} -static inline bool tdx_has_emulated_msr(u32 index) { return false; } -static inline int tdx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)= { return 1; } -static inline int tdx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)= { return 1; } - -static inline int tdx_vcpu_ioctl(struct kvm_vcpu *vcpu, void __user *argp)= { return -EOPNOTSUPP; } - -static inline int tdx_sept_link_private_spt(struct kvm *kvm, gfn_t gfn, - enum pg_level level, - void *private_spt) -{ - return -EOPNOTSUPP; -} - -static inline int tdx_sept_free_private_spt(struct kvm *kvm, gfn_t gfn, - enum pg_level level, - void *private_spt) -{ - return -EOPNOTSUPP; -} - -static inline int tdx_sept_set_private_spte(struct kvm *kvm, gfn_t gfn, - enum pg_level level, - kvm_pfn_t pfn) -{ - return -EOPNOTSUPP; -} - -static inline int tdx_sept_remove_private_spte(struct kvm *kvm, gfn_t gfn, - enum pg_level level, - kvm_pfn_t pfn) -{ - return -EOPNOTSUPP; -} - -static inline void tdx_flush_tlb_current(struct kvm_vcpu *vcpu) {} -static inline void tdx_flush_tlb_all(struct kvm_vcpu *vcpu) {} -static inline void tdx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,= int root_level) {} -static inline int tdx_gmem_private_max_mapping_level(struct kvm *kvm, kvm_= pfn_t pfn) { return 0; } #endif =20 #endif /* __KVM_X86_VMX_X86_OPS_H */ diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index e46005c81e5f..218078ba039f 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -878,7 +878,13 @@ static int vt_gmem_private_max_mapping_level(struct kv= m *kvm, kvm_pfn_t pfn) =20 return 0; } -#endif + +#define vt_op(name) vt_##name +#define vt_op_tdx_only(name) vt_##name +#else /* CONFIG_KVM_INTEL_TDX */ +#define vt_op(name) vmx_##name +#define vt_op_tdx_only(name) NULL +#endif /* CONFIG_KVM_INTEL_TDX */ =20 #define VMX_REQUIRED_APICV_INHIBITS \ (BIT(APICV_INHIBIT_REASON_DISABLED) | \ @@ -897,113 +903,113 @@ struct kvm_x86_ops vt_x86_ops __initdata =3D { .hardware_unsetup =3D vmx_hardware_unsetup, =20 .enable_virtualization_cpu =3D vmx_enable_virtualization_cpu, - .disable_virtualization_cpu =3D vt_disable_virtualization_cpu, + .disable_virtualization_cpu =3D vt_op(disable_virtualization_cpu), .emergency_disable_virtualization_cpu =3D vmx_emergency_disable_virtualiz= ation_cpu, =20 - .has_emulated_msr =3D vt_has_emulated_msr, + .has_emulated_msr =3D vt_op(has_emulated_msr), =20 .vm_size =3D sizeof(struct kvm_vmx), =20 - .vm_init =3D vt_vm_init, - .vm_pre_destroy =3D vt_vm_pre_destroy, - .vm_destroy =3D vt_vm_destroy, + .vm_init =3D vt_op(vm_init), + .vm_destroy =3D vt_op(vm_destroy), + .vm_pre_destroy =3D vt_op_tdx_only(vm_pre_destroy), =20 - .vcpu_precreate =3D vt_vcpu_precreate, - .vcpu_create =3D vt_vcpu_create, - .vcpu_free =3D vt_vcpu_free, - .vcpu_reset =3D vt_vcpu_reset, + .vcpu_precreate =3D vt_op(vcpu_precreate), + .vcpu_create =3D vt_op(vcpu_create), + .vcpu_free =3D vt_op(vcpu_free), + .vcpu_reset =3D vt_op(vcpu_reset), =20 - .prepare_switch_to_guest =3D vt_prepare_switch_to_guest, - .vcpu_load =3D vt_vcpu_load, - .vcpu_put =3D vt_vcpu_put, + .prepare_switch_to_guest =3D vt_op(prepare_switch_to_guest), + .vcpu_load =3D vt_op(vcpu_load), + .vcpu_put =3D vt_op(vcpu_put), =20 - .update_exception_bitmap =3D vt_update_exception_bitmap, + .update_exception_bitmap =3D vt_op(update_exception_bitmap), .get_feature_msr =3D vmx_get_feature_msr, - .get_msr =3D vt_get_msr, - .set_msr =3D vt_set_msr, + .get_msr =3D vt_op(get_msr), + .set_msr =3D vt_op(set_msr), =20 - .get_segment_base =3D vt_get_segment_base, - .get_segment =3D vt_get_segment, - .set_segment =3D vt_set_segment, - .get_cpl =3D vt_get_cpl, - .get_cpl_no_cache =3D vt_get_cpl_no_cache, - .get_cs_db_l_bits =3D vt_get_cs_db_l_bits, - .is_valid_cr0 =3D vt_is_valid_cr0, - .set_cr0 =3D vt_set_cr0, - .is_valid_cr4 =3D vt_is_valid_cr4, - .set_cr4 =3D vt_set_cr4, - .set_efer =3D vt_set_efer, - .get_idt =3D vt_get_idt, - .set_idt =3D vt_set_idt, - .get_gdt =3D vt_get_gdt, - .set_gdt =3D vt_set_gdt, - .set_dr6 =3D vt_set_dr6, - .set_dr7 =3D vt_set_dr7, - .sync_dirty_debug_regs =3D vt_sync_dirty_debug_regs, - .cache_reg =3D vt_cache_reg, - .get_rflags =3D vt_get_rflags, - .set_rflags =3D vt_set_rflags, - .get_if_flag =3D vt_get_if_flag, + .get_segment_base =3D vt_op(get_segment_base), + .get_segment =3D vt_op(get_segment), + .set_segment =3D vt_op(set_segment), + .get_cpl =3D vt_op(get_cpl), + .get_cpl_no_cache =3D vt_op(get_cpl_no_cache), + .get_cs_db_l_bits =3D vt_op(get_cs_db_l_bits), + .is_valid_cr0 =3D vt_op(is_valid_cr0), + .set_cr0 =3D vt_op(set_cr0), + .is_valid_cr4 =3D vt_op(is_valid_cr4), + .set_cr4 =3D vt_op(set_cr4), + .set_efer =3D vt_op(set_efer), + .get_idt =3D vt_op(get_idt), + .set_idt =3D vt_op(set_idt), + .get_gdt =3D vt_op(get_gdt), + .set_gdt =3D vt_op(set_gdt), + .set_dr6 =3D vt_op(set_dr6), + .set_dr7 =3D vt_op(set_dr7), + .sync_dirty_debug_regs =3D vt_op(sync_dirty_debug_regs), + .cache_reg =3D vt_op(cache_reg), + .get_rflags =3D vt_op(get_rflags), + .set_rflags =3D vt_op(set_rflags), + .get_if_flag =3D vt_op(get_if_flag), =20 - .flush_tlb_all =3D vt_flush_tlb_all, - .flush_tlb_current =3D vt_flush_tlb_current, - .flush_tlb_gva =3D vt_flush_tlb_gva, - .flush_tlb_guest =3D vt_flush_tlb_guest, + .flush_tlb_all =3D vt_op(flush_tlb_all), + .flush_tlb_current =3D vt_op(flush_tlb_current), + .flush_tlb_gva =3D vt_op(flush_tlb_gva), + .flush_tlb_guest =3D vt_op(flush_tlb_guest), =20 - .vcpu_pre_run =3D vt_vcpu_pre_run, - .vcpu_run =3D vt_vcpu_run, - .handle_exit =3D vt_handle_exit, + .vcpu_pre_run =3D vt_op(vcpu_pre_run), + .vcpu_run =3D vt_op(vcpu_run), + .handle_exit =3D vt_op(handle_exit), .skip_emulated_instruction =3D vmx_skip_emulated_instruction, .update_emulated_instruction =3D vmx_update_emulated_instruction, - .set_interrupt_shadow =3D vt_set_interrupt_shadow, - .get_interrupt_shadow =3D vt_get_interrupt_shadow, - .patch_hypercall =3D vt_patch_hypercall, - .inject_irq =3D vt_inject_irq, - .inject_nmi =3D vt_inject_nmi, - .inject_exception =3D vt_inject_exception, - .cancel_injection =3D vt_cancel_injection, - .interrupt_allowed =3D vt_interrupt_allowed, - .nmi_allowed =3D vt_nmi_allowed, - .get_nmi_mask =3D vt_get_nmi_mask, - .set_nmi_mask =3D vt_set_nmi_mask, - .enable_nmi_window =3D vt_enable_nmi_window, - .enable_irq_window =3D vt_enable_irq_window, - .update_cr8_intercept =3D vt_update_cr8_intercept, + .set_interrupt_shadow =3D vt_op(set_interrupt_shadow), + .get_interrupt_shadow =3D vt_op(get_interrupt_shadow), + .patch_hypercall =3D vt_op(patch_hypercall), + .inject_irq =3D vt_op(inject_irq), + .inject_nmi =3D vt_op(inject_nmi), + .inject_exception =3D vt_op(inject_exception), + .cancel_injection =3D vt_op(cancel_injection), + .interrupt_allowed =3D vt_op(interrupt_allowed), + .nmi_allowed =3D vt_op(nmi_allowed), + .get_nmi_mask =3D vt_op(get_nmi_mask), + .set_nmi_mask =3D vt_op(set_nmi_mask), + .enable_nmi_window =3D vt_op(enable_nmi_window), + .enable_irq_window =3D vt_op(enable_irq_window), + .update_cr8_intercept =3D vt_op(update_cr8_intercept), =20 .x2apic_icr_is_split =3D false, - .set_virtual_apic_mode =3D vt_set_virtual_apic_mode, - .set_apic_access_page_addr =3D vt_set_apic_access_page_addr, - .refresh_apicv_exec_ctrl =3D vt_refresh_apicv_exec_ctrl, - .load_eoi_exitmap =3D vt_load_eoi_exitmap, + .set_virtual_apic_mode =3D vt_op(set_virtual_apic_mode), + .set_apic_access_page_addr =3D vt_op(set_apic_access_page_addr), + .refresh_apicv_exec_ctrl =3D vt_op(refresh_apicv_exec_ctrl), + .load_eoi_exitmap =3D vt_op(load_eoi_exitmap), .apicv_pre_state_restore =3D pi_apicv_pre_state_restore, .required_apicv_inhibits =3D VMX_REQUIRED_APICV_INHIBITS, - .hwapic_isr_update =3D vt_hwapic_isr_update, - .sync_pir_to_irr =3D vt_sync_pir_to_irr, - .deliver_interrupt =3D vt_deliver_interrupt, + .hwapic_isr_update =3D vt_op(hwapic_isr_update), + .sync_pir_to_irr =3D vt_op(sync_pir_to_irr), + .deliver_interrupt =3D vt_op(deliver_interrupt), .dy_apicv_has_pending_interrupt =3D pi_has_pending_interrupt, =20 - .set_tss_addr =3D vt_set_tss_addr, - .set_identity_map_addr =3D vt_set_identity_map_addr, + .set_tss_addr =3D vt_op(set_tss_addr), + .set_identity_map_addr =3D vt_op(set_identity_map_addr), .get_mt_mask =3D vmx_get_mt_mask, =20 - .get_exit_info =3D vt_get_exit_info, - .get_entry_info =3D vt_get_entry_info, + .get_exit_info =3D vt_op(get_exit_info), + .get_entry_info =3D vt_op(get_entry_info), =20 - .vcpu_after_set_cpuid =3D vt_vcpu_after_set_cpuid, + .vcpu_after_set_cpuid =3D vt_op(vcpu_after_set_cpuid), =20 .has_wbinvd_exit =3D cpu_has_vmx_wbinvd_exit, =20 - .get_l2_tsc_offset =3D vt_get_l2_tsc_offset, - .get_l2_tsc_multiplier =3D vt_get_l2_tsc_multiplier, - .write_tsc_offset =3D vt_write_tsc_offset, - .write_tsc_multiplier =3D vt_write_tsc_multiplier, + .get_l2_tsc_offset =3D vt_op(get_l2_tsc_offset), + .get_l2_tsc_multiplier =3D vt_op(get_l2_tsc_multiplier), + .write_tsc_offset =3D vt_op(write_tsc_offset), + .write_tsc_multiplier =3D vt_op(write_tsc_multiplier), =20 - .load_mmu_pgd =3D vt_load_mmu_pgd, + .load_mmu_pgd =3D vt_op(load_mmu_pgd), =20 .check_intercept =3D vmx_check_intercept, .handle_exit_irqoff =3D vmx_handle_exit_irqoff, =20 - .update_cpu_dirty_logging =3D vt_update_cpu_dirty_logging, + .update_cpu_dirty_logging =3D vt_op(update_cpu_dirty_logging), =20 .nested_ops =3D &vmx_nested_ops, =20 @@ -1011,38 +1017,38 @@ struct kvm_x86_ops vt_x86_ops __initdata =3D { .pi_start_assignment =3D vmx_pi_start_assignment, =20 #ifdef CONFIG_X86_64 - .set_hv_timer =3D vt_set_hv_timer, - .cancel_hv_timer =3D vt_cancel_hv_timer, + .set_hv_timer =3D vt_op(set_hv_timer), + .cancel_hv_timer =3D vt_op(cancel_hv_timer), #endif =20 - .setup_mce =3D vt_setup_mce, + .setup_mce =3D vt_op(setup_mce), =20 #ifdef CONFIG_KVM_SMM - .smi_allowed =3D vt_smi_allowed, - .enter_smm =3D vt_enter_smm, - .leave_smm =3D vt_leave_smm, - .enable_smi_window =3D vt_enable_smi_window, + .smi_allowed =3D vt_op(smi_allowed), + .enter_smm =3D vt_op(enter_smm), + .leave_smm =3D vt_op(leave_smm), + .enable_smi_window =3D vt_op(enable_smi_window), #endif =20 - .check_emulate_instruction =3D vt_check_emulate_instruction, - .apic_init_signal_blocked =3D vt_apic_init_signal_blocked, + .check_emulate_instruction =3D vt_op(check_emulate_instruction), + .apic_init_signal_blocked =3D vt_op(apic_init_signal_blocked), .migrate_timers =3D vmx_migrate_timers, =20 - .msr_filter_changed =3D vt_msr_filter_changed, - .complete_emulated_msr =3D vt_complete_emulated_msr, + .msr_filter_changed =3D vt_op(msr_filter_changed), + .complete_emulated_msr =3D vt_op(complete_emulated_msr), =20 .vcpu_deliver_sipi_vector =3D kvm_vcpu_deliver_sipi_vector, =20 .get_untagged_addr =3D vmx_get_untagged_addr, =20 - .mem_enc_ioctl =3D vt_mem_enc_ioctl, - .vcpu_mem_enc_ioctl =3D vt_vcpu_mem_enc_ioctl, + .mem_enc_ioctl =3D vt_op_tdx_only(mem_enc_ioctl), + .vcpu_mem_enc_ioctl =3D vt_op_tdx_only(vcpu_mem_enc_ioctl), =20 - .private_max_mapping_level =3D vt_gmem_private_max_mapping_level + .private_max_mapping_level =3D vt_op_tdx_only(gmem_private_max_mapping_le= vel) }; =20 struct kvm_x86_init_ops vt_init_ops __initdata =3D { - .hardware_setup =3D vt_hardware_setup, + .hardware_setup =3D vt_op(hardware_setup), .handle_intel_pt_intr =3D NULL, =20 .runtime_ops =3D &vt_x86_ops, --=20 2.48.1