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Thu, 13 Mar 2025 04:41:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGR5pEWOAMrWLBgCGm+Y7Lh3lWzuvfVLeGeW96YfCH6EZ4bcTcGbK5BM/qWPoV32jTCmQphNw== X-Received: by 2002:a05:6a21:2d08:b0:1f3:41d5:65f6 with SMTP id adf61e73a8af0-1f544c35f78mr46788511637.32.1741866073376; Thu, 13 Mar 2025 04:41:13 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-af56ea964e3sm1063219a12.76.2025.03.13.04.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 04:41:13 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Thu, 13 Mar 2025 17:10:12 +0530 Subject: [PATCH v2 05/10] PCI: qcom: Add support for PCIe bus bw scaling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250313-mhi_bw_up-v2-5-869ca32170bf@oss.qualcomm.com> References: <20250313-mhi_bw_up-v2-0-869ca32170bf@oss.qualcomm.com> In-Reply-To: <20250313-mhi_bw_up-v2-0-869ca32170bf@oss.qualcomm.com> To: Bjorn Helgaas , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Johannes Berg , Jeff Johnson Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, linux-wireless@vger.kernel.org, ath11k@lists.infradead.org, quic_pyarlaga@quicinc.com, quic_vbadigan@quicinc.com, quic_vpernami@quicinc.com, quic_mrana@quicinc.com, Krishna Chaitanya Chundru , Jeff Johnson X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1741866038; l=2585; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=lgnh2IagKe1mBKfHYr9hIoBnucVnZ4hYxrdTnG/zcSI=; b=DOpCvzJguNOxEnEcPj9bp2zqW7NE5+r9kIIrCmHya4hHTe+ncFBrhbxMhaKsjwDOd+qCnU8jD SuAA5bLA2c+BuOZzHb9HXIrgzQ3DMO5zTqGXl08FjFuwI+NCuRXooMw X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: SOc9-csJTZFxX3KQjyyv1Zm0C12E-tRC X-Authority-Analysis: v=2.4 cv=Q4XS452a c=1 sm=1 tr=0 ts=67d2c45b cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=kXhGf0cxdCgfIYue-YsA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: SOc9-csJTZFxX3KQjyyv1Zm0C12E-tRC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_05,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 mlxscore=0 clxscore=1015 phishscore=0 malwarescore=0 spamscore=0 impostorscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130092 QCOM PCIe controllers need to disable ASPM before initiating link re-train. So as part of pre_bw_scale() disable ASPM and as part of post_scale_bus_bw() enable ASPM back. Update ICC & OPP votes based on the requested speed so that RPMh votes get updated based on the speed. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 49 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 49 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index b66c413f1e2b..a68e62422ff7 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1328,10 +1328,59 @@ static int qcom_pcie_set_icc_opp(struct qcom_pcie *= pcie, int speed, int width) return ret; } =20 +static int qcom_pcie_scale_bw(struct dw_pcie_rp *pp, int speed) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + u32 offset, status, width; + + offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + status =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + + width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, status); + + return qcom_pcie_set_icc_opp(pcie, speed, width); +} + +static int qcom_pcie_enable_disable_aspm(struct pci_dev *pdev, void *userd= ata) +{ + bool *enable =3D userdata; + + /* + * QCOM controllers doesn't support link re-train with ASPM enabled. + * Disable ASPM as part of pre_bus_bw() and enable them back as + * part of post_bus_bw(). + */ + if (*enable) + pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); + else + pci_disable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); + + return 0; +} + +static void qcom_pcie_host_post_scale_bus_bw(struct dw_pcie_rp *pp, int cu= rrent_speed) +{ + bool enable =3D true; + + pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_disable_aspm, &enable); + qcom_pcie_scale_bw(pp, current_speed); +} + +static int qcom_pcie_host_pre_scale_bus_bw(struct dw_pcie_rp *pp, int targ= et_speed) +{ + bool enable =3D false; + + pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_disable_aspm, &enable); + return qcom_pcie_scale_bw(pp, target_speed); +} + static const struct dw_pcie_host_ops qcom_pcie_dw_ops =3D { .init =3D qcom_pcie_host_init, .deinit =3D qcom_pcie_host_deinit, .post_init =3D qcom_pcie_host_post_init, + .pre_scale_bus_bw =3D qcom_pcie_host_pre_scale_bus_bw, + .post_scale_bus_bw =3D qcom_pcie_host_post_scale_bus_bw, }; =20 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ --=20 2.34.1