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a=ed25519-sha256; t=1741866038; l=865; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=kC8jbRyoGWHcr5F6bMdpdYEPmSroHXkD/t16CewXuhA=; b=ahY6Y0A168tVls7xeIA9KMyOy4DdXUlaSCT4aLtCvCoOwCqtVuPLJB4oihUbL9V6lKzs0jMIr YbHNVpW7tlaAw2nG6V5+CebfmNfg9kEZrPSIm76H9fmD5LPSKow5ily X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: 9qMG6Ow24J5tTN3SYd0vJ_HWUVJRkhGM X-Authority-Analysis: v=2.4 cv=DNSP4zNb c=1 sm=1 tr=0 ts=67d2c444 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=u3yxjsl3ZikD_R2semEA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: 9qMG6Ow24J5tTN3SYd0vJ_HWUVJRkhGM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_05,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 phishscore=0 malwarescore=0 mlxlogscore=982 priorityscore=1501 mlxscore=0 spamscore=0 bulkscore=0 impostorscore=0 suspectscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130092 If the link is not up till the pwrctl drivers enable power to endpoints then cur_bus_speed will not be updated with correct speed. As part of rescan, pci_bus_add_devices() will be called and as part of it update the link bus speed. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/bus.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c index 98910bc0fcc4..994879071d4c 100644 --- a/drivers/pci/bus.c +++ b/drivers/pci/bus.c @@ -432,6 +432,9 @@ void pci_bus_add_devices(const struct pci_bus *bus) struct pci_dev *dev; struct pci_bus *child; =20 + if (bus->self) + pcie_update_link_speed((struct pci_bus *)bus); + list_for_each_entry(dev, &bus->devices, bus_list) { /* Skip already-added devices */ if (pci_dev_is_added(dev)) --=20 2.34.1 From nobody Thu Dec 18 07:21:40 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35BCD2676FD for ; Thu, 13 Mar 2025 11:40:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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a=ed25519-sha256; t=1741866038; l=3703; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=QF3t9Npqd6WDL13WAUYjPdc5+X7unsf6GqmoGDJ96Z4=; b=r9fy/TEQIugEusXyzLXabUGKObbPiDQA2y0cW3J/suds1DrMZVbsdRhS6C69uzJ4DGZnytm19 VjGnvA/1AohDqYs2XNcrykXd1/23Tf2WTarVjm71yVNjL4/h/JZY91N X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: jgsxRz7MFofunIEmWNOo-PYstMbbZCvo X-Authority-Analysis: v=2.4 cv=I+llRMgg c=1 sm=1 tr=0 ts=67d2c449 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=p-QNkzJndyCg75AdzNkA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: jgsxRz7MFofunIEmWNOo-PYstMbbZCvo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_05,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 spamscore=0 malwarescore=0 mlxscore=0 suspectscore=0 phishscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130092 If the driver wants to move to higher data rate/speed than the current data rate then the controller driver may need to change certain votes so that link may come up at requested data rate/speed like QCOM PCIe controllers need to change their RPMh (Resource Power Manager-hardened) state. Once link retraining is done controller drivers needs to adjust their votes based on the final data rate. Some controllers also may need to update their bandwidth voting like ICC bw votings etc. So, add pre_scale_bus_bw() & post_scale_bus_bw() op to call before & after the link re-train. There is no explicit locking mechanisms as these are called by a single client endpoint driver. In case of PCIe switch, if there is a request to change target speed for a downstream port then no need to call these function ops as these are outside the scope of the controller drivers. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/pcie/bwctrl.c | 15 +++++++++++++++ include/linux/pci.h | 13 +++++++++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c index 0a5e7efbce2c..b1d660359553 100644 --- a/drivers/pci/pcie/bwctrl.c +++ b/drivers/pci/pcie/bwctrl.c @@ -161,6 +161,8 @@ static int pcie_bwctrl_change_speed(struct pci_dev *por= t, u16 target_speed, bool int pcie_set_target_speed(struct pci_dev *port, enum pci_bus_speed speed_r= eq, bool use_lt) { + struct pci_host_bridge *host =3D pci_find_host_bridge(port->bus); + bool is_rootport =3D pci_is_root_bus(port->bus); struct pci_bus *bus =3D port->subordinate; u16 target_speed; int ret; @@ -173,6 +175,16 @@ int pcie_set_target_speed(struct pci_dev *port, enum p= ci_bus_speed speed_req, =20 target_speed =3D pcie_bwctrl_select_speed(port, speed_req); =20 + /* + * The controller driver may need to be scaled for targeted speed + * otherwise link might not come up at requested speed. + */ + if (is_rootport && host->ops->pre_scale_bus_bw) { + ret =3D host->ops->pre_scale_bus_bw(host->bus, target_speed); + if (ret) + return ret; + } + scoped_guard(rwsem_read, &pcie_bwctrl_setspeed_rwsem) { struct pcie_bwctrl_data *data =3D port->link_bwctrl; =20 @@ -197,6 +209,9 @@ int pcie_set_target_speed(struct pci_dev *port, enum pc= i_bus_speed speed_req, !list_empty(&bus->devices)) ret =3D -EAGAIN; =20 + if (is_rootport && host->ops->post_scale_bus_bw) + host->ops->post_scale_bus_bw(host->bus, pci_bus_speed2lnkctl2(bus->cur_b= us_speed)); + return ret; } =20 diff --git a/include/linux/pci.h b/include/linux/pci.h index 47b31ad724fa..9ae199c1e698 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -804,6 +804,19 @@ struct pci_ops { void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int whe= re); int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size,= u32 *val); int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size= , u32 val); + /* + * Callback to the drivers to update ICC bw votes, clock frequencies etc = for + * the link re-train to come up in targeted speed. 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These are called by a + * single client endpoint driver, so there is no need for explicit + * locking mechanisms. + */ + void (*post_scale_bus_bw)(struct pci_bus *bus, int current_speed); }; =20 /* --=20 2.34.1 From nobody Thu Dec 18 07:21:40 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C01B7266B51 for ; Thu, 13 Mar 2025 11:41:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741866066; cv=none; b=n6pBZUyDVB6lh6VMiOIno1LVWA/5xVYGpcznWmTwE2jiyyEmiEn6h5s+AJqlCLNv2a63wymXkhNC6B8MGl2RDCOXlbr2WF1AEhnq9C2DDQQNFhL6c5GP3IUv1o7qHRXvwxaVQRzfU/ePmCc5Pz72GqesTBPDQHbBx6BBwlAdZdo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741866066; 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a=ed25519-sha256; t=1741866038; l=2235; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=PmKuDjh7TYnL36BsL4uFK3e2cvQCdB+O1CmCQrAD7C4=; b=VI/8VNWycXRlPi0pSYk0Fr6aifEQor01L8qOLpfV49fEVzw8N9gQDJummotBMBPqY31zZA7TF 8B8Qv21rWMtAW2YvmJKRYqNsOmy9HioTo1b4j7eqVXVCjt88vTUB69Y X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: -CRx_Df6LOIXH1d_r3e8omAC3HL8khFz X-Authority-Analysis: v=2.4 cv=V+F90fni c=1 sm=1 tr=0 ts=67d2c44f cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=kXhGf0cxdCgfIYue-YsA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-ORIG-GUID: -CRx_Df6LOIXH1d_r3e8omAC3HL8khFz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_05,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 impostorscore=0 spamscore=0 priorityscore=1501 phishscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 adultscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130092 Add support for pre_scale_bus_bw() & post_scale_bus_bw() function op's. Add support for DWC glue drivers to register for these ops. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 21 +++++++++++++++++++= ++ drivers/pci/controller/dwc/pcie-designware.h | 2 ++ 2 files changed, 23 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index ffaded8f2df7..4da4df62c3f8 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -697,10 +697,31 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus= *bus, unsigned int devfn, } EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); =20 +static int dw_pcie_pre_scale_bus_bw(struct pci_bus *bus, int target_speed) +{ + struct dw_pcie_rp *pp =3D bus->sysdata; + int ret =3D 0; + + if (pp->ops->pre_scale_bus_bw) + ret =3D pp->ops->pre_scale_bus_bw(pp, target_speed); + + return ret; +} + +static void dw_pcie_post_scale_bus_bw(struct pci_bus *bus, int current_spe= ed) +{ + struct dw_pcie_rp *pp =3D bus->sysdata; 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Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 61 +++++++++++++++++++-----------= ---- 1 file changed, 35 insertions(+), 26 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index e4d3366ead1f..b66c413f1e2b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1294,6 +1294,40 @@ static void qcom_pcie_host_post_init(struct dw_pcie_= rp *pp) pcie->cfg->ops->host_post_init(pcie); } =20 +static int qcom_pcie_set_icc_opp(struct qcom_pcie *pcie, int speed, int wi= dth) +{ + struct dw_pcie *pci =3D pcie->pci; + unsigned long freq_kbps; + struct dev_pm_opp *opp; + int ret =3D 0, freq_mbps; + + if (pcie->icc_mem) { + ret =3D icc_set_bw(pcie->icc_mem, 0, + width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); + if (ret) { + dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect pa= th: %d\n", + ret); + } + } else if (pcie->use_pm_opp) { + freq_mbps =3D pcie_dev_speed_mbps(pcie_link_speed[speed]); + if (freq_mbps < 0) + return -EINVAL; + + freq_kbps =3D freq_mbps * KILO; + opp =3D dev_pm_opp_find_freq_exact(pci->dev, freq_kbps * width, + true); + if (!IS_ERR(opp)) { + ret =3D dev_pm_opp_set_opp(pci->dev, opp); + if (ret) + dev_err(pci->dev, "Failed to set OPP for freq (%lu): %d\n", + freq_kbps * width, ret); + dev_pm_opp_put(opp); + } + } + + return ret; +} + static const struct dw_pcie_host_ops qcom_pcie_dw_ops =3D { .init =3D qcom_pcie_host_init, .deinit =3D qcom_pcie_host_deinit, @@ -1478,9 +1512,6 @@ static void qcom_pcie_icc_opp_update(struct qcom_pcie= *pcie) { u32 offset, status, width, speed; struct dw_pcie *pci =3D pcie->pci; - unsigned long freq_kbps; - struct dev_pm_opp *opp; - int ret, freq_mbps; =20 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); status =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); @@ -1492,29 +1523,7 @@ static void qcom_pcie_icc_opp_update(struct qcom_pci= e *pcie) speed =3D FIELD_GET(PCI_EXP_LNKSTA_CLS, status); width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, status); 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a=ed25519-sha256; t=1741866038; l=2585; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=lgnh2IagKe1mBKfHYr9hIoBnucVnZ4hYxrdTnG/zcSI=; b=DOpCvzJguNOxEnEcPj9bp2zqW7NE5+r9kIIrCmHya4hHTe+ncFBrhbxMhaKsjwDOd+qCnU8jD SuAA5bLA2c+BuOZzHb9HXIrgzQ3DMO5zTqGXl08FjFuwI+NCuRXooMw X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: SOc9-csJTZFxX3KQjyyv1Zm0C12E-tRC X-Authority-Analysis: v=2.4 cv=Q4XS452a c=1 sm=1 tr=0 ts=67d2c45b cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=kXhGf0cxdCgfIYue-YsA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: SOc9-csJTZFxX3KQjyyv1Zm0C12E-tRC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_05,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 mlxscore=0 clxscore=1015 phishscore=0 malwarescore=0 spamscore=0 impostorscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130092 QCOM PCIe controllers need to disable ASPM before initiating link re-train. So as part of pre_bw_scale() disable ASPM and as part of post_scale_bus_bw() enable ASPM back. Update ICC & OPP votes based on the requested speed so that RPMh votes get updated based on the speed. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 49 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 49 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index b66c413f1e2b..a68e62422ff7 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1328,10 +1328,59 @@ static int qcom_pcie_set_icc_opp(struct qcom_pcie *= pcie, int speed, int width) return ret; } =20 +static int qcom_pcie_scale_bw(struct dw_pcie_rp *pp, int speed) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + u32 offset, status, width; + + offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + status =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + + width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, status); + + return qcom_pcie_set_icc_opp(pcie, speed, width); +} + +static int qcom_pcie_enable_disable_aspm(struct pci_dev *pdev, void *userd= ata) +{ + bool *enable =3D userdata; + + /* + * QCOM controllers doesn't support link re-train with ASPM enabled. + * Disable ASPM as part of pre_bus_bw() and enable them back as + * part of post_bus_bw(). + */ + if (*enable) + pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); + else + pci_disable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); + + return 0; +} + +static void qcom_pcie_host_post_scale_bus_bw(struct dw_pcie_rp *pp, int cu= rrent_speed) +{ + bool enable =3D true; + + pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_disable_aspm, &enable); + qcom_pcie_scale_bw(pp, current_speed); +} + +static int qcom_pcie_host_pre_scale_bus_bw(struct dw_pcie_rp *pp, int targ= et_speed) +{ + bool enable =3D false; + + pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_disable_aspm, &enable); + return qcom_pcie_scale_bw(pp, target_speed); +} + static const struct dw_pcie_host_ops qcom_pcie_dw_ops =3D { .init =3D qcom_pcie_host_init, .deinit =3D qcom_pcie_host_deinit, .post_init =3D qcom_pcie_host_post_init, + .pre_scale_bus_bw =3D qcom_pcie_host_pre_scale_bus_bw, + .post_scale_bus_bw =3D qcom_pcie_host_post_scale_bus_bw, }; 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a=ed25519-sha256; t=1741866038; l=2486; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=nMXDxyNhjI58pEdLUQqctmcAdSRLINO8la+ypV3eSj8=; b=IQFrsWjbiSFkhhFBnz/9ECFoXIf7GbLmM1L6/nMA8GY8bq3hdf6o2GCxsl0IkRddYfEnufKMF 7l0la06C7++BPXkI71ClW+XSU+tDbkr2gtqK0EIF/oHROpwpoeEt/nS X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: dpm6dlTlVBco2DfTxGQ0t3MX2UxOFNTO X-Authority-Analysis: v=2.4 cv=DNSP4zNb c=1 sm=1 tr=0 ts=67d2c460 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=8tVK0NU1EB3xojDYR3gA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: dpm6dlTlVBco2DfTxGQ0t3MX2UxOFNTO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_05,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 phishscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 spamscore=0 bulkscore=0 impostorscore=0 suspectscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130092 From: Vivek Pernamitta As per MHI spec sec 6.6, MHI has capability registers which are located after the ERDB array. The location of this group of registers is indicated by the MISCOFF register. Each capability has a capability ID to determine which functionality is supported and each capability will point to the next capability supported. Add a basic function to read those capabilities offsets. Signed-off-by: Vivek Pernamitta Signed-off-by: Krishna Chaitanya Chundru --- drivers/bus/mhi/common.h | 4 ++++ drivers/bus/mhi/host/init.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/bus/mhi/common.h b/drivers/bus/mhi/common.h index dda340aaed95..eedac801b800 100644 --- a/drivers/bus/mhi/common.h +++ b/drivers/bus/mhi/common.h @@ -16,6 +16,7 @@ #define MHICFG 0x10 #define CHDBOFF 0x18 #define ERDBOFF 0x20 +#define MISCOFF 0x24 #define BHIOFF 0x28 #define BHIEOFF 0x2c #define DEBUGOFF 0x30 @@ -113,6 +114,9 @@ #define MHISTATUS_MHISTATE_MASK GENMASK(15, 8) #define MHISTATUS_SYSERR_MASK BIT(2) #define MHISTATUS_READY_MASK BIT(0) +#define MISC_CAP_MASK GENMASK(31, 0) +#define CAP_CAPID_MASK GENMASK(31, 24) +#define CAP_NEXT_CAP_MASK GENMASK(23, 12) =20 /* Command Ring Element macros */ /* No operation command */ diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c index a9b1f8beee7b..0b14b665ed15 100644 --- a/drivers/bus/mhi/host/init.c +++ b/drivers/bus/mhi/host/init.c @@ -467,6 +467,35 @@ int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl) return ret; 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Thu, 13 Mar 2025 04:41:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEdu71Za2ZIZUx6nw1zhHEdLpi1bIhp4FzCqFkiIftAJo4YOptEIDabzzSpcA9fncM47Xposw== X-Received: by 2002:a05:6a21:3986:b0:1f5:6d6f:28e with SMTP id adf61e73a8af0-1f56d6f0a57mr25199651637.42.1741866084978; Thu, 13 Mar 2025 04:41:24 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-af56ea964e3sm1063219a12.76.2025.03.13.04.41.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 04:41:24 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Thu, 13 Mar 2025 17:10:14 +0530 Subject: [PATCH v2 07/10] bus: mhi: host: Add support for Bandwidth scale Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250313-mhi_bw_up-v2-7-869ca32170bf@oss.qualcomm.com> References: <20250313-mhi_bw_up-v2-0-869ca32170bf@oss.qualcomm.com> In-Reply-To: <20250313-mhi_bw_up-v2-0-869ca32170bf@oss.qualcomm.com> To: Bjorn Helgaas , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Johannes Berg , Jeff Johnson Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, linux-wireless@vger.kernel.org, ath11k@lists.infradead.org, quic_pyarlaga@quicinc.com, quic_vbadigan@quicinc.com, quic_vpernami@quicinc.com, quic_mrana@quicinc.com, Krishna Chaitanya Chundru , Jeff Johnson X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1741866038; l=14880; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=Rkq9qxZem1xtKkroWEWyT6QgQtmiODnW7a2FMBFIv28=; b=yOPEIt8vuzQ8aa0EY3Y0GsWv9/o7mKsPchWc407vhO5cpSBLpEBXxrBKr2RYr2oMJg8rl32BR aEj1dx3KqQeCcW4++BEC5Xo5X+kzIUNdKEpAUrbQ51KjUZuaiFmhnqQ X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Authority-Analysis: v=2.4 cv=D6NHKuRj c=1 sm=1 tr=0 ts=67d2c467 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=DYpYOybAal_UZhkPskYA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-GUID: DZ7TtEXb2dJN9ORsVGECH4pBWzURVlQ8 X-Proofpoint-ORIG-GUID: DZ7TtEXb2dJN9ORsVGECH4pBWzURVlQ8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_05,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 priorityscore=1501 mlxscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 clxscore=1015 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130092 As per MHI spec sec 14, MHI supports bandwidth scaling to reduce power consumption. MHI bandwidth scaling is advertised in devices that contain the bandwidth scaling capability registers. If enabled, the device aggregates bandwidth requirements and sends them to the host in the form of an event. After the host performs the bandwidth switch, it sends an acknowledgment by ringing a doorbell. if the host supports bandwidth scaling events, then it must set BW_CFG.ENABLED bit, set BW_CFG.DB_CHAN_ID to the channel ID to the doorbell that will be used by the host to communicate the bandwidth scaling status and BW_CFG.ER_INDEX to the index for the event ring to which the device should send bandwidth scaling request in the bandwidth scaling capability register. As part of mmio init check if the bw scale capability is present or not, if present advertise host supports bw scale by setting all the required fields. MHI layer will only forward the bw scaling request to the controller driver, it is responsibility of the controller driver to do actual bw scaling and then pass status to the MHI. MHI will response back to the device based up on the status of the bw scale received. Add a new get_misc_doorbell() to get doorbell for misc capabilities to use the doorbell with mhi events like MHI BW scale etc. Use workqueue & mutex for the bw scale events as the pci_set_target_speed() which will called by the mhi controller driver can sleep. Signed-off-by: Krishna Chaitanya Chundru --- drivers/bus/mhi/common.h | 16 +++++++ drivers/bus/mhi/host/init.c | 64 ++++++++++++++++++++++++- drivers/bus/mhi/host/internal.h | 7 ++- drivers/bus/mhi/host/main.c | 101 ++++++++++++++++++++++++++++++++++++= +++- drivers/bus/mhi/host/pm.c | 10 +++- include/linux/mhi.h | 13 ++++++ 6 files changed, 205 insertions(+), 6 deletions(-) diff --git a/drivers/bus/mhi/common.h b/drivers/bus/mhi/common.h index eedac801b800..0a02acee709a 100644 --- a/drivers/bus/mhi/common.h +++ b/drivers/bus/mhi/common.h @@ -208,6 +208,22 @@ #define MHI_RSCTRE_DATA_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \ MHI_PKT_TYPE_COALESCING)) =20 +/* MHI Bandwidth scaling offsets */ +#define MHI_BW_SCALE_CFG_OFFSET 0x4 +#define MHI_BW_SCALE_CAP_ID (3) + +#define MHI_BW_SCALE_ENABLE(bw_scale_db, er_index) cpu_to_le32(FIELD_PREP(= GENMASK(31, 25), \ + bw_scale_db) | \ + FIELD_PREP(GENMASK(23, 19), er_index) | \ + BIT(24)) + +#define MHI_TRE_GET_EV_BW_REQ_SEQ(tre) FIELD_GET(GENMASK(15, 8), (MHI_TRE_= GET_DWORD(tre, 0))) +#define MHI_BW_SCALE_DB_ID(er_index) FIELD_PREP(GENMASK(31, 25), er_index) + +#define MHI_BW_SCALE_RESULT(status, seq) cpu_to_le32(FIELD_PREP(GENMASK(11= , 8), status) | \ + FIELD_PREP(GENMASK(7, 0), seq)) +#define MHI_BW_SCALE_NACK 0xF + enum mhi_pkt_type { MHI_PKT_TYPE_INVALID =3D 0x0, MHI_PKT_TYPE_NOOP_CMD =3D 0x1, diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c index 0b14b665ed15..71abe02f5726 100644 --- a/drivers/bus/mhi/host/init.c +++ b/drivers/bus/mhi/host/init.c @@ -496,10 +496,56 @@ static int mhi_get_capability_offset(struct mhi_contr= oller *mhi_cntrl, u32 capab return -ENXIO; } =20 +/* to be used only if a single event ring with the type is present */ +static int mhi_get_er_index(struct mhi_controller *mhi_cntrl, + enum mhi_er_data_type type) +{ + struct mhi_event *mhi_event =3D mhi_cntrl->mhi_event; + int i; + + /* find event ring for requested type */ + for (i =3D 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { + if (mhi_event->data_type =3D=3D type) + return mhi_event->er_index; + } + + return -ENOENT; +} + +static int mhi_init_bw_scale(struct mhi_controller *mhi_cntrl, + int bw_scale_db) +{ + struct device *dev =3D &mhi_cntrl->mhi_dev->dev; + u32 bw_cfg_offset, val =3D 0; + int ret, er_index; + + ret =3D mhi_get_capability_offset(mhi_cntrl, MHI_BW_SCALE_CAP_ID, + &bw_cfg_offset); + if (ret) + return ret; + + /* No ER configured to support BW scale */ + er_index =3D mhi_get_er_index(mhi_cntrl, MHI_ER_BW_SCALE); + if (er_index < 0) + return er_index; + + bw_cfg_offset +=3D MHI_BW_SCALE_CFG_OFFSET; + + /* advertise host support */ + val =3D MHI_BW_SCALE_ENABLE(bw_scale_db, er_index); + + mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, bw_cfg_offset, val); + + dev_dbg(dev, "Bandwidth scaling setup complete. Event ring:%d\n", + er_index); + + return 0; +} + int mhi_init_mmio(struct mhi_controller *mhi_cntrl) { u32 val; - int i, ret; + int i, ret, doorbell =3D 0; struct mhi_chan *mhi_chan; struct mhi_event *mhi_event; void __iomem *base =3D mhi_cntrl->regs; @@ -633,6 +679,16 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl) return ret; } =20 + if (mhi_cntrl->get_misc_doorbell) + doorbell =3D mhi_cntrl->get_misc_doorbell(mhi_cntrl, MHI_ER_BW_SCALE); + + if (doorbell > 0) { + ret =3D mhi_init_bw_scale(mhi_cntrl, doorbell); + if (!ret) + mhi_cntrl->bw_scale_db =3D base + val + (8 * doorbell); + else + dev_warn(dev, "BW scale setup failure\n"); + } return 0; } =20 @@ -778,6 +834,9 @@ static int parse_ev_cfg(struct mhi_controller *mhi_cntr= l, case MHI_ER_CTRL: mhi_event->process_event =3D mhi_process_ctrl_ev_ring; break; + case MHI_ER_BW_SCALE: + mhi_event->process_event =3D mhi_process_bw_scale_ev_ring; + break; default: dev_err(dev, "Event Ring type not supported\n"); goto error_ev_cfg; @@ -1012,9 +1071,12 @@ int mhi_register_controller(struct mhi_controller *m= hi_cntrl, =20 mhi_event->mhi_cntrl =3D mhi_cntrl; spin_lock_init(&mhi_event->lock); + mutex_init(&mhi_event->mutex); if (mhi_event->data_type =3D=3D MHI_ER_CTRL) tasklet_init(&mhi_event->task, mhi_ctrl_ev_task, (ulong)mhi_event); + else if (mhi_event->data_type =3D=3D MHI_ER_BW_SCALE) + INIT_WORK(&mhi_event->work, mhi_process_ev_work); else tasklet_init(&mhi_event->task, mhi_ev_task, (ulong)mhi_event); diff --git a/drivers/bus/mhi/host/internal.h b/drivers/bus/mhi/host/interna= l.h index 3134f111be35..bf7c6a7c9383 100644 --- a/drivers/bus/mhi/host/internal.h +++ b/drivers/bus/mhi/host/internal.h @@ -241,6 +241,8 @@ struct mhi_event { struct mhi_ring ring; struct db_cfg db_cfg; struct tasklet_struct task; + struct work_struct work; + struct mutex mutex; spinlock_t lock; int (*process_event)(struct mhi_controller *mhi_cntrl, struct mhi_event *mhi_event, @@ -403,7 +405,8 @@ int mhi_process_data_event_ring(struct mhi_controller *= mhi_cntrl, struct mhi_event *mhi_event, u32 event_quota); int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, struct mhi_event *mhi_event, u32 event_quota); - +int mhi_process_bw_scale_ev_ring(struct mhi_controller *mhi_cntrl, + struct mhi_event *mhi_event, u32 event_quota); /* ISR handlers */ irqreturn_t mhi_irq_handler(int irq_number, void *dev); irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *dev); @@ -419,5 +422,5 @@ void mhi_unmap_single_no_bb(struct mhi_controller *mhi_= cntrl, struct mhi_buf_info *buf_info); void mhi_unmap_single_use_bb(struct mhi_controller *mhi_cntrl, struct mhi_buf_info *buf_info); - +void mhi_process_ev_work(struct work_struct *work); #endif /* _MHI_INT_H */ diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c index 4de75674f193..967563d86aec 100644 --- a/drivers/bus/mhi/host/main.c +++ b/drivers/bus/mhi/host/main.c @@ -472,7 +472,10 @@ irqreturn_t mhi_irq_handler(int irq_number, void *dev) if (mhi_dev) mhi_notify(mhi_dev, MHI_CB_PENDING_DATA); } else { - tasklet_schedule(&mhi_event->task); + if (mhi_event->data_type =3D=3D MHI_ER_BW_SCALE) + queue_work(mhi_cntrl->hiprio_wq, &mhi_event->work); + else + tasklet_schedule(&mhi_event->task); } =20 return IRQ_HANDLED; @@ -1049,6 +1052,102 @@ int mhi_process_data_event_ring(struct mhi_controll= er *mhi_cntrl, return count; } =20 +/* dedicated bw scale event ring processing */ +int mhi_process_bw_scale_ev_ring(struct mhi_controller *mhi_cntrl, + struct mhi_event *mhi_event, u32 event_quota) +{ + struct mhi_event_ctxt *er_ctxt =3D &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_even= t->er_index]; + struct device *dev =3D &mhi_cntrl->mhi_dev->dev; + struct mhi_ring *ev_ring =3D &mhi_event->ring; + dma_addr_t ptr =3D le64_to_cpu(er_ctxt->rp); + u32 response =3D MHI_BW_SCALE_NACK; + struct mhi_ring_element *dev_rp; + struct mhi_link_info link_info; + int ret =3D -EINVAL; + + if (unlikely(MHI_EVENT_ACCESS_INVALID(mhi_cntrl->pm_state))) { + ret =3D -EIO; + goto exit_bw_scale_process; + } + + if (!MHI_IN_MISSION_MODE(mhi_cntrl->ee)) + goto exit_bw_scale_process; + + if (!is_valid_ring_ptr(ev_ring, ptr)) { + dev_err(dev, + "Event ring rp points outside of the event ring\n"); + ret =3D -EIO; + goto exit_bw_scale_process; + } + + dev_rp =3D mhi_to_virtual(ev_ring, ptr); + + /* if rp points to base, we need to wrap it around */ + if (dev_rp =3D=3D ev_ring->base) + dev_rp =3D ev_ring->base + ev_ring->len; + dev_rp--; + + /* fast forward to currently processed element and recycle er */ + ev_ring->rp =3D dev_rp; + ev_ring->wp =3D dev_rp - 1; + if (ev_ring->wp < ev_ring->base) + ev_ring->wp =3D ev_ring->base + ev_ring->len - ev_ring->el_size; + mhi_recycle_ev_ring_element(mhi_cntrl, ev_ring); + + if (WARN_ON(MHI_TRE_GET_EV_TYPE(dev_rp) !=3D MHI_PKT_TYPE_BW_REQ_EVENT)) { + dev_err(dev, "!BW SCALE REQ event\n"); + goto exit_bw_scale_process; + } + + link_info.target_link_speed =3D MHI_TRE_GET_EV_LINKSPEED(dev_rp); + link_info.target_link_width =3D MHI_TRE_GET_EV_LINKWIDTH(dev_rp); + link_info.sequence_num =3D MHI_TRE_GET_EV_BW_REQ_SEQ(dev_rp); + + dev_info(dev, "Received BW_REQ with seq:%d link speed:0x%x width:0x%x\n", + link_info.sequence_num, + link_info.target_link_speed, + link_info.target_link_width); + + /* bring host and device out of suspended states */ + ret =3D mhi_device_get_sync(mhi_cntrl->mhi_dev); + if (ret) + goto exit_bw_scale_process; + + mhi_cntrl->runtime_get(mhi_cntrl); + + ret =3D mhi_cntrl->bw_scale(mhi_cntrl, &link_info); + if (!ret) + response =3D 0; + + response =3D MHI_BW_SCALE_RESULT(response, link_info.sequence_num); + + write_lock_bh(&mhi_cntrl->pm_lock); + mhi_write_reg(mhi_cntrl, mhi_cntrl->bw_scale_db, 0, response); + write_unlock_bh(&mhi_cntrl->pm_lock); + + mhi_cntrl->runtime_put(mhi_cntrl); + mhi_device_put(mhi_cntrl->mhi_dev); + +exit_bw_scale_process: + dev_dbg(dev, "exit er_index:%u ret:%d\n", mhi_event->er_index, ret); + + return ret; +} + +void mhi_process_ev_work(struct work_struct *work) +{ + struct mhi_event *mhi_event =3D container_of(work, struct mhi_event, + work); + + struct mhi_controller *mhi_cntrl =3D mhi_event->mhi_cntrl; + + if (unlikely(MHI_EVENT_ACCESS_INVALID(mhi_cntrl->pm_state))) + return; + + guard(mutex)(&mhi_event->mutex); + mhi_event->process_event(mhi_cntrl, mhi_event, U32_MAX); +} + void mhi_ev_task(unsigned long data) { struct mhi_event *mhi_event =3D (struct mhi_event *)data; diff --git a/drivers/bus/mhi/host/pm.c b/drivers/bus/mhi/host/pm.c index 11c0e751f223..9c848ca582f0 100644 --- a/drivers/bus/mhi/host/pm.c +++ b/drivers/bus/mhi/host/pm.c @@ -523,7 +523,10 @@ static void mhi_pm_disable_transition(struct mhi_contr= oller *mhi_cntrl, if (mhi_event->offload_ev) continue; disable_irq(mhi_cntrl->irq[mhi_event->irq]); - tasklet_kill(&mhi_event->task); + if (mhi_event->data_type =3D=3D MHI_ER_BW_SCALE) + cancel_work_sync(&mhi_event->work); + else + tasklet_kill(&mhi_event->task); } =20 /* Release lock and wait for all pending threads to complete */ @@ -670,7 +673,10 @@ static void mhi_pm_sys_error_transition(struct mhi_con= troller *mhi_cntrl) for (i =3D 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { if (mhi_event->offload_ev) continue; - tasklet_kill(&mhi_event->task); + if (mhi_event->data_type =3D=3D MHI_ER_BW_SCALE) + cancel_work_sync(&mhi_event->work); + else + tasklet_kill(&mhi_event->task); } =20 /* Release lock and wait for all pending threads to complete */ diff --git a/include/linux/mhi.h b/include/linux/mhi.h index 059dc94d20bb..d9bf88c35d14 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -102,10 +102,12 @@ struct image_info { * struct mhi_link_info - BW requirement * target_link_speed - Link speed as defined by TLS bits in LinkControl reg * target_link_width - Link width as defined by NLW bits in LinkStatus reg + * sequence_num - used by device to track bw requests sent to host */ struct mhi_link_info { unsigned int target_link_speed; unsigned int target_link_width; + int sequence_num; }; =20 /** @@ -183,10 +185,12 @@ enum mhi_ch_ee_mask { * enum mhi_er_data_type - Event ring data types * @MHI_ER_DATA: Only client data over this ring * @MHI_ER_CTRL: MHI control data and client data + * @MHI_ER_BW_SCALE: MHI controller bandwidth scale functionality */ enum mhi_er_data_type { MHI_ER_DATA, MHI_ER_CTRL, + MHI_ER_BW_SCALE, }; =20 /** @@ -299,6 +303,7 @@ struct mhi_controller_config { * @bhi: Points to base of MHI BHI register space * @bhie: Points to base of MHI BHIe register space * @wake_db: MHI WAKE doorbell register address + * @wake_db: MHI BW_SCALE doorbell register address * @iova_start: IOMMU starting address for data (required) * @iova_stop: IOMMU stop address for data (required) * @fw_image: Firmware image name for normal booting (optional) @@ -355,6 +360,8 @@ struct mhi_controller_config { * @write_reg: Write a MHI register via the physical link (required) * @reset: Controller specific reset function (optional) * @edl_trigger: CB function to trigger EDL mode (optional) + * @get_misc_doobell: function to get doorbell used for MISC feature like = BW scale etc (optional) + * @bw_scale: CB function for passing BW scale info (optional) * @buffer_len: Bounce buffer length * @index: Index of the MHI controller instance * @bounce_buf: Use of bounce buffer @@ -376,6 +383,7 @@ struct mhi_controller { void __iomem *bhi; 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Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/pcie/bwctrl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c index b1d660359553..0f4f68c170cd 100644 --- a/drivers/pci/pcie/bwctrl.c +++ b/drivers/pci/pcie/bwctrl.c @@ -214,6 +214,7 @@ int pcie_set_target_speed(struct pci_dev *port, enum pc= i_bus_speed speed_req, =20 return ret; } +EXPORT_SYMBOL_GPL(pcie_set_target_speed); =20 static void pcie_bwnotif_enable(struct pcie_device *srv) { --=20 2.34.1 From nobody Thu Dec 18 07:21:40 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D638266F17 for ; Thu, 13 Mar 2025 11:41:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/pci.c | 12 ++++++++++++ include/linux/pci.h | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 869d204a70a3..75505437a9c9 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6011,6 +6011,18 @@ int pcie_link_speed_mbps(struct pci_dev *pdev) } EXPORT_SYMBOL(pcie_link_speed_mbps); =20 +/** + * pci_lnkctl2_bus_speed - converts lnkctl2 speed to pci_bus_speed + * @speed: LNKCAP2 SLS value + * + * Returns pci_bus_speed + */ +enum pci_bus_speed pci_lnkctl2_bus_speed(int speed) +{ + return pcie_link_speed[speed]; +} +EXPORT_SYMBOL(pci_lnkctl2_bus_speed); + /** * pcie_bandwidth_available - determine minimum link settings of a PCIe * device and its bandwidth limitation diff --git a/include/linux/pci.h b/include/linux/pci.h index 9ae199c1e698..b84473f228c8 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1653,6 +1653,7 @@ unsigned char pci_bus_max_busnr(struct pci_bus *bus); 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a=ed25519-sha256; t=1741866038; l=2735; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=UDj4phVy/DG+9hjqxt6EGxZVpcx8i+kJ4nOzNceABAI=; b=hqdCuLeJn0OqieMuIehjgOVSVH10bKZwuK9rz+XDm+BSXBAIpRQvbjfXjpv4/+/BYkNxW94aN OFUd0jheytFBkp8l/OA96dvuqcapnrWdXf6JwA+9nMflIMTRzatgsbn X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Authority-Analysis: v=2.4 cv=CNQqXQrD c=1 sm=1 tr=0 ts=67d2c477 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=PcFPl4qhhl0nOZx1bFwA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: oPYqlfjx5bSI7yXUMnC_omIvrG4inNbV X-Proofpoint-GUID: oPYqlfjx5bSI7yXUMnC_omIvrG4inNbV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_05,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 mlxscore=0 priorityscore=1501 suspectscore=0 phishscore=0 malwarescore=0 clxscore=1015 bulkscore=0 adultscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130092 From: Miaoqing Pan Add support for MHI bandwidth scaling, which will reduce power consumption if WLAN operates with lower bandwidth. This feature is only enabled for QCA6390. Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-04546-QCAHSPSWPL_V1_V2_SILICONZ_I= OE-1 Signed-off-by: Miaoqing Pan --- drivers/net/wireless/ath/ath11k/mhi.c | 41 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 41 insertions(+) diff --git a/drivers/net/wireless/ath/ath11k/mhi.c b/drivers/net/wireless/a= th/ath11k/mhi.c index 6e45f464a429..74769c0993ae 100644 --- a/drivers/net/wireless/ath/ath11k/mhi.c +++ b/drivers/net/wireless/ath/ath11k/mhi.c @@ -20,6 +20,7 @@ #define MHI_TIMEOUT_DEFAULT_MS 20000 #define RDDM_DUMP_SIZE 0x420000 #define MHI_CB_INVALID 0xff +#define MHI_BW_SCALE_CHAN_DB 126 =20 static const struct mhi_channel_config ath11k_mhi_channels_qca6390[] =3D { { @@ -73,6 +74,17 @@ static struct mhi_event_config ath11k_mhi_events_qca6390= [] =3D { .client_managed =3D false, .offload_channel =3D false, }, + { + .num_elements =3D 8, + .irq_moderation_ms =3D 0, + .irq =3D 1, + .mode =3D MHI_DB_BRST_DISABLE, + .data_type =3D MHI_ER_BW_SCALE, + .priority =3D 2, + .hardware_event =3D false, + .client_managed =3D false, + .offload_channel =3D false, + }, }; =20 static const struct mhi_controller_config ath11k_mhi_config_qca6390 =3D { @@ -313,6 +325,33 @@ static void ath11k_mhi_op_write_reg(struct mhi_control= ler *mhi_cntrl, writel(val, addr); } =20 +static int ath11k_mhi_op_get_misc_doorbell(struct mhi_controller *mhi_cntr= l, + enum mhi_er_data_type type) +{ + if (type =3D=3D MHI_ER_BW_SCALE) + return MHI_BW_SCALE_CHAN_DB; + + return -EINVAL; +} + +static int ath11k_mhi_op_bw_scale(struct mhi_controller *mhi_cntrl, + struct mhi_link_info *link_info) +{ + enum pci_bus_speed speed =3D pci_lnkctl2_bus_speed(link_info->target_link= _speed); + struct ath11k_base *ab =3D dev_get_drvdata(mhi_cntrl->cntrl_dev); + struct pci_dev *pci_dev =3D to_pci_dev(ab->dev); + struct pci_dev *pdev; + + if (!pci_dev) + return -EINVAL; + + pdev =3D pci_upstream_bridge(pci_dev); + if (!pdev) + return -ENODEV; + + return pcie_set_target_speed(pdev, speed, true); +} + static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl) { struct device_node *np; @@ -389,6 +428,8 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci) mhi_ctrl->status_cb =3D ath11k_mhi_op_status_cb; mhi_ctrl->read_reg =3D ath11k_mhi_op_read_reg; mhi_ctrl->write_reg =3D ath11k_mhi_op_write_reg; + mhi_ctrl->bw_scale =3D ath11k_mhi_op_bw_scale; + mhi_ctrl->get_misc_doorbell =3D ath11k_mhi_op_get_misc_doorbell; =20 switch (ab->hw_rev) { case ATH11K_HW_QCN9074_HW10: --=20 2.34.1