From nobody Thu Dec 18 07:19:47 2025 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D1901F7545 for ; Thu, 13 Mar 2025 21:43:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741902205; cv=none; b=PBmV45FRYu6R9BrK2fULBVyJQKmdUktUc/avH+d2e10xJDTxAnSx2DQdTiG9amLU6KE4obX3dlfUsHbIaAkZ50bBu35RL1bkPnim6cGHdlNNnWNpApffZ0Ff0IrWrWc/SvhlNR2kdaZ7Sk5cy4rtgO68p9XYtpzE82n698rLRok= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741902205; c=relaxed/simple; bh=a3wrzpVCaYNuMwQuNJHx7mKyoFe02+zkw63lLomddaA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eaRljvaVbr34xv40znnpxza683ZRwyka7CpQtY2ARQE7+OC1ZVVWZsvrvxb57Di41hNHUPoriekVGSN6zXK++/vROpiaE8jDsce4xUs1+ZmN6tE5oYHfI1EZ1K3eynDkdlQ7aS33I1xO6cB7e0PtwuBQv2LJ7MpcfvcvXxn+gMg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=tJamV0ca; arc=none smtp.client-ip=209.85.218.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="tJamV0ca" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-ac25313ea37so290840466b.1 for ; Thu, 13 Mar 2025 14:43:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741902201; x=1742507001; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qZMmcHfeB4rBHuWqkNhUsUagbSg6bNeQKDj5E5I8kNM=; b=tJamV0caOKAODX9elPyfz2762PepQmOA4jbp8A54lFjSBTVt2Xou5vNiwkLCI6hfnH 1SB7mG3JjSRP0A77cF05jv8EfIVuWsqK7ukUpny6Re8Fgv3ShReQQkXNObLWfAzxbex2 JZLR4j0mWicYX7QZMIOEXouEgyVdhwNPlLbF/MkEVp7SAA4MnKAObExbymNkCFvOSstV u49hePDOSN3PSgXCbSC+V6RtTvH/hevhURgs8TjjjK5bVCg2KEgb552DJHCATB1XMGjf uURrvc3yMm3FCJQl3FzSXkRvTppAdkh+V+RfuxnIN8Gv8EjhvIi+EMpnjTEGg9Au1TGu 1XVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741902201; x=1742507001; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qZMmcHfeB4rBHuWqkNhUsUagbSg6bNeQKDj5E5I8kNM=; b=pkBnQBnkrYOCDOkjoSjr2nB77dnzRyqP9zGPsPZX+iuU5q6QjDZMUznxf1TL3Hcvqc yBHPcGR+RNBNNF16rhNSLLa82h/lK48SlvqUHirFbSMad7LH3DTU/n63+NJ+hWABLAy7 GAphBEALsmAJznvjEABi9klrOR0beajtjaR0CI3GRw9uvv3XdTMTQMLKFZ6MHcWKkW0k eDd9/WTnw5DSwdrUei6wjCPPUD/kTlLjzO+OmuBlDEEXvEy8LW5iAK6vyEgqXySakuCN lPimudKmkbrBSKIeWlsEv1b15Sl7gzUvCzBeouTbiY5w0Cf0j36exFAamo28euI8QrYz drsA== X-Forwarded-Encrypted: i=1; AJvYcCXDmR5/fnmy21WsD9D45ov3GY+Xo6oj4HYKehP9yNJBUuZmWugNcCuYcDx6eCvE2q/34fuYPTGHk540IMo=@vger.kernel.org X-Gm-Message-State: AOJu0Yx9wFOGlrVme7NrzD8dyH4qTzrbK7U2DUFCN1QDCMZ1aIGapWuJ jQYpuEnh3k49WDPbAPdLD4VdKKxXuzoAIrZp89nxMB2B3Zq83M2kLk2AvfBuRWA= X-Gm-Gg: ASbGncvV5/usnaTwWVP/XhGIwuaIyf66dNzEaTH7Tuw6KUZ9/UMVZcqqZqHj6Mp2Rbn ZQ4SBS63+y2wjtF7EH/ggkBF/aTv1b/5FptV42DAN12Nc2nDIqPzUOf6rLZaqqtltqjwkcbbSA8 dpSrcywBimiUl9TL3sZsWxKu5xXPdB5tZeW8hU0eD8ZW9azaR3jBLnOsp30YxJ22nIVDLyUerkW 9Tgyt+3Dg2fPUFzwsdAcPWIByzy0yaDFvhB/GXphy8p7Cmp+mfperca5cXUpbnUx1g2Guct34YH 0SQ5uMwb4wNZUFRnxz9k13nPbYG4HKhglJKkxx0+yKFY+W8zYdy9j0/k5bSFQEUUyKa9ob5vCBa o4JAkp71Ckk7BfWsDTfbS4qJC2CxJbDa74xHQb0bCje1PNSLTCMpcBH/82pxsvBXf21nP X-Google-Smtp-Source: AGHT+IEoowJuPUsYRRA5+TwZx73pPwDGjlSG75J2GAB4x1TkjB/AGGligwnBjapO7S/jscNp4DnL5w== X-Received: by 2002:a17:907:2d0f:b0:ac2:8a59:92f4 with SMTP id a640c23a62f3a-ac330408d5cmr8908566b.51.1741902200774; Thu, 13 Mar 2025 14:43:20 -0700 (PDT) Received: from [192.168.178.107] (2001-1c06-2302-5600-7555-cca3-bbc4-648b.cable.dynamic.v6.ziggo.nl. [2001:1c06:2302:5600:7555:cca3:bbc4:648b]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac314a489e0sm126938866b.151.2025.03.13.14.43.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 14:43:20 -0700 (PDT) From: Bryan O'Donoghue Date: Thu, 13 Mar 2025 21:43:16 +0000 Subject: [PATCH v5 4/5] arm64: dts: qcom: x1e80100: Add CCI definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-4-846c9a6493a8@linaro.org> References: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-0-846c9a6493a8@linaro.org> In-Reply-To: <20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-0-846c9a6493a8@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue , Konrad Dybcio , Vladimir Zapolskiy X-Mailer: b4 0.14.2 Add in two CCI busses. One bus has two CCI bus master pinouts: cci_i2c_sda0 =3D gpio101 cci_i2c_scl0 =3D gpio102 cci_i2c_sda1 =3D gpio103 cci_i2c_scl1 =3D gpio104 The second bus has two CCI bus master pinouts: cci_i2c_sda2 =3D gpio105 cci_i2c_scl2 =3D gpio106 aon_cci_i2c_sda3 =3D gpio235 aon_cci_i2c_scl3 =3D gpio236 Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 150 +++++++++++++++++++++++++++++= ++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 065a219e69c632eca288c9ade001949e37b92173..4ae0f67a634a982143df7aa933e= c4de697f357a5 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5117,6 +5117,84 @@ usb_1_ss1_dwc3_ss: endpoint { }; }; =20 + cci0: cci@ac15000 { + compatible =3D "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg =3D <0 0x0ac15000 0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci0_default>; + pinctrl-1 =3D <&cci0_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac16000 { + compatible =3D "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg =3D <0 0x0ac16000 0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci1_default>; + pinctrl-1 =3D <&cci1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + camcc: clock-controller@ade0000 { compatible =3D "qcom,x1e80100-camcc"; reg =3D <0 0x0ade0000 0 0x20000>; @@ -5741,6 +5819,78 @@ tlmm: pinctrl@f100000 { gpio-ranges =3D <&tlmm 0 0 239>; wakeup-parent =3D <&pdc>; =20 + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins =3D "gpio101", "gpio102"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci0_i2c1_default: cci0-i2c1-default-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins =3D "gpio103", "gpio104"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins =3D "gpio101", "gpio102"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins =3D "gpio103", "gpio104"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins =3D "gpio105","gpio106"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci1_i2c1_default: cci1-i2c1-default-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins =3D "gpio235","gpio236"; + function =3D "aon_cci"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins =3D "gpio105","gpio106"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins =3D "gpio235","gpio236"; + function =3D "aon_cci"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { /* SDA, SCL */ pins =3D "gpio0", "gpio1"; --=20 2.48.1