From nobody Thu Dec 18 07:11:53 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7DD8260A3C; Thu, 13 Mar 2025 09:06:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741856789; cv=none; b=NhUtdykQztG5tmh0khl/cygSTot8k+3Sfe7STXXK0pmaC56Uhw4XSMdhQY8X77dMUkwOIFYiauojZSF+Q2ZpX7InI0U6+nW7d2fYkWF23toTOz/VoQT5ek1wDDSWWJKKK95azD3ueNY619bYO1KlRZrOLyjYKdnmajuru80fhGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741856789; c=relaxed/simple; bh=rcZ4hUqkPHAzf/+Hghm6DmFVxWHcdR3LRlMwrsk358A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AIrqg5S4G0L//SXtC8dkoB3nw+FxctVCUom93cbL86UEuAScjGRVh0YgXacuAb53CQ2flXM1EbTAAolkZ/1st1kUAvy1zoPqo7fCLjkmXCn0SyAnTof32cOC/7CZzzywT4tE6Mtf/ZErTqOQFApWz9FfWmD8Zms3kYudEcOdBD8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=o2tKgqtt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="o2tKgqtt" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3DDF8C4CEEA; Thu, 13 Mar 2025 09:06:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1741856788; bh=rcZ4hUqkPHAzf/+Hghm6DmFVxWHcdR3LRlMwrsk358A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=o2tKgqttg+IrzwqcRJSBH46YNitpjH2/Inzl5Hqly8q08RRSw+9TyNK8lGYI0/nRF BcQ0SiCixJZpWtdXqr+zd9k6zsSnXaWvR0NSDtQAhqAtwb2NQZjd+iQAggRW/NoVVt E4pZ1qmqgQYR1q9UcBCMqc20R8WjQEM0+D2kOrzex5OLyi/hvyVPPzD0n8OnbAzDBo x+5wJf3jUyRjkyN+60nhH24AXWChhTCvirNXF3oOCqSCMl3lxJGK9m/iOp5lijGUSd gnbPIe5NVuH/6cBfyT30/SZ0FghvU5wYEP4seNrVyQszkm7w0EGyZOYIQ5IVh7V4UR OkQTglES4/X5A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CD21C28B28; Thu, 13 Mar 2025 09:06:28 +0000 (UTC) From: Kelvin Zhang via B4 Relay Date: Thu, 13 Mar 2025 17:05:34 +0800 Subject: [PATCH v4 1/3] dt-bindings: reset: Add compatible for Amlogic A4/A5 Reset Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250313-a4-a5-reset-v4-1-8076f684d6cf@amlogic.com> References: <20250313-a4-a5-reset-v4-0-8076f684d6cf@amlogic.com> In-Reply-To: <20250313-a4-a5-reset-v4-0-8076f684d6cf@amlogic.com> To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Zelong Dong , Conor Dooley , Kelvin Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1741856786; l=2254; i=kelvin.zhang@amlogic.com; s=20240329; h=from:subject:message-id; bh=RBPG6lp45fxsEDVQ6Y1mIySEYTUUWfsM6OujOhVw3vA=; b=JCc17KCO/vZFwG4kiG7RGpV4Q7ntH3awp5/UxBjM4/ryfjUXlI8ceBJaUjO6BexJJnfCWr1aU jRYu0G1MUD7A4hXQqUzVzR7Su3BBygjqvihxq3h2fwr5RN7kxfhuJHe X-Developer-Key: i=kelvin.zhang@amlogic.com; a=ed25519; pk=pgnle7HTNvnNTcOoGejvtTC7BJT30HUNXfMHRRXSylI= X-Endpoint-Received: by B4 Relay for kelvin.zhang@amlogic.com/20240329 with auth_id=148 X-Original-From: Kelvin Zhang Reply-To: kelvin.zhang@amlogic.com From: Zelong Dong Add compatibles for Amlogic A4 and A5 reset controllers, which fall back to 'amlogic,meson-s4-reset'. Signed-off-by: Zelong Dong Acked-by: Conor Dooley Acked-by: Philipp Zabel Link: https://lore.kernel.org/r/20240918074211.8067-2-zelong.dong@amlogic.c= om Signed-off-by: Kelvin Zhang --- .../bindings/reset/amlogic,meson-reset.yaml | 22 ++++++++++++++----= ---- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.ya= ml b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml index 695ef38a7bb346c92b4cf428e7615d45682c940a..150e95c0d9bed74c7045942610a= 311114a257889 100644 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml @@ -12,14 +12,20 @@ maintainers: =20 properties: compatible: - enum: - - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible= SoCs - - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible= SoCs - - amlogic,meson-axg-reset # Reset Controller on AXG and compatible S= oCs - - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs - - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs - - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs - - amlogic,t7-reset + oneOf: + - enum: + - amlogic,meson8b-reset # Reset Controller on Meson8b and compat= ible SoCs + - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compat= ible SoCs + - amlogic,meson-axg-reset # Reset Controller on AXG and compatib= le SoCs + - amlogic,meson-a1-reset # Reset Controller on A1 and compatible= SoCs + - amlogic,meson-s4-reset # Reset Controller on S4 and compatible= SoCs + - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs + - amlogic,t7-reset + - items: + - enum: + - amlogic,a4-reset + - amlogic,a5-reset + - const: amlogic,meson-s4-reset =20 reg: maxItems: 1 --=20 2.37.1 From nobody Thu Dec 18 07:11:53 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7E88263C8E; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250313-a4-a5-reset-v4-2-8076f684d6cf@amlogic.com> References: <20250313-a4-a5-reset-v4-0-8076f684d6cf@amlogic.com> In-Reply-To: <20250313-a4-a5-reset-v4-0-8076f684d6cf@amlogic.com> To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Zelong Dong , Kelvin Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1741856786; l=3846; i=kelvin.zhang@amlogic.com; s=20240329; h=from:subject:message-id; bh=3wgP2tWcYm0WqWBwyu5Znx0BI/LoQVm4PvQJrojr2U0=; b=F0eD24wVRcS75K+YpS2UxVOvd9oN29dHjYSiBdJgg0l1jEobSiqnwvJHvscbgYqP/VLf7gKE6 hOM2wPARKiUCHG2R53X8o/IOSQQe5Su3itFzVodcLOZJg/moM3jVfSg X-Developer-Key: i=kelvin.zhang@amlogic.com; a=ed25519; pk=pgnle7HTNvnNTcOoGejvtTC7BJT30HUNXfMHRRXSylI= X-Endpoint-Received: by B4 Relay for kelvin.zhang@amlogic.com/20240329 with auth_id=148 X-Original-From: Kelvin Zhang Reply-To: kelvin.zhang@amlogic.com From: Zelong Dong Add the device node and related header file for Amlogic A4 reset controller. Signed-off-by: Zelong Dong Link: https://lore.kernel.org/r/20240918074211.8067-3-zelong.dong@amlogic.c= om Signed-off-by: Kelvin Zhang --- arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h | 93 ++++++++++++++++++++++= ++++ arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 8 +++ 2 files changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h b/arch/arm64/bo= ot/dts/amlogic/amlogic-a4-reset.h new file mode 100644 index 0000000000000000000000000000000000000000..f6a4c90bab3cf7cfaa3c98c522b= ed5e455b73bd3 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + */ + +#ifndef __DTS_AMLOGIC_A4_RESET_H +#define __DTS_AMLOGIC_A4_RESET_H + +/* RESET0 */ +/* 0-3 */ +#define RESET_USB 4 +/* 5-6*/ +#define RESET_U2PHY22 7 +#define RESET_USBPHY20 8 +#define RESET_U2PHY21 9 +#define RESET_USB2DRD 10 +#define RESET_U2H 11 +#define RESET_LED_CTRL 12 +/* 13-31 */ + +/* RESET1 */ +#define RESET_AUDIO 32 +#define RESET_AUDIO_VAD 33 +/* 34*/ +#define RESET_DDR_APB 35 +#define RESET_DDR 36 +#define RESET_VOUT_VENC 37 +#define RESET_VOUT 38 +/* 39-47 */ +#define RESET_ETHERNET 48 +/* 49-63 */ + +/* RESET2 */ +#define RESET_DEVICE_MMC_ARB 64 +#define RESET_IRCTRL 65 +/* 66*/ +#define RESET_TS_PLL 67 +/* 68-72*/ +#define RESET_SPICC_0 73 +#define RESET_SPICC_1 74 +/* 75-79*/ +#define RESET_MSR_CLK 80 +/* 81*/ +#define RESET_SAR_ADC 82 +/* 83-87*/ +#define RESET_ACODEC 88 +/* 89-90*/ +#define RESET_WATCHDOG 91 +/* 92-95*/ + +/* RESET3 */ +/* 96-127 */ + +/* RESET4 */ +/* 128-131 */ +#define RESET_PWM_AB 132 +#define RESET_PWM_CD 133 +#define RESET_PWM_EF 134 +#define RESET_PWM_GH 135 +/* 136-137*/ +#define RESET_UART_A 138 +#define RESET_UART_B 139 +/* 140*/ +#define RESET_UART_D 141 +#define RESET_UART_E 142 +/* 143-144*/ +#define RESET_I2C_M_A 145 +#define RESET_I2C_M_B 146 +#define RESET_I2C_M_C 147 +#define RESET_I2C_M_D 148 +/* 149-151*/ +#define RESET_SDEMMC_A 152 +/* 153*/ +#define RESET_SDEMMC_C 154 +/* 155-159*/ + +/* RESET5 */ +/* 160-175*/ +#define RESET_BRG_AO_NIC_SYS 176 +/* 177*/ +#define RESET_BRG_AO_NIC_MAIN 178 +#define RESET_BRG_AO_NIC_AUDIO 179 +/* 180-183*/ +#define RESET_BRG_AO_NIC_ALL 184 +/* 185*/ +#define RESET_BRG_NIC_SDIO 186 +#define RESET_BRG_NIC_EMMC 187 +#define RESET_BRG_NIC_DSU 188 +#define RESET_BRG_NIC_CLK81 189 +#define RESET_BRG_NIC_MAIN 190 +#define RESET_BRG_NIC_ALL 191 + +#endif diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-a4.dtsi index efba8565af3cf5298f894819572d78e0c0041f71..02365494d8655f8cf97f0ffdc9a= 9566e42ab61ae 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi @@ -4,6 +4,7 @@ */ =20 #include "amlogic-a4-common.dtsi" +#include "amlogic-a4-reset.h" #include #include / { @@ -51,6 +52,13 @@ pwrc: power-controller { }; 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a=ed25519-sha256; t=1741856786; l=3877; i=kelvin.zhang@amlogic.com; s=20240329; h=from:subject:message-id; bh=ZFu/iq6Br16B1GmXZXg+n7u5XDIS+7iiJRB1TMYOhs4=; b=8WsA+Mm77eVUAT3YgjZQzAi9J3yuCVLHAYgwmSKS8l6fcCTikKBtv+PoxXMtrweg0qyrUt9n4 19h7CXmFbd3DXsUYHDxicwR7642QUCitxBuP0WfbwV/EQKeIIjb976U X-Developer-Key: i=kelvin.zhang@amlogic.com; a=ed25519; pk=pgnle7HTNvnNTcOoGejvtTC7BJT30HUNXfMHRRXSylI= X-Endpoint-Received: by B4 Relay for kelvin.zhang@amlogic.com/20240329 with auth_id=148 X-Original-From: Kelvin Zhang Reply-To: kelvin.zhang@amlogic.com From: Zelong Dong Add the device node and related header file for Amlogic A5 reset controller. Signed-off-by: Zelong Dong Link: https://lore.kernel.org/r/20240918074211.8067-4-zelong.dong@amlogic.c= om Signed-off-by: Kelvin Zhang --- arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h | 95 ++++++++++++++++++++++= ++++ arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 10 +++ 2 files changed, 105 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h b/arch/arm64/bo= ot/dts/amlogic/amlogic-a5-reset.h new file mode 100644 index 0000000000000000000000000000000000000000..cdf0f515962097c606e4c53badb= 19df7d21606ec --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + */ + +#ifndef __DTS_AMLOGIC_A5_RESET_H +#define __DTS_AMLOGIC_A5_RESET_H + +/* RESET0 */ +/* 0-3 */ +#define RESET_USB 4 +/* 5-7 */ +#define RESET_USBPHY20 8 +/* 9 */ +#define RESET_USB2DRD 10 +/* 11-31 */ + +/* RESET1 */ +#define RESET_AUDIO 32 +#define RESET_AUDIO_VAD 33 +/* 34 */ +#define RESET_DDR_APB 35 +#define RESET_DDR 36 +/* 37-40 */ +#define RESET_DSPA_DEBUG 41 +/* 42 */ +#define RESET_DSPA 43 +/* 44-46 */ +#define RESET_NNA 47 +#define RESET_ETHERNET 48 +/* 49-63 */ + +/* RESET2 */ +#define RESET_ABUS_ARB 64 +#define RESET_IRCTRL 65 +/* 66 */ +#define RESET_TS_PLL 67 +/* 68-72 */ +#define RESET_SPICC_0 73 +#define RESET_SPICC_1 74 +#define RESET_RSA 75 + +/* 76-79 */ +#define RESET_MSR_CLK 80 +#define RESET_SPIFC 81 +#define RESET_SAR_ADC 82 +/* 83-90 */ +#define RESET_WATCHDOG 91 +/* 92-95 */ + +/* RESET3 */ +/* 96-127 */ + +/* RESET4 */ +#define RESET_RTC 128 +/* 129-131 */ +#define RESET_PWM_AB 132 +#define RESET_PWM_CD 133 +#define RESET_PWM_EF 134 +#define RESET_PWM_GH 135 +/* 104-105 */ +#define RESET_UART_A 138 +#define RESET_UART_B 139 +#define RESET_UART_C 140 +#define RESET_UART_D 141 +#define RESET_UART_E 142 +/* 143*/ +#define RESET_I2C_S_A 144 +#define RESET_I2C_M_A 145 +#define RESET_I2C_M_B 146 +#define RESET_I2C_M_C 147 +#define RESET_I2C_M_D 148 +/* 149-151 */ +#define RESET_SDEMMC_A 152 +/* 153 */ +#define RESET_SDEMMC_C 154 +/* 155-159*/ + +/* RESET5 */ +/* 160-175 */ +#define RESET_BRG_AO_NIC_SYS 176 +#define RESET_BRG_AO_NIC_DSPA 177 +#define RESET_BRG_AO_NIC_MAIN 178 +#define RESET_BRG_AO_NIC_AUDIO 179 +/* 180-183 */ +#define RESET_BRG_AO_NIC_ALL 184 +#define RESET_BRG_NIC_NNA 185 +#define RESET_BRG_NIC_SDIO 186 +#define RESET_BRG_NIC_EMMC 187 +#define RESET_BRG_NIC_DSU 188 +#define RESET_BRG_NIC_SYSCLK 189 +#define RESET_BRG_NIC_MAIN 190 +#define RESET_BRG_NIC_ALL 191 + +#endif diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-a5.dtsi index 17a6316de8918f31f3f7625f2eda06a60664139a..b97e2f3091bf62f4bdaaebeaf5d= 1dfe695cfc6d5 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi @@ -4,6 +4,7 @@ */ =20 #include "amlogic-a4-common.dtsi" +#include "amlogic-a5-reset.h" #include / { cpus { @@ -48,3 +49,12 @@ pwrc: power-controller { }; }; }; + +&apb { + reset: reset-controller@2000 { + compatible =3D "amlogic,a5-reset", + "amlogic,meson-s4-reset"; + reg =3D <0x0 0x2000 0x0 0x98>; + #reset-cells =3D <1>; + }; +}; --=20 2.37.1