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[81.240.10.146]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5e816afe223sm26732a12.70.2025.03.12.16.23.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Mar 2025 16:23:20 -0700 (PDT) From: Philippe Simons To: Boris Brezillon , Rob Herring , Steven Price , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Philipp Zabel Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Andre Przywara , =?UTF-8?q?Jernej=20=C5=A0krabec?= Subject: [PATCH 1/2] drm/panfrost: Add PM runtime flags Date: Thu, 13 Mar 2025 00:23:18 +0100 Message-ID: <20250312232319.25712-2-simons.philippe@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250312232319.25712-1-simons.philippe@gmail.com> References: <20250312232319.25712-1-simons.philippe@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When the GPU is the only device attached to a single power domain, core genpd disable and enable it when gpu enter and leave runtime suspend. Some power-domain requires a sequence before disabled, and the reverse when enabled. Add PM flags for CLK and RST, and implement in panfrost_device_runtime_suspend/resume. Signed-off-by: Philippe Simons Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_device.c | 37 ++++++++++++++++++++++ drivers/gpu/drm/panfrost/panfrost_device.h | 4 +++ 2 files changed, 41 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/p= anfrost/panfrost_device.c index a45e4addcc19..189ad2ad2b32 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.c +++ b/drivers/gpu/drm/panfrost/panfrost_device.c @@ -406,11 +406,38 @@ void panfrost_device_reset(struct panfrost_device *pf= dev) static int panfrost_device_runtime_resume(struct device *dev) { struct panfrost_device *pfdev =3D dev_get_drvdata(dev); + int ret; + + if (pfdev->comp->pm_features & BIT(GPU_PM_RT_RST_ASRT)) { + ret =3D reset_control_deassert(pfdev->rstc); + if (ret) + return ret; + } + + if (pfdev->comp->pm_features & BIT(GPU_PM_RT_CLK_DIS)) { + ret =3D clk_enable(pfdev->clock); + if (ret) + goto err_clk; + + if (pfdev->bus_clock) { + ret =3D clk_enable(pfdev->bus_clock); + if (ret) + goto err_bus_clk; + } + } =20 panfrost_device_reset(pfdev); panfrost_devfreq_resume(pfdev); =20 return 0; + +err_bus_clk: + if (pfdev->comp->pm_features & BIT(GPU_PM_RT_CLK_DIS)) + clk_disable(pfdev->clock); +err_clk: + if (pfdev->comp->pm_features & BIT(GPU_PM_RT_RST_ASRT)) + reset_control_assert(pfdev->rstc); + return ret; } =20 static int panfrost_device_runtime_suspend(struct device *dev) @@ -426,6 +453,16 @@ static int panfrost_device_runtime_suspend(struct devi= ce *dev) panfrost_gpu_suspend_irq(pfdev); panfrost_gpu_power_off(pfdev); =20 + if (pfdev->comp->pm_features & BIT(GPU_PM_RT_CLK_DIS)) { + if (pfdev->bus_clock) + clk_disable(pfdev->bus_clock); + + clk_disable(pfdev->clock); + } + + if (pfdev->comp->pm_features & BIT(GPU_PM_RT_RST_ASRT)) + reset_control_assert(pfdev->rstc); + return 0; } =20 diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/p= anfrost/panfrost_device.h index cffcb0ac7c11..f372d4819262 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -36,10 +36,14 @@ enum panfrost_drv_comp_bits { * enum panfrost_gpu_pm - Supported kernel power management features * @GPU_PM_CLK_DIS: Allow disabling clocks during system suspend * @GPU_PM_VREG_OFF: Allow turning off regulators during system suspend + * @GPU_PM_RT_CLK_DIS: Allow disabling clocks during system runtime suspend + * @GPU_PM_RST_ASRT: Allow asserting the reset control during runtime susp= end */ enum panfrost_gpu_pm { GPU_PM_CLK_DIS, GPU_PM_VREG_OFF, + GPU_PM_RT_CLK_DIS, + GPU_PM_RT_RST_ASRT }; =20 struct panfrost_features { --=20 2.48.1 From nobody Thu Dec 18 17:43:58 2025 Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66B591F153D for ; Wed, 12 Mar 2025 23:23:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741821806; cv=none; b=VXZDTFxIqmRwz77GUIBNQytUUL0ZCDYTis/CBA5eKcGYoTte60FnAr1nqiS8wc2n9jBvw5bSpeG3W0/ESFxS40o7HjspuDyqk5DnE56TGPTnQ/cW/fC7PFgh59dBkCuHXIJHg3U+sxgiRFLUOuj1vpBN7LpMow0aw8USLrEP4qw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741821806; c=relaxed/simple; bh=4YZluZGJ4DEMVE+2SA7gUODIucELBWly4WYu8TV+KoA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EnPVjH3T592Mg77QjlSO+VtrhPuFYeQp/dhgm2eZnoPHfdG4dyj/gf6eHRgSn7mRQt3yCHJkuBSQh3KjXDz2XOICv6S0bgnXt4CJNShdxtgZvfGbPdp6GF4I0TY5MT2WjcEsn/799NmNjUGUL+bd7Sopjh5HtGqnGld0lOAYt4Q= ARC-Authentication-Results: i=1; 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[81.240.10.146]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5e816afe223sm26732a12.70.2025.03.12.16.23.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Mar 2025 16:23:21 -0700 (PDT) From: Philippe Simons To: Boris Brezillon , Rob Herring , Steven Price , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Philipp Zabel Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Andre Przywara , =?UTF-8?q?Jernej=20=C5=A0krabec?= Subject: [PATCH 2/2] drm/panfrost: add h616 compatible string Date: Thu, 13 Mar 2025 00:23:19 +0100 Message-ID: <20250312232319.25712-3-simons.philippe@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250312232319.25712-1-simons.philippe@gmail.com> References: <20250312232319.25712-1-simons.philippe@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tie the Allwinner compatible string to the two features bits that will toggle the clocks and the reset line whenever the power domain is changing state. Signed-off-by: Philippe Simons --- drivers/gpu/drm/panfrost/panfrost_drv.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panf= rost/panfrost_drv.c index 0f3935556ac7..f13743fe6bad 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -776,6 +776,13 @@ static const struct panfrost_compatible default_data = =3D { .pm_domain_names =3D NULL, }; =20 +static const struct panfrost_compatible allwinner_h616_data =3D { + .num_supplies =3D ARRAY_SIZE(default_supplies) - 1, + .supply_names =3D default_supplies, + .num_pm_domains =3D 1, + .pm_features =3D BIT(GPU_PM_RT_CLK_DIS) | BIT(GPU_PM_RT_RST_ASRT), +}; + static const struct panfrost_compatible amlogic_data =3D { .num_supplies =3D ARRAY_SIZE(default_supplies) - 1, .supply_names =3D default_supplies, @@ -859,6 +866,7 @@ static const struct of_device_id dt_match[] =3D { { .compatible =3D "mediatek,mt8186-mali", .data =3D &mediatek_mt8186_data= }, { .compatible =3D "mediatek,mt8188-mali", .data =3D &mediatek_mt8188_data= }, { .compatible =3D "mediatek,mt8192-mali", .data =3D &mediatek_mt8192_data= }, + { .compatible =3D "allwinner,sun50i-h616-mali", .data =3D &allwinner_h616= _data }, {} }; MODULE_DEVICE_TABLE(of, dt_match); --=20 2.48.1