From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A1CB42A82 for ; Wed, 12 Mar 2025 14:37:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790273; cv=none; b=kTCXhJJZGMEcSVOgmJx+hRF6PH5yhqLYKO+DO7XfPVsrRBszUsmLlaSF3i1UJMnJedRbWK+z4jvBW95q+aCAMAdNlbIiHefB0QS4fxwS4tOa8xJt+oEIOt/n6fgDi6eeN1WcSFdZk9bKos+0B+u151aXBDWR5Bd4sanE5nz6w8k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790273; c=relaxed/simple; bh=V0ZaSj+Spn2inI0JqfzyJrjh+Rsa6AKhAMrFK/kqgB8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ty5Yk5QOl0o78aRGHgseM+cIKelBqxYifjU34ikirT4JO6yeBHSpqB0Z9GeKtOuTf4N9Fj21weDcFKEcBbzyzGKS3yvWIX+pcJoVkwMw2aR2Admuk1p4Da+ZA44Ofc/H0gcWYfj7/SiQcYK+l8ppb9E/3JC+2QyApyM0PMLAFkc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=kr8gc1gp; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=QZIzu+3/; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="kr8gc1gp"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="QZIzu+3/" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741790270; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8s+kgyHb+rH7bNPws5A6RoZEJxeIxOWBkNJP/5UXKEw=; b=kr8gc1gp+egonbM23oXjLEMAhf23ig5fpVYT1pC5fSCNtp39pz6hKnGCCxxstner7gIQmx r6rYrHSH+509uGsiXzeUg0W6vU4YPTchFZTkpLrDQEARPVU80JOFw4jGaXI6G0Jl0voZwV 4egrMQFQNjhOtmzssJYuYG0U4yPh2uw7I1CzsDdi2m4Qje0yRgKgXPll5pdEKHpRsYUYcq pAFwi34uPLGZn3BQ/vD7KkOFxdlBNCeSTPbpgstwVxZHHl6/cngcWOTYEdp+kLv5OfYbOC lHec+svLtBT1qGaYoEsO76XaDiUNEqdzoWOBCUHCFNCDU8znVaW6P3rVhzHQUg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741790270; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8s+kgyHb+rH7bNPws5A6RoZEJxeIxOWBkNJP/5UXKEw=; b=QZIzu+3/Jf48X6I3zUQZBxgxgYeOhOKyPUn07NAA5lvZ6XJr1NNWeAFqfLUE9vCZx4TW6P KCrRnB7FVu35JTAA== To: Ingo Molnar , Dave Hansen , Borislav Petkov Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 01/20] tools/x86/kcpuid: Fix error handling Date: Wed, 12 Mar 2025 15:37:18 +0100 Message-ID: <20250312143738.458507-2-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Error handling in kcpuid is unreliable. On malloc() failures, the code prints an error then just goes on. The error messages are also printed to standard output instead of standard error. Use err() and errx() from to direct all error messages to standard error and automatically exit the program. Use err() to include the errno information, and errx() otherwise. Use warnx() for warnings. While at it, alphabetically reorder the header includes. Fixes: c6b2f240bf8d ("tools/x86: Add a kcpuid tool to show raw CPU features= ") Reported-by: Remington Brasga Closes: https://lkml.kernel.org/r/20240926223557.2048-1-rbrasga@uci.edu Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 47 +++++++++++++++++----------------- 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 1b25c0a95d3f..abfeecce5aa8 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 #define _GNU_SOURCE =20 -#include +#include +#include #include +#include #include #include -#include =20 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) #define min(a, b) (((a) < (b)) ? (a) : (b)) @@ -145,14 +146,14 @@ static bool cpuid_store(struct cpuid_range *range, u3= 2 f, int subleaf, if (!func->leafs) { func->leafs =3D malloc(sizeof(struct subleaf)); if (!func->leafs) - perror("malloc func leaf"); + err(EXIT_FAILURE, NULL); =20 func->nr =3D 1; } else { s =3D func->nr; func->leafs =3D realloc(func->leafs, (s + 1) * sizeof(*leaf)); if (!func->leafs) - perror("realloc f->leafs"); + err(EXIT_FAILURE, NULL); =20 func->nr++; } @@ -211,7 +212,7 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) =20 range =3D malloc(sizeof(struct cpuid_range)); if (!range) - perror("malloc range"); + err(EXIT_FAILURE, NULL); =20 if (input_eax & 0x80000000) range->is_ext =3D true; @@ -220,7 +221,7 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) =20 range->funcs =3D malloc(sizeof(struct cpuid_func) * idx_func); if (!range->funcs) - perror("malloc range->funcs"); + err(EXIT_FAILURE, NULL); =20 range->nr =3D idx_func; memset(range->funcs, 0, sizeof(struct cpuid_func) * idx_func); @@ -395,8 +396,8 @@ static int parse_line(char *line) return 0; =20 err_exit: - printf("Warning: wrong line format:\n"); - printf("\tline[%d]: %s\n", flines, line); + warnx("Wrong line format:\n" + "\tline[%d]: %s", flines, line); return -1; } =20 @@ -418,10 +419,8 @@ static void parse_text(void) file =3D fopen("./cpuid.csv", "r"); } =20 - if (!file) { - printf("Fail to open '%s'\n", filename); - return; - } + if (!file) + err(EXIT_FAILURE, "%s", filename); =20 while (1) { ret =3D getline(&line, &len, file); @@ -530,7 +529,7 @@ static inline struct cpuid_func *index_to_func(u32 inde= x) func_idx =3D index & 0xffff; =20 if ((func_idx + 1) > (u32)range->nr) { - printf("ERR: invalid input index (0x%x)\n", index); + warnx("Invalid input index (0x%x)", index); return NULL; } return &range->funcs[func_idx]; @@ -562,7 +561,7 @@ static void show_info(void) return; } =20 - printf("ERR: invalid input subleaf (0x%x)\n", user_sub); + warnx("Invalid input subleaf (0x%x)", user_sub); } =20 show_func(func); @@ -593,15 +592,15 @@ static void setup_platform_cpuid(void) =20 static void usage(void) { - printf("kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n" - "\t-a|--all Show both bit flags and complex bit fields info\= n" - "\t-b|--bitflags Show boolean flags only\n" - "\t-d|--detail Show details of the flag/fields (default)\n" - "\t-f|--flags Specify the cpuid csv file\n" - "\t-h|--help Show usage info\n" - "\t-l|--leaf=3Dindex Specify the leaf you want to check\n" - "\t-r|--raw Show raw cpuid data\n" - "\t-s|--subleaf=3Dsub Specify the subleaf you want to check\n" + warnx("kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n" + "\t-a|--all Show both bit flags and complex bit fields = info\n" + "\t-b|--bitflags Show boolean flags only\n" + "\t-d|--detail Show details of the flag/fields (default)\n" + "\t-f|--flags Specify the cpuid csv file\n" + "\t-h|--help Show usage info\n" + "\t-l|--leaf=3Dindex Specify the leaf you want to check\n" + "\t-r|--raw Show raw cpuid data\n" + "\t-s|--subleaf=3Dsub Specify the subleaf you want to check" ); } =20 @@ -652,7 +651,7 @@ static int parse_options(int argc, char *argv[]) user_sub =3D strtoul(optarg, NULL, 0); break; default: - printf("%s: Invalid option '%c'\n", argv[0], optopt); + warnx("Invalid option '%c'", optopt); return -1; } =20 --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A514A24BBEF for ; Wed, 12 Mar 2025 14:37:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790277; cv=none; b=YsOLgCuAw1YNOEt3eWPXnuzfFtol6qAF2gfNstkY/gq2gvD9o5tcfp3xk89K55rVn2mKXfE7lxYArtKWNZVlIi09VzJi1BIKw8CHy5xaQknuk1Ob1HBbekJvLRXOpafUxMPQx785quOD7itD0cvYP3V7j/Yiz8AYuvYUhpPAq+A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ruQW06ub" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741790273; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fBfo8AXB79SPLI7+74Hw01qjH5lduLL/N5gJi7n6n7M=; b=UyvoIAmmq5d4AzDEw17Yn3fLtsNAd+kKSiWuswXDeR/NMePT7XmVlNsX/aI+tHlGPA5s15 KPo/uOo+HHPo/SbhO1jsR07dJGyDyiQDvyqPpcmVY7e/0w2wAZGBwx5Y4Gx6N4EOk8+qMR 3dIs7Kf/bi7HkqtEdt95WPhVhAE7jzjRBSAdYmCuh3raRgg5pGQ239WNSY5Jf6cH5twCKZ whglolOqOpiOu4t9dsdHabV3JFz/UP1HryUMejrl7NW3maiptHEiXk2Kt1wYT2SJpy7YuN 8vG1j9nstI91NA9gD77T1xFyDulf1vjDTc0l1g0nPEHsZsN3mUdutaIxNCsryQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741790273; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fBfo8AXB79SPLI7+74Hw01qjH5lduLL/N5gJi7n6n7M=; b=ruQW06ubK65R5tjuR436vL10XXigHzlX714b0sxsYlqpisOneqMrByaiR/kLcaH3lkaIAW vDyIz6pRw9MI36Ag== To: Ingo Molnar , Dave Hansen , Borislav Petkov Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 02/20] tools/x86/kcpuid: Exit the program on invalid parameters Date: Wed, 12 Mar 2025 15:37:19 +0100 Message-ID: <20250312143738.458507-3-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the user passed an invalid CPUID index value through --leaf=3Dindex, kcpuid prints a warning, does nothing, then exits successfully. Transform the warning to an error, and exit the program with a proper error code. Similarly, if the user passed an invalid subleaf, kcpuid prints a warning, dumps the whole leaf, then exits successfully. Print a clear error message regarding the invalid subleaf and exit the program with the proper error code. Note, moving the "Invalid input index" message from index_to_func() to show_info() localizes error message handling to the latter, where it should be. It also allows index_to_func() to be refactored at further commits. Note, since after this commit and its parent kcpuid does not just "move on" on failures, remove the NULL parameter check plus silent exit at show_func() and show_leaf(). Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index abfeecce5aa8..8585c1009c8b 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -481,9 +481,6 @@ static void decode_bits(u32 value, struct reg_desc *rde= sc, enum cpuid_reg reg) =20 static void show_leaf(struct subleaf *leaf) { - if (!leaf) - return; - if (show_raw) { leaf_print_raw(leaf); } else { @@ -505,9 +502,6 @@ static void show_func(struct cpuid_func *func) { int i; =20 - if (!func) - return; - for (i =3D 0; i < func->nr; i++) show_leaf(&func->leafs[i]); } @@ -528,10 +522,9 @@ static inline struct cpuid_func *index_to_func(u32 ind= ex) range =3D (index & 0x80000000) ? leafs_ext : leafs_basic; func_idx =3D index & 0xffff; =20 - if ((func_idx + 1) > (u32)range->nr) { - warnx("Invalid input index (0x%x)", index); + if ((func_idx + 1) > (u32)range->nr) return NULL; - } + return &range->funcs[func_idx]; } =20 @@ -550,18 +543,19 @@ static void show_info(void) /* Only show specific leaf/subleaf info */ func =3D index_to_func(user_index); if (!func) - return; + errx(EXIT_FAILURE, "Invalid input leaf (0x%x)", user_index); =20 /* Dump the raw data also */ show_raw =3D true; =20 if (user_sub !=3D 0xFFFFFFFF) { - if (user_sub + 1 <=3D (u32)func->nr) { - show_leaf(&func->leafs[user_sub]); - return; + if (user_sub + 1 > (u32)func->nr) { + errx(EXIT_FAILURE, "Leaf 0x%x has no valid subleaf =3D 0x%x", + user_index, user_sub); } =20 - warnx("Invalid input subleaf (0x%x)", user_sub); + show_leaf(&func->leafs[user_sub]); + return; } =20 show_func(func); --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 517DC24F5A4 for ; Wed, 12 Mar 2025 14:37:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790278; cv=none; b=NaFTsle9JH718U5GnjJfjaJ8qesyi1nj4g74oC1r5ryru7m6CZcPsx//6B7EwqPuu/JAod6Bog+OIQlGrpjYbRNX3YakJjrstFjkYOn6dkvrXlqwZ+JcsHPeTALsk3nlOdJY/Wn/u+jvzA+IsUpIE/Ze83g6f/GgeRd9Gj18dkY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790278; c=relaxed/simple; bh=4dO68SUYqAkwEY7UThLrLaHl7z6KmwFajAtnun0lg3c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lqdbHv8DgqMA2N9Ifl9ENzSSSm0Z/jBVAS9AaC0kSan6PE3rfIcvmsot4CokF+3I3aDRPxBHrNyZ9t0SdUxdLX3Le6Ax8lFPnwskla93tKNkdX3bEL2EJMScbzZkD2W1V2F32lU0OLh+n9VK92KHUo5tKNuOnW2jsTN2RDE1+rs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=hDttEXTT; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=73tlTTqJ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="hDttEXTT"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="73tlTTqJ" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 03/20] tools/x86/kcpuid: Simplify usage() handling Date: Wed, 12 Mar 2025 15:37:20 +0100 Message-ID: <20250312143738.458507-4-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor usage() to accept an exit code parameter and exit the program after usage output. This streamlines its callers' code paths. Remove the "Invalid option" error message since getopt_long(3) already emits a similar message by default. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 37 +++++++++++++++------------------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 8585c1009c8b..b760c5730c89 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -10,6 +10,7 @@ =20 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) #define min(a, b) (((a) < (b)) ? (a) : (b)) +#define __noreturn __attribute__((__noreturn__)) =20 typedef unsigned int u32; typedef unsigned long long u64; @@ -584,17 +585,17 @@ static void setup_platform_cpuid(void) leafs_ext =3D setup_cpuid_range(0x80000000); } =20 -static void usage(void) +static void __noreturn usage(int exit_code) { - warnx("kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n" - "\t-a|--all Show both bit flags and complex bit fields = info\n" - "\t-b|--bitflags Show boolean flags only\n" - "\t-d|--detail Show details of the flag/fields (default)\n" - "\t-f|--flags Specify the cpuid csv file\n" - "\t-h|--help Show usage info\n" - "\t-l|--leaf=3Dindex Specify the leaf you want to check\n" - "\t-r|--raw Show raw cpuid data\n" - "\t-s|--subleaf=3Dsub Specify the subleaf you want to check" + errx(exit_code, "kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n" + "\t-a|--all Show both bit flags and complex bit fields i= nfo\n" + "\t-b|--bitflags Show boolean flags only\n" + "\t-d|--detail Show details of the flag/fields (default)\n" + "\t-f|--flags Specify the cpuid csv file\n" + "\t-h|--help Show usage info\n" + "\t-l|--leaf=3Dindex Specify the leaf you want to check\n" + "\t-r|--raw Show raw cpuid data\n" + "\t-s|--subleaf=3Dsub Specify the subleaf you want to check" ); } =20 @@ -610,7 +611,7 @@ static struct option opts[] =3D { { NULL, 0, NULL, 0 } }; =20 -static int parse_options(int argc, char *argv[]) +static void parse_options(int argc, char *argv[]) { int c; =20 @@ -630,9 +631,7 @@ static int parse_options(int argc, char *argv[]) user_csv =3D optarg; break; case 'h': - usage(); - exit(1); - break; + usage(EXIT_SUCCESS); case 'l': /* main leaf */ user_index =3D strtoul(optarg, NULL, 0); @@ -645,11 +644,8 @@ static int parse_options(int argc, char *argv[]) user_sub =3D strtoul(optarg, NULL, 0); break; default: - warnx("Invalid option '%c'", optopt); - return -1; - } - - return 0; + usage(EXIT_FAILURE); + } } =20 /* @@ -662,8 +658,7 @@ static int parse_options(int argc, char *argv[]) */ int main(int argc, char *argv[]) { - if (parse_options(argc, argv)) - return -1; + parse_options(argc, argv); =20 /* Setup the cpuid leafs of current platform */ setup_platform_cpuid(); --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABA04250C0E for ; Wed, 12 Mar 2025 14:38:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790282; cv=none; b=owEa93Lr2y+PHfm5KDB6RhnMeelbP9kvTKMDQ7SebbyHj1L9QktUuTupVw4nkXVo/FpFnKXtezObYiTzodSfl2UsukQKXIybWMTrwgNDQMqYD37C1bj90XWEbRPAzs8Cl6nvjeSim0vNHw7Zs1qaj5oGybx6Xibn5z2/10v5b4c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790282; c=relaxed/simple; bh=TTRr9DIck2vTMBqimKMjA0AXz1JdWsyxH9ey+9dIcDc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lQkbKw7UAHWqtNvQE2u2psZh6t29p6V8dRPg25D5OSQh7hJBy+CUzOOVCxrRDBaVzI4SXndCt/VgFQSByRGlGnUtBaRTdnZT3kguG3bBUn3Bee0b0B+eU7kSksNXRuk+DvbTWiO5dPvO4PF5zqYxVC0Q8sTMCQZbbIA440+FCBg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=4GS+qQpf; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=cYij7p6v; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="4GS+qQpf"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="cYij7p6v" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 04/20] tools/x86/kcpuid: Save CPUID output in an array Date: Wed, 12 Mar 2025 15:37:21 +0100 Message-ID: <20250312143738.458507-5-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For each CPUID leaf/subleaf query, save the output in an output[] array instead of spelling it out using EAX to EDX variables. This allows the CPUID output to be accessed programmatically instead of calling decode_bits() four times. Loop-based access also allows "kcpuid --detail" to print the correct output register names in next commit. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index b760c5730c89..dfabc0a56507 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -51,7 +51,7 @@ static const char * const reg_names[] =3D { struct subleaf { u32 index; u32 sub; - u32 eax, ebx, ecx, edx; + u32 output[NR_REGS]; struct reg_desc info[NR_REGS]; }; =20 @@ -119,11 +119,11 @@ static void leaf_print_raw(struct subleaf *leaf) if (leaf->sub =3D=3D 0) printf("0x%08x: subleafs:\n", leaf->index); =20 - printf(" %2d: EAX=3D0x%08x, EBX=3D0x%08x, ECX=3D0x%08x, EDX=3D0x%08x\n", - leaf->sub, leaf->eax, leaf->ebx, leaf->ecx, leaf->edx); + printf(" %2d: EAX=3D0x%08x, EBX=3D0x%08x, ECX=3D0x%08x, EDX=3D0x%08x\n",= leaf->sub, + leaf->output[0], leaf->output[1], leaf->output[2], leaf->output[3= ]); } else { - printf("0x%08x: EAX=3D0x%08x, EBX=3D0x%08x, ECX=3D0x%08x, EDX=3D0x%08x\n= ", - leaf->index, leaf->eax, leaf->ebx, leaf->ecx, leaf->edx); + printf("0x%08x: EAX=3D0x%08x, EBX=3D0x%08x, ECX=3D0x%08x, EDX=3D0x%08x\n= ", leaf->index, + leaf->output[0], leaf->output[1], leaf->output[2], leaf->output[3= ]); } } =20 @@ -163,10 +163,10 @@ static bool cpuid_store(struct cpuid_range *range, u3= 2 f, int subleaf, =20 leaf->index =3D f; leaf->sub =3D subleaf; - leaf->eax =3D a; - leaf->ebx =3D b; - leaf->ecx =3D c; - leaf->edx =3D d; + leaf->output[R_EAX] =3D a; + leaf->output[R_EBX] =3D b; + leaf->output[R_ECX] =3D c; + leaf->output[R_EDX] =3D d; =20 return false; } @@ -490,10 +490,8 @@ static void show_leaf(struct subleaf *leaf) leaf->index, leaf->sub); } =20 - decode_bits(leaf->eax, &leaf->info[R_EAX], R_EAX); - decode_bits(leaf->ebx, &leaf->info[R_EBX], R_EBX); - decode_bits(leaf->ecx, &leaf->info[R_ECX], R_ECX); - decode_bits(leaf->edx, &leaf->info[R_EDX], R_EDX); + for (int i =3D R_EAX; i < NR_REGS; i++) + decode_bits(leaf->output[i], &leaf->info[i], i); =20 if (!show_raw && show_details) printf("\n"); --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA8A72517B8 for ; Wed, 12 Mar 2025 14:38:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790285; cv=none; b=dH7qmNHgB+C2ABlQO8sO7YAn+ldyAIuZmEHhJiPt6tiqhzOpKAIQS57laZVVG/00keDxOnq9vGfUYtS7e0E52XnixuGgaOBkBWv9At6LB12y6XtF5EqomZoAvfiDHdsEY+gfCDwpW4lbfLhv+tHNKNK87IgeA+qwDMVA+ZNDuLM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790285; c=relaxed/simple; bh=a0P0gl/D62qUuSPbpqJlT0jpvngBvF4VU9cToBKlJjM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JcrPZ212rttTSQhZ/7oWRmST8NKMWuOc2ii5LCQAzntsLFkO84plR0Utx3V8h3lpxbqQRb9inSvxvTte4RWpBrNWNWpDBzWfbVF3DCCUEfxjixpSoaMOkaKDH/uwqHj4NTKM9O0AgwQHkLJ7iqQeEv9UqZxogTEEE+MUNG9NFko= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=CAhTpxAV; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=P7QQxuGL; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="CAhTpxAV"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="P7QQxuGL" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 05/20] tools/x86/kcpuid: Print correct CPUID output register names Date: Wed, 12 Mar 2025 15:37:22 +0100 Message-ID: <20250312143738.458507-6-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" kcpuid --all --detail claims that all bits belong to ECX, in the form of the header CPUID_${leaf}_ECX[${subleaf}]. Print the correct register name for all CPUID output. kcpuid --detail also dumps the raw register value if a leaf/subleaf is covered in the CSV file, but a certain output register within it is not covered by any CSV entry. Since register names are now properly printed, and since the CSV file has become exhaustive using x86-cpuid-db, remove that value dump as it pollutes the output. While at it, rename decode_bits() to show_reg(). This makes it match its show_range(), show_leaf() and show_reg_header() counterparts. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index dfabc0a56507..d518a13e4386 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -436,20 +436,12 @@ static void parse_text(void) fclose(file); } =20 - -/* Decode every eax/ebx/ecx/edx */ -static void decode_bits(u32 value, struct reg_desc *rdesc, enum cpuid_reg = reg) +static void show_reg(const struct reg_desc *rdesc, u32 value) { - struct bits_desc *bdesc; + const struct bits_desc *bdesc; int start, end, i; u32 mask; =20 - if (!rdesc->nr) { - if (show_details) - printf("\t %s: 0x%08x\n", reg_names[reg], value); - return; - } - for (i =3D 0; i < rdesc->nr; i++) { bdesc =3D &rdesc->descs[i]; =20 @@ -480,18 +472,21 @@ static void decode_bits(u32 value, struct reg_desc *r= desc, enum cpuid_reg reg) } } =20 +static void show_reg_header(bool has_entries, u32 leaf, u32 subleaf, const= char *reg_name) +{ + if (show_details && has_entries) + printf("CPUID_0x%x_%s[0x%x]:\n", leaf, reg_name, subleaf); +} + static void show_leaf(struct subleaf *leaf) { - if (show_raw) { + if (show_raw) leaf_print_raw(leaf); - } else { - if (show_details) - printf("CPUID_0x%x_ECX[0x%x]:\n", - leaf->index, leaf->sub); - } =20 - for (int i =3D R_EAX; i < NR_REGS; i++) - decode_bits(leaf->output[i], &leaf->info[i], i); + for (int i =3D R_EAX; i < NR_REGS; i++) { + show_reg_header((leaf->info[i].nr > 0), leaf->index, leaf->sub, reg_name= s[i]); + show_reg(&leaf->info[i], leaf->output[i]); + } =20 if (!show_raw && show_details) printf("\n"); --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B63C3252913 for ; Wed, 12 Mar 2025 14:38:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790288; cv=none; b=EQ9A5TaQ/ECDzG1kwhS+aitRgj2S+ZDfl/YWhFQquu2WN1gyTSG3gJSPSAO7WYYNpSLUabJ07NYI6EYKiRhNjh6L3kIT2K5bAsVUVL48GyBqfmkP2hP0zQbwLdluRxyfden4ZdXOhLCdf0zm9GWJYadqR2tOaMr0QeJDSO/vUM8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790288; c=relaxed/simple; bh=Ushz4JR4gBXwlY3rF7uYB5PnO6rgziwqmj7rQX1GkQw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Rc0GuUdc3cob2xvohE8m/zB3Td8OrJ2lIwR7V4Bzg2LBcEnaIPgmnzBstZ7vvFZ+ZG3P6qWUPhHP0jX/hMsQ4Q8CVE4Qe+F0FeVRDjQ3WvJRk3kuSO7Phnsm6TNyLjDcJ72PK2WjllFfW6RFUDxjJtVBxqSchrqkVH3QoZ0FO/g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=33tg6GIJ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=XFXTnEw/; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="33tg6GIJ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="XFXTnEw/" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 06/20] tools/x86/kcpuid: Remove unused local variable Date: Wed, 12 Mar 2025 15:37:23 +0100 Message-ID: <20250312143738.458507-7-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The local variable "index" is written to, but is not read from anywhere. Remove it. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index d518a13e4386..a89da2af98e9 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -181,10 +181,6 @@ static void raw_dump_range(struct cpuid_range *range) =20 for (f =3D 0; (int)f < range->nr; f++) { struct cpuid_func *func =3D &range->funcs[f]; - u32 index =3D f; - - if (range->is_ext) - index +=3D 0x80000000; =20 /* Skip leaf without valid items */ if (!func->nr) --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E4BE253F06 for ; Wed, 12 Mar 2025 14:38:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790291; cv=none; b=IIf/N/ncQRY1SeGP3ql6NUc82YTVrFuaOFTUbWP0Fs0yaBC3ly6D2+2STlh/VqNoBmv3nQqi/GvXobMosdf+TPIF+Vua3m1UZiKB/PceUMxul09+I8sf/LwTu3rmkIKWbRmm020T+51hSwvFCkY3kZaa8wPcP8XZ4mVfGzvCX6Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790291; c=relaxed/simple; bh=3y7y/+TG/coMCKwSXE98CIgHpa9wr5XS5fRq2IuwG2k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BUiRo2uGzCirQY71b2PQ3fbMAHMFf/K8PP8KQiQU8ahvl0L/4aMIHolPX6diEkdLKR97gYoeuQDuDxfr5ajTV/WsXyzamwUJhfczU/IeHWdgDUhpsqmpI0/CWEqfpeMvhGcBJiDkky1J/pkTH2IG8xorC4X9EpKVEO9PMqjMkEQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=nLgW9qHB; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=sOidJnru; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="nLgW9qHB"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="sOidJnru" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 07/20] tools/x86/kcpuid: Remove unused global variable Date: Wed, 12 Mar 2025 15:37:24 +0100 Message-ID: <20250312143738.458507-8-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The global variable "is_amd" is written to, but is not read from anywhere. Remove it. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index a89da2af98e9..908f0de2d4f0 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -79,7 +79,6 @@ struct cpuid_range { */ struct cpuid_range *leafs_basic, *leafs_ext; =20 -static bool is_amd; static bool show_details; static bool show_raw; static bool show_flags_only =3D true; @@ -559,16 +558,6 @@ static void show_info(void) =20 static void setup_platform_cpuid(void) { - u32 eax, ebx, ecx, edx; - - /* Check vendor */ - eax =3D ebx =3D ecx =3D edx =3D 0; - cpuid(&eax, &ebx, &ecx, &edx); - - /* "htuA" */ - if (ebx =3D=3D 0x68747541) - is_amd =3D true; - /* Setup leafs for the basic and extended range */ leafs_basic =3D setup_cpuid_range(0x0); leafs_ext =3D setup_cpuid_range(0x80000000); --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84652254AF8 for ; Wed, 12 Mar 2025 14:38:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790294; cv=none; b=PcJEhQQVG0WYrmz2/HIXsGMY7yIFR7gY6RmcEpr5aHoPSrxxZ9Xc3goOrUmYEDcru4y4fJ4Suc/3EiahSzPoI5vKJE9VTU+kWk7LVSwNcEXBfkQXbVlu8kMijXF4EFMmFt8hdYmkboRBWTi62MoqcxaMK48/7Rb9ZRE2GurPZu4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790294; c=relaxed/simple; bh=U3FmrnZ/4s402XkrjUkox44nIGjdsllUxaqR4EvG7sE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=V9ywctNAbCgcJh3XDTU9V13Va7WM6VZ+trmwr19fuzFIB1AIxLDESbeAJrEwG9bu2W+lDSKpsoi1LP9gfSZ+2DskOoaaCwjcPti/kMpuAvhL0C8EIUdchTjAguHnZRVIT/xjW136r9gMwYigVymnmWgmS589zuNwO2e7uNE7I5U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=HWsz2x7p; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=gaTeWF0A; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="HWsz2x7p"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="gaTeWF0A" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 08/20] tools/x86/kcpuid: Set function return type to void Date: Wed, 12 Mar 2025 15:37:25 +0100 Message-ID: <20250312143738.458507-9-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" parse_line() returns an integer but its caller ignored it. Change the function signature to return void. While at it, adjust some of the "Skip line" comments for readability. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 908f0de2d4f0..1db2c8d7cf27 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -277,7 +277,7 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) * 0, 0, EAX, 31:0, max_basic_leafs, Max input value for supported = subleafs * 1, 0, ECX, 0, sse3, Streaming SIMD Extensions 3(SSE3) */ -static int parse_line(char *line) +static void parse_line(char *line) { char *str; int i; @@ -307,7 +307,7 @@ static int parse_line(char *line) =20 /* Skip comments and NULL line */ if (line[0] =3D=3D '#' || line[0] =3D=3D '\n') - return 0; + return; =20 strncpy(buffer, line, 511); buffer[511] =3D 0; @@ -330,16 +330,15 @@ static int parse_line(char *line) else range =3D leafs_basic; =20 - index &=3D 0x7FFFFFFF; /* Skip line parsing for non-existing indexes */ + index &=3D 0x7FFFFFFF; if ((int)index >=3D range->nr) - return -1; + return; =20 + /* Skip line parsing if the index CPUID output is all zero */ func =3D &range->funcs[index]; - - /* Return if the index has no valid item on this platform */ if (!func->nr) - return 0; + return; =20 /* subleaf */ buf =3D tokens[1]; @@ -352,11 +351,11 @@ static int parse_line(char *line) subleaf_start =3D strtoul(start, NULL, 0); subleaf_end =3D min(subleaf_end, (u32)(func->nr - 1)); if (subleaf_start > subleaf_end) - return 0; + return; } else { subleaf_start =3D subleaf_end; if (subleaf_start > (u32)(func->nr - 1)) - return 0; + return; } =20 /* register */ @@ -389,12 +388,11 @@ static int parse_line(char *line) strcpy(bdesc->simp, strtok(tokens[4], " \t")); strcpy(bdesc->detail, tokens[5]); } - return 0; + return; =20 err_exit: warnx("Wrong line format:\n" "\tline[%d]: %s", flines, line); - return -1; } =20 /* Parse csv file, and construct the array of all leafs and subleafs */ --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8209842A82 for ; Wed, 12 Mar 2025 14:38:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790297; cv=none; b=VQ+9Z1NqI5ImNrT3s4bHcsDgk5FDxvK1W5jI9vuNtZhgKHuHDbwt+CXuLz0tn+RiDAyMs/1gSlVIktCbbKLxynHIL3v12LFUS0767EdRlq/IYntsKI5bDWO741Twni46E55qVhRB6Cs9fBCWJPYkUJr1zGPCWQkTTsSGz33SxZg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790297; c=relaxed/simple; bh=hlJEINp0MWs4PvmYX5e/esVtPDzXEBFZZKKS3C7B3kc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nEOdBNnLDY2xJHdDNcqAsup643dhVdsL5KPRb9CA30bL4PDK1Mb+qbtCo+TTl9W4xPyrBe6ax71X7hQUE7+5QLcqzg2xWapm+ySvn6fU1xyieuovjo43x4zDAdJICBHYaf6oD2Sut3ZpbNhhnJ72M0HhyE2J90seIc/pR4f5U/Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=3D53Gs1V; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=DfzXUwPi; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="3D53Gs1V"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="DfzXUwPi" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741790294; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=057rGxAD1cvihnAjC3OKTQL5jAwYl0z9M+EMf1Xwooo=; b=3D53Gs1Vzh7UdxEt5UcKoRZ+Tz8Mo8hLXe5d0zdCKJNoKSrksD/h/T/2dgvC4Q1KuRGNRs qtftTUYY3dv/gsHVZqxVvxwVn7tSgz+YtO7+ll8t0hflEImeBeMejWj8fXom/186OKw6bS zAQsKju6RGOgyGkBVromiiga4Esw420/064RPg2JCMkFQwrNotoLOasFCW7wGCTyOsRRxT 00Mb6Vv6NZMS3jgTxWWHVKnLsS9JCaY8W5TWTj4QnhS++UiWhr4ebJcNyG3FLXj0Ah2c8O h2LlhsoWsJ46dfzFNlqhnHJHdy13GDFejVhycJtAeR5IaRCYmFyzDDXBsVlK+Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741790294; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=057rGxAD1cvihnAjC3OKTQL5jAwYl0z9M+EMf1Xwooo=; b=DfzXUwPiAEvTGvKf71u0DWThQ1gIkVc8ygfoHY+KQBKzmFDsTVIIl8UwItFrP8Xih5J8wU XNutiK9k2Qg8WOAw== To: Ingo Molnar , Dave Hansen , Borislav Petkov Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 09/20] tools/x86/kcpuid: Use C99-style for loops Date: Wed, 12 Mar 2025 15:37:26 +0100 Message-ID: <20250312143738.458507-10-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since commit e8c07082a810 ("Kbuild: move to -std=3Dgnu11") and the kernel allows C99-style variable declarations inside of a for() loop. Adjust the kcpuid code accordingly. Note, this helps readability as some of the kcpuid functions have a huge list of variable declarations on top. Note, remove the empty lines before cpuid() invocations as it is clearer to have their parameter initialization and the actual call in one block. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 52 ++++++++++++++-------------------- 1 file changed, 21 insertions(+), 31 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 1db2c8d7cf27..79deb506b349 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -172,13 +172,10 @@ static bool cpuid_store(struct cpuid_range *range, u3= 2 f, int subleaf, =20 static void raw_dump_range(struct cpuid_range *range) { - u32 f; - int i; - printf("%s Leafs :\n", range->is_ext ? "Extended" : "Basic"); printf("=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"); =20 - for (f =3D 0; (int)f < range->nr; f++) { + for (u32 f =3D 0; (int)f < range->nr; f++) { struct cpuid_func *func =3D &range->funcs[f]; =20 /* Skip leaf without valid items */ @@ -186,7 +183,7 @@ static void raw_dump_range(struct cpuid_range *range) continue; =20 /* First item is the main leaf, followed by all subleafs */ - for (i =3D 0; i < func->nr; i++) + for (int i =3D 0; i < func->nr; i++) leaf_print_raw(&func->leafs[i]); } } @@ -194,15 +191,14 @@ static void raw_dump_range(struct cpuid_range *range) #define MAX_SUBLEAF_NUM 64 struct cpuid_range *setup_cpuid_range(u32 input_eax) { - u32 max_func, idx_func, subleaf, max_subleaf; - u32 eax, ebx, ecx, edx, f =3D input_eax; struct cpuid_range *range; - bool allzero; + u32 max_func, idx_func; + u32 eax, ebx, ecx, edx; =20 eax =3D input_eax; ebx =3D ecx =3D edx =3D 0; - cpuid(&eax, &ebx, &ecx, &edx); + max_func =3D eax; idx_func =3D (max_func & 0xffff) + 1; =20 @@ -222,20 +218,21 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) range->nr =3D idx_func; memset(range->funcs, 0, sizeof(struct cpuid_func) * idx_func); =20 - for (; f <=3D max_func; f++) { - eax =3D f; - subleaf =3D ecx =3D 0; + for (u32 f =3D input_eax; f <=3D max_func; f++) { + u32 max_subleaf =3D MAX_SUBLEAF_NUM; + bool allzero; =20 + eax =3D f; + ecx =3D 0; cpuid(&eax, &ebx, &ecx, &edx); - allzero =3D cpuid_store(range, f, subleaf, eax, ebx, ecx, edx); + + allzero =3D cpuid_store(range, f, 0, eax, ebx, ecx, edx); if (allzero) continue; =20 if (!has_subleafs(f)) continue; =20 - max_subleaf =3D MAX_SUBLEAF_NUM; - /* * Some can provide the exact number of subleafs, * others have to be tried (0xf) @@ -253,13 +250,12 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) if (f =3D=3D 0x80000026) max_subleaf =3D 5; =20 - for (subleaf =3D 1; subleaf < max_subleaf; subleaf++) { + for (u32 subleaf =3D 1; subleaf < max_subleaf; subleaf++) { eax =3D f; ecx =3D subleaf; - cpuid(&eax, &ebx, &ecx, &edx); - allzero =3D cpuid_store(range, f, subleaf, - eax, ebx, ecx, edx); + + allzero =3D cpuid_store(range, f, subleaf, eax, ebx, ecx, edx); if (allzero) continue; } @@ -280,12 +276,10 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) static void parse_line(char *line) { char *str; - int i; struct cpuid_range *range; struct cpuid_func *func; struct subleaf *leaf; u32 index; - u32 sub; char buffer[512]; char *buf; /* @@ -312,7 +306,7 @@ static void parse_line(char *line) strncpy(buffer, line, 511); buffer[511] =3D 0; str =3D buffer; - for (i =3D 0; i < 5; i++) { + for (int i =3D 0; i < 5; i++) { tokens[i] =3D strtok(str, ","); if (!tokens[i]) goto err_exit; @@ -378,7 +372,7 @@ static void parse_line(char *line) bit_end =3D strtoul(end, NULL, 0); bit_start =3D (start) ? strtoul(start, NULL, 0) : bit_end; =20 - for (sub =3D subleaf_start; sub <=3D subleaf_end; sub++) { + for (u32 sub =3D subleaf_start; sub <=3D subleaf_end; sub++) { leaf =3D &func->leafs[sub]; reg =3D &leaf->info[reg_index]; bdesc =3D ®->descs[reg->nr++]; @@ -432,10 +426,10 @@ static void parse_text(void) static void show_reg(const struct reg_desc *rdesc, u32 value) { const struct bits_desc *bdesc; - int start, end, i; + int start, end; u32 mask; =20 - for (i =3D 0; i < rdesc->nr; i++) { + for (int i =3D 0; i < rdesc->nr; i++) { bdesc =3D &rdesc->descs[i]; =20 start =3D bdesc->start; @@ -487,17 +481,13 @@ static void show_leaf(struct subleaf *leaf) =20 static void show_func(struct cpuid_func *func) { - int i; - - for (i =3D 0; i < func->nr; i++) + for (int i =3D 0; i < func->nr; i++) show_leaf(&func->leafs[i]); } =20 static void show_range(struct cpuid_range *range) { - int i; - - for (i =3D 0; i < range->nr; i++) + for (int i =3D 0; i < range->nr; i++) show_func(&range->funcs[i]); } =20 --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6CA5256C62 for ; Wed, 12 Mar 2025 14:38:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790300; cv=none; b=FF3c0DzDE3aL360cCpOok4ROwQIJtuJWc3Ks3RbMGMeTricV7C5QemQ3V/P9YqUbZmMO793pDiNcIj6U1c4OtjlTxwGGq2orR3vgAr1LtyCZYVH5aP1SowA4BNlktC12dy6CCFmXvJm4oBsJdmH5F5jYdAhN0duRR6wLFkd2VeE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790300; c=relaxed/simple; bh=BKQD6k60Mnq8kNsJxtQIlNwtJHS5ZuWqFdDwFc62AC0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bKajSjyB2fGQQxJJznvJT1A1E84D+BxWOdT3rrnlBff6b+yAcZBv1mL70zD6iv5f+n1L1CPchYqsiA/BwE24bSjG9nrEhmlFIM3Y4TXq5iLGA0gc2PQOd/T0JLbxfjxmTLHJEmdHhcZNKrE7o1xmgHlD4/8zRwCpvqgj5yB0ty0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Q+J2aYyN; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=P2c23a/P; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Q+J2aYyN"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="P2c23a/P" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741790297; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=x1DtEHn1El6g4W3dtqLn/pJd+l9oe/iYWXMyy19sLw4=; b=Q+J2aYyN7NMNco3qY/pAcrAl/JecapdipVZeNG8yQUxRXe5Lia7SiprTW4fi0S6PnwVFPZ 2H32+r3fVvVdtBSMBUFEDU28sRlLR/YKEa6kbyg1vjWR894tHlWUUg5RMS6H36h3gAHddf 50YbP6dGUW3Or8OdQqHoqagAAeVeB1bSyz9GyvIh3WCgVjnT87bAGJRPgB62W2AHaQK7Tw z5H9h8XLgLVN9VfJnbT6sQHoSGl9am/+BG0FDoOlIGJH6TjDYR/MiiO/7YNPSt0c0Wiofi dx0grNliMN8HjziHxRWPCWp8bd0+17b6bIpq9r8sQMS8gNCnI257XkhEEIRajg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741790297; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=x1DtEHn1El6g4W3dtqLn/pJd+l9oe/iYWXMyy19sLw4=; b=P2c23a/Ps80uPaW4pUcALjnbUdz0jeGqv0KOg3yrgPOkYfg0qCQQPZ05BkPaR/tl6SKN+n T7pLrN1uen3B0cBg== To: Ingo Molnar , Dave Hansen , Borislav Petkov Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 10/20] tools/x86/kcpuid: Use intrinsics Date: Wed, 12 Mar 2025 15:37:27 +0100 Message-ID: <20250312143738.458507-11-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the __cpuid_count() intrinsic, provided by GCC and LLVM, instead of rolling a manual version. Both of the kernel's minimum required GCC version (5.1) and LLVM version (13.0.1) supports it, and it is heavily used across standard Linux user-space tooling. This also makes the CPUID call sites more readable. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 37 ++++++++++++++-------------------- 1 file changed, 15 insertions(+), 22 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 79deb506b349..0dbd93ab652a 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #define _GNU_SOURCE =20 +#include #include #include #include @@ -86,16 +87,16 @@ static u32 user_index =3D 0xFFFFFFFF; static u32 user_sub =3D 0xFFFFFFFF; static int flines; =20 -static inline void cpuid(u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) -{ - /* ecx is often an input as well as an output. */ - asm volatile("cpuid" - : "=3Da" (*eax), - "=3Db" (*ebx), - "=3Dc" (*ecx), - "=3Dd" (*edx) - : "0" (*eax), "2" (*ecx)); -} +/* + * Force using __cpuid_count() instead of __cpuid(). The + * latter leaves ECX uninitialized, which can break CPUID queries. + */ + +#define cpuid(leaf, a, b, c, d) \ + __cpuid_count(leaf, 0, a, b, c, d) + +#define cpuid_count(leaf, subleaf, a, b, c, d) \ + __cpuid_count(leaf, subleaf, a, b, c, d) =20 static inline bool has_subleafs(u32 f) { @@ -195,12 +196,7 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) u32 max_func, idx_func; u32 eax, ebx, ecx, edx; =20 - eax =3D input_eax; - ebx =3D ecx =3D edx =3D 0; - cpuid(&eax, &ebx, &ecx, &edx); - - max_func =3D eax; - idx_func =3D (max_func & 0xffff) + 1; + cpuid(input_eax, max_func, ebx, ecx, edx); =20 range =3D malloc(sizeof(struct cpuid_range)); if (!range) @@ -211,6 +207,7 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) else range->is_ext =3D false; =20 + idx_func =3D (max_func & 0xffff) + 1; range->funcs =3D malloc(sizeof(struct cpuid_func) * idx_func); if (!range->funcs) err(EXIT_FAILURE, NULL); @@ -222,9 +219,7 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) u32 max_subleaf =3D MAX_SUBLEAF_NUM; bool allzero; =20 - eax =3D f; - ecx =3D 0; - cpuid(&eax, &ebx, &ecx, &edx); + cpuid(f, eax, ebx, ecx, edx); =20 allzero =3D cpuid_store(range, f, 0, eax, ebx, ecx, edx); if (allzero) @@ -251,9 +246,7 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) max_subleaf =3D 5; =20 for (u32 subleaf =3D 1; subleaf < max_subleaf; subleaf++) { - eax =3D f; - ecx =3D subleaf; - cpuid(&eax, &ebx, &ecx, &edx); + cpuid_count(f, subleaf, eax, ebx, ecx, edx); =20 allzero =3D cpuid_store(range, f, subleaf, eax, ebx, ecx, edx); if (allzero) --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0BE724E00B for ; Wed, 12 Mar 2025 14:38:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790303; cv=none; b=j531nWTDOuoUKyKmxdICeoonFK/eQak9SGryI94mtdZiQwO1UlGqNT5CJXd+/5jexvJ7t+137Ake1OBpcHhQ5521esb24YB1CqiwtoA6EALlaPRLwpP446R9bov8/hDK0iaIiDAssRXDOwNCr5JVeJqKAKaeidwQvxELu0rlNVE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790303; c=relaxed/simple; bh=dIBtuB0ReHZ0I98KRhCaiisrdZFa1qbIYTsgucwFjWw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mVCc3gbXldlfabLv5N0kACVCBOGMk38MyQPLnvtO1G/YUArU9bMKVz4uTNYdM8t13lXeOEPf7k0L3PMFiSqcnWoTiKzktVKAtgvA7jJcUAm5jO4bAxrEAVE8YywBFN3+VAiTUu0B/jPUFNTGiqA9oYEQpoUX8XrL8NMBjjGrxgk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=fzwa36yW; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=o/xKhOEm; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="fzwa36yW"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="o/xKhOEm" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 11/20] tools/x86/kcpuid: Refactor CPUID range handling for future expansion Date: Wed, 12 Mar 2025 15:37:28 +0100 Message-ID: <20250312143738.458507-12-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The kcpuid code assumes only two CPUID index ranges, standard (0x0...) and extended (0x80000000...). Since additional CPUID index ranges will be added in further commits, replace the "is_ext" boolean with enumeration-based range classification. Collect all CPUID ranges in a structured array and introduce helper macros to iterate over it. Use such helpers throughout the code. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 100 +++++++++++++++++++-------------- 1 file changed, 59 insertions(+), 41 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 0dbd93ab652a..00a3b7a8953c 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -66,19 +66,50 @@ struct cpuid_func { int nr; }; =20 +enum range_index { + RANGE_STD =3D 0, /* Standard */ + RANGE_EXT =3D 0x80000000, /* Extended */ +}; + +#define CPUID_INDEX_MASK 0x80000000 +#define CPUID_FUNCTION_MASK (~CPUID_INDEX_MASK) + struct cpuid_range { /* array of main leafs */ struct cpuid_func *funcs; /* number of valid leafs */ int nr; - bool is_ext; + enum range_index index; }; =20 -/* - * basic: basic functions range: [0... ] - * ext: extended functions range: [0x80000000... ] - */ -struct cpuid_range *leafs_basic, *leafs_ext; +static struct cpuid_range ranges[] =3D { + { .index =3D RANGE_STD, }, + { .index =3D RANGE_EXT, }, +}; + +static char *range_to_str(struct cpuid_range *range) +{ + switch (range->index) { + case RANGE_STD: return "Standard"; + case RANGE_EXT: return "Extended"; + default: return NULL; + } +} + +#define for_each_cpuid_range(range) \ + for (unsigned int i =3D 0; i < ARRAY_SIZE(ranges) && ((range) =3D &ranges= [i]); i++) + +struct cpuid_range *index_to_cpuid_range(u32 index) +{ + struct cpuid_range *range; + + for_each_cpuid_range(range) { + if (range->index =3D=3D (index & CPUID_INDEX_MASK)) + return range; + } + + return NULL; +} =20 static bool show_details; static bool show_raw; @@ -173,7 +204,7 @@ static bool cpuid_store(struct cpuid_range *range, u32 = f, int subleaf, =20 static void raw_dump_range(struct cpuid_range *range) { - printf("%s Leafs :\n", range->is_ext ? "Extended" : "Basic"); + printf("%s Leafs :\n", range_to_str(range)); printf("=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"); =20 for (u32 f =3D 0; (int)f < range->nr; f++) { @@ -190,22 +221,12 @@ static void raw_dump_range(struct cpuid_range *range) } =20 #define MAX_SUBLEAF_NUM 64 -struct cpuid_range *setup_cpuid_range(u32 input_eax) +void setup_cpuid_range(struct cpuid_range *range) { - struct cpuid_range *range; u32 max_func, idx_func; u32 eax, ebx, ecx, edx; =20 - cpuid(input_eax, max_func, ebx, ecx, edx); - - range =3D malloc(sizeof(struct cpuid_range)); - if (!range) - err(EXIT_FAILURE, NULL); - - if (input_eax & 0x80000000) - range->is_ext =3D true; - else - range->is_ext =3D false; + cpuid(range->index, max_func, ebx, ecx, edx); =20 idx_func =3D (max_func & 0xffff) + 1; range->funcs =3D malloc(sizeof(struct cpuid_func) * idx_func); @@ -215,7 +236,7 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) range->nr =3D idx_func; memset(range->funcs, 0, sizeof(struct cpuid_func) * idx_func); =20 - for (u32 f =3D input_eax; f <=3D max_func; f++) { + for (u32 f =3D range->index; f <=3D max_func; f++) { u32 max_subleaf =3D MAX_SUBLEAF_NUM; bool allzero; =20 @@ -254,8 +275,6 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) } =20 } - - return range; } =20 /* @@ -312,13 +331,13 @@ static void parse_line(char *line) /* index/main-leaf */ index =3D strtoull(tokens[0], NULL, 0); =20 - if (index & 0x80000000) - range =3D leafs_ext; - else - range =3D leafs_basic; + /* Skip line parsing if it's not covered by known ranges */ + range =3D index_to_cpuid_range(index); + if (!range) + return; =20 /* Skip line parsing for non-existing indexes */ - index &=3D 0x7FFFFFFF; + index &=3D CPUID_FUNCTION_MASK; if ((int)index >=3D range->nr) return; =20 @@ -489,9 +508,11 @@ static inline struct cpuid_func *index_to_func(u32 ind= ex) struct cpuid_range *range; u32 func_idx; =20 - range =3D (index & 0x80000000) ? leafs_ext : leafs_basic; - func_idx =3D index & 0xffff; + range =3D index_to_cpuid_range(index); + if (!range) + return NULL; =20 + func_idx =3D index & 0xffff; if ((func_idx + 1) > (u32)range->nr) return NULL; =20 @@ -500,12 +521,13 @@ static inline struct cpuid_func *index_to_func(u32 in= dex) =20 static void show_info(void) { + struct cpuid_range *range; struct cpuid_func *func; =20 if (show_raw) { /* Show all of the raw output of 'cpuid' instr */ - raw_dump_range(leafs_basic); - raw_dump_range(leafs_ext); + for_each_cpuid_range(range) + raw_dump_range(range); return; } =20 @@ -533,15 +555,8 @@ static void show_info(void) } =20 printf("CPU features:\n=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n\n"); - show_range(leafs_basic); - show_range(leafs_ext); -} - -static void setup_platform_cpuid(void) -{ - /* Setup leafs for the basic and extended range */ - leafs_basic =3D setup_cpuid_range(0x0); - leafs_ext =3D setup_cpuid_range(0x80000000); + for_each_cpuid_range(range) + show_range(range); } =20 static void __noreturn usage(int exit_code) @@ -617,10 +632,13 @@ static void parse_options(int argc, char *argv[]) */ int main(int argc, char *argv[]) { + struct cpuid_range *range; + parse_options(argc, argv); =20 /* Setup the cpuid leafs of current platform */ - setup_platform_cpuid(); + for_each_cpuid_range(range) + setup_cpuid_range(range); =20 /* Read and parse the 'cpuid.csv' */ parse_text(); --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFBC82571B5 for ; Wed, 12 Mar 2025 14:38:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790306; cv=none; b=R75iyBHca8RFIGTmwQ/NZxedFUlms16l6SQJQIZYFF/iAjGd9D/AOzdFQsStZr0MEX12Ua6IlFB/g+wuB62edgUDrgrgsWOikpbhZIt/pTotjPCWH5hJOtzldMuOuEY42QRJDH4io15VKxA8wKVNIjgCj8FW09nAJbv7PgVqpYY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790306; c=relaxed/simple; bh=Adf+zN0jZwi1RYzCLoCEtx2M+jktmNOuFEJOe/QrH74=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ttnqPPqA/c0h0t3LIB7DFE7EXzmIvD4DULF99NMiuLFnqVaQUWnuLc/KRF6QarQ6BR7OPW6/6tIsDcu+NZbspb3/VSjJ9dVVMNYn7lI/nMmukvkUcNMd/dstNe5bz3T0gdOA0WxxM/ER5YcdtDt9aSt/DSH5oG38OrDTXR/BS1c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Edt61PlO; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=dZ6WyitZ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Edt61PlO"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="dZ6WyitZ" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741790303; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NLdZ2DXpJDx8yhYu4D1b1KQ/w9DYKov9AN7jy9kVAKA=; b=Edt61PlOLARx2gizMoOJKFGoW5gIFTA2eu9pOyw+fumbHpWIJm694RefvfsxFccfoNNAv3 YKbYp6txF7vD7T8tsEeT/ehpMFzNTo8stg87oPCJfiJ5YuS/I0gvRVnVLw1pRa5YMW4cw/ xWR9O7GfTt5cZmOB6xPiOQwYPKAjREjy3+81dmMTfTAPDtGlSDsU0e+MF+ejukzCW+irsK +cFJ0Rnv7JNJTpz1neSzBjuoWd0/u082pjLve17y8s+aAgXww/9pXtCSg9ZSTAHD8ENs/n voWsrk3iPC1AB/3ZBNKm0KArH/9RLIlrezCejPOf1lXwLQ7ZIJblpoLlrjNnyw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741790303; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NLdZ2DXpJDx8yhYu4D1b1KQ/w9DYKov9AN7jy9kVAKA=; b=dZ6WyitZ1Wm2v97P+gtzH5VNw0NxhC0BSVWtNoTAHajjaxuX4YdBp/4VFRbdj1kfBLOrzK V+UTQBfr+jd7z8BA== To: Ingo Molnar , Dave Hansen , Borislav Petkov Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 12/20] tools/x86/kcpuid: Extend CPUID index mask macro Date: Wed, 12 Mar 2025 15:37:29 +0100 Message-ID: <20250312143738.458507-13-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the CPUID index mask macro from 0x80000000 to 0xffff0000. This accommodates the Transmeta (0x80860000) and Centaur (0xc0000000) index ranges which will be later added. This also automatically sets CPUID_FUNCTION_MASK to 0x0000ffff, which is the actual correct value. Use that macro, instead of the 0xffff literal where appropriate. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 00a3b7a8953c..0ba0d440482c 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -71,7 +71,7 @@ enum range_index { RANGE_EXT =3D 0x80000000, /* Extended */ }; =20 -#define CPUID_INDEX_MASK 0x80000000 +#define CPUID_INDEX_MASK 0xffff0000 #define CPUID_FUNCTION_MASK (~CPUID_INDEX_MASK) =20 struct cpuid_range { @@ -173,7 +173,7 @@ static bool cpuid_store(struct cpuid_range *range, u32 = f, int subleaf, * Cut off vendor-prefix from CPUID function as we're using it as an * index into ->funcs. */ - func =3D &range->funcs[f & 0xffff]; + func =3D &range->funcs[f & CPUID_FUNCTION_MASK]; =20 if (!func->leafs) { func->leafs =3D malloc(sizeof(struct subleaf)); @@ -228,7 +228,7 @@ void setup_cpuid_range(struct cpuid_range *range) =20 cpuid(range->index, max_func, ebx, ecx, edx); =20 - idx_func =3D (max_func & 0xffff) + 1; + idx_func =3D (max_func & CPUID_FUNCTION_MASK) + 1; range->funcs =3D malloc(sizeof(struct cpuid_func) * idx_func); if (!range->funcs) err(EXIT_FAILURE, NULL); @@ -512,7 +512,7 @@ static inline struct cpuid_func *index_to_func(u32 inde= x) if (!range) return NULL; =20 - func_idx =3D index & 0xffff; + func_idx =3D index & CPUID_FUNCTION_MASK; if ((func_idx + 1) > (u32)range->nr) return NULL; =20 --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A9552571BA for ; Wed, 12 Mar 2025 14:38:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790309; cv=none; b=nsTXCy+gnc1iypdwYAatdCFAmq2Ye/R3DL5plC7h0W6tx9j46npOye6i4LGDi+QLLMap/kApx8j1JKo5QvpVmsfTRtHUIn9l1YaN4V9B3FRwi93FQvh3i7IddB284njr1Nt7uH9KstMe0Cnn4K0gcvUb1zEr7LJ9dAYpgrFcBO4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790309; c=relaxed/simple; bh=qWrm+5sdJIBIXXCJ0kSnHvIZfC2T8C6svN5rvbnkpiU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W3tilvyy/6li1KQygnmI7vfGqspHE8pHNGBw96TQPyO8usDjSKHJWpqQAb21jSMtIop+OW33vLr6XTkL3VMfNXiFHQvg+744Yv8uWjD66bSSfPZCDwmmRwQ//Jf/S5Vyb4a/fcjQwRD9u90LKffQi6VZyrvxksw5g0waZdEE8YI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=22jyB/2Y; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=86+UfwIM; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="22jyB/2Y"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="86+UfwIM" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741790306; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ug2XSIyXFgWR3Oi6TV0HW8fjI9rdKYlILIEfOFbHB+I=; b=22jyB/2YvlJ7N88O9EWHxH3ZqXoHCJ2D/0TSBDNVSGoIX0cWoo8fbB0p4wb27fPQwAojEy t0aIXaYfufOM87LWFciTgGZYeBfiP1cuxcRvz+R6T+/OHsE7zF7fkfo82PkPGyKCu02RWe Tzz0K9QVg8QkJAep2rAY/W/4gjMSL9IiTaVHIlzDHdUXwsCepTO6d9l/SSCwe0bSAoI7we WfEyswTCJJS5KGsuozxKAvstm71vX9LxfNPXTXA8YGGLnMFDequMNzZRrhvQ6k0/1Y2Cnb 8Di44YQvW3WcHUWkjU4oWNtEEaY/LLWR4b4FfHowyQECxW4U+smPT3FDF7QB2w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741790306; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ug2XSIyXFgWR3Oi6TV0HW8fjI9rdKYlILIEfOFbHB+I=; b=86+UfwIMMCbu8kbwfmJdLyonVYC37kNHyERvDwx1NYoghaDIW38BMzqSVQk5Kjm2n5mOp3 yJWlolQ5SuM13gDQ== To: Ingo Molnar , Dave Hansen , Borislav Petkov Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 13/20] tools/x86/kcpuid: Consolidate index validity checks Date: Wed, 12 Mar 2025 15:37:30 +0100 Message-ID: <20250312143738.458507-14-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Let index_to_cpuid_range() return a range only if the passed index is within that range's maximum supported function on the CPU. This avoids repeating the same index validity check at both setup_cpuid_range() and index_to_func(). Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 0ba0d440482c..fff6db1119ed 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -101,10 +101,12 @@ static char *range_to_str(struct cpuid_range *range) =20 struct cpuid_range *index_to_cpuid_range(u32 index) { + u32 func_idx =3D index & CPUID_FUNCTION_MASK; + u32 range_idx =3D index & CPUID_INDEX_MASK; struct cpuid_range *range; =20 for_each_cpuid_range(range) { - if (range->index =3D=3D (index & CPUID_INDEX_MASK)) + if (range->index =3D=3D range_idx && (u32)range->nr > func_idx) return range; } =20 @@ -331,16 +333,14 @@ static void parse_line(char *line) /* index/main-leaf */ index =3D strtoull(tokens[0], NULL, 0); =20 - /* Skip line parsing if it's not covered by known ranges */ + /* + * Skip line parsing if the index is not covered by known-valid + * CPUID ranges on this CPU. + */ range =3D index_to_cpuid_range(index); if (!range) return; =20 - /* Skip line parsing for non-existing indexes */ - index &=3D CPUID_FUNCTION_MASK; - if ((int)index >=3D range->nr) - return; - /* Skip line parsing if the index CPUID output is all zero */ func =3D &range->funcs[index]; if (!func->nr) @@ -505,17 +505,13 @@ static void show_range(struct cpuid_range *range) =20 static inline struct cpuid_func *index_to_func(u32 index) { + u32 func_idx =3D index & CPUID_FUNCTION_MASK; struct cpuid_range *range; - u32 func_idx; =20 range =3D index_to_cpuid_range(index); if (!range) return NULL; =20 - func_idx =3D index & CPUID_FUNCTION_MASK; - if ((func_idx + 1) > (u32)range->nr) - return NULL; - return &range->funcs[func_idx]; } =20 --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F0BE25744D for ; Wed, 12 Mar 2025 14:38:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790312; cv=none; b=lJ7o1EZ+k5aQ4P8kHtATxEZroVVRZNURetOVnh0m1YKDgaEBBhO1JdAzeJ/sg9Rnk5TdTIjqqXuUpdyribevGyAniKZT9x1QZRHyOsit5vVtGXHL5VNR23BOb+5VMMAZukiOzVHJtg/q24EYI9FsNOH2ERa6rWIjfLjjGOnN91o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790312; c=relaxed/simple; bh=8walHUFNWDLqCeWRlbjXXE83sOY+KDfDUfwaXtESxaY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WnD0KFvTfmgqqcAurSSb9nJyeub1v/X0cEUnVody1cOtIkWfgZWXeLI724xF4hULWzlLw9nESQKg+IS+NEnu+sFCERKE4ylGwOOt//oMmIHH0fW/M5zvfWr5tUTEyTxQZEOO8LmfDwX8v7ZQrCosnQ3ta2v31JCdSrR8jBNYpAY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Vfq8PRtN; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=8y/xeWBp; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Vfq8PRtN"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="8y/xeWBp" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741790309; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tmWYZzE0Ec0LLqlWFnpScuQL44sfE7yciPPWV7UJ68A=; b=Vfq8PRtNUI8PbCxLRnBbtkifqOUyxFLg0krixa8LhSh3kT+QfHdaEQaTOq8GkPyeEpH1Ce lIbI4e900DnQHaRHgx+Icz2DrrZTm6d0tREsFwiRy/1J+fHQbat5tvazm7tMUF5raL30nk MiAD2hu2GAEXXvt5WHWgVoGMTPkmJe0Kj2BccGesz1ALbHC1eP6LmsSoGsag8Y0FuMnqGr NXjJEiFS63sfqngnRDQGK68gjoGRgO/DxlKSX1sZQ+qVEwvadNprhzIYPVH6IEHc5v7E9P qhRc+JHqCptvaiZowfLYt94hur8kJSERODCBM7/nqinS8fuE2k/95QCRyuVbyQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741790309; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tmWYZzE0Ec0LLqlWFnpScuQL44sfE7yciPPWV7UJ68A=; b=8y/xeWBp4BhhBJZjxpstc/p9rjWPrKRCWBIkmBoITaGVjHtIaHtKuBukyeTrCm7gackoi2 /06xS/Y0drGExjDA== To: Ingo Molnar , Dave Hansen , Borislav Petkov Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 14/20] tools/x86/kcpuid: Filter valid CPUID ranges Date: Wed, 12 Mar 2025 15:37:31 +0100 Message-ID: <20250312143738.458507-15-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Next commits will introduce vendor-specific CPUID ranges like Transmeta's 0x8086000 range and Centaur's 0xc0000000. Initially explicit vendor detection was implemented, but it turned out to be not strictly necessary. As Dave Hansen noted, even established tools like cpuid(1) just tries all ranges indices, and see if the CPU responds back with something sensible. Do something similar at setup_cpuid_range(). Query the range's index, and check the maximum range function value returned. If it's within an expected interval of [range_index, range_index + MAX_RANGE_INDEX_OFFSET], accept the range as valid and further query its leaves. Set MAX_RANGE_INDEX_OFFSET to a heuristic of 0xff. That should be sensible enough since all the ranges covered by x86-cpuid-db XML database are: 0x00000000 0x00000023 0x40000000 0x40000000 0x80000000 0x80000026 0x80860000 0x80860007 0xc0000000 0xc0000001 At setup_cpuid_range(), if the range's returned maximum function was not sane, mark it as invalid by setting its number of leaves, range->nr, to zero. Introduce the for_each_valid_cpuid_range() iterator instead of sprinkling "range->nr !=3D 0" checks throughout the code. Suggested-by: Dave Hansen Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 38 +++++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 10 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index fff6db1119ed..94a5926d00d0 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -96,8 +96,13 @@ static char *range_to_str(struct cpuid_range *range) } } =20 -#define for_each_cpuid_range(range) \ - for (unsigned int i =3D 0; i < ARRAY_SIZE(ranges) && ((range) =3D &ranges= [i]); i++) +#define __for_each_cpuid_range(range, __condition) \ + for (unsigned int i =3D 0; \ + i < ARRAY_SIZE(ranges) && ((range) =3D &ranges[i]) && (__condition);= \ + i++) + +#define for_each_valid_cpuid_range(range) __for_each_cpuid_range(range, (r= ange)->nr !=3D 0) +#define for_each_cpuid_range(range) __for_each_cpuid_range(range, true) =20 struct cpuid_range *index_to_cpuid_range(u32 index) { @@ -105,7 +110,7 @@ struct cpuid_range *index_to_cpuid_range(u32 index) u32 range_idx =3D index & CPUID_INDEX_MASK; struct cpuid_range *range; =20 - for_each_cpuid_range(range) { + for_each_valid_cpuid_range(range) { if (range->index =3D=3D range_idx && (u32)range->nr > func_idx) return range; } @@ -223,20 +228,32 @@ static void raw_dump_range(struct cpuid_range *range) } =20 #define MAX_SUBLEAF_NUM 64 +#define MAX_RANGE_INDEX_OFFSET 0xff void setup_cpuid_range(struct cpuid_range *range) { - u32 max_func, idx_func; + u32 max_func, range_funcs_sz; u32 eax, ebx, ecx, edx; =20 cpuid(range->index, max_func, ebx, ecx, edx); =20 - idx_func =3D (max_func & CPUID_FUNCTION_MASK) + 1; - range->funcs =3D malloc(sizeof(struct cpuid_func) * idx_func); + /* + * If the CPUID range's maximum function value is garbage, then it + * is not recognized by this CPU. Set the range's number of valid + * leaves to zero so that for_each_valid_cpu_range() can ignore it. + */ + if (max_func < range->index || max_func > (range->index + MAX_RANGE_INDEX= _OFFSET)) { + range->nr =3D 0; + return; + } + + range->nr =3D (max_func & CPUID_FUNCTION_MASK) + 1; + range_funcs_sz =3D range->nr * sizeof(struct cpuid_func); + + range->funcs =3D malloc(range_funcs_sz); if (!range->funcs) err(EXIT_FAILURE, NULL); =20 - range->nr =3D idx_func; - memset(range->funcs, 0, sizeof(struct cpuid_func) * idx_func); + memset(range->funcs, 0, range_funcs_sz); =20 for (u32 f =3D range->index; f <=3D max_func; f++) { u32 max_subleaf =3D MAX_SUBLEAF_NUM; @@ -342,6 +359,7 @@ static void parse_line(char *line) return; =20 /* Skip line parsing if the index CPUID output is all zero */ + index &=3D CPUID_FUNCTION_MASK; func =3D &range->funcs[index]; if (!func->nr) return; @@ -522,7 +540,7 @@ static void show_info(void) =20 if (show_raw) { /* Show all of the raw output of 'cpuid' instr */ - for_each_cpuid_range(range) + for_each_valid_cpuid_range(range) raw_dump_range(range); return; } @@ -551,7 +569,7 @@ static void show_info(void) } =20 printf("CPU features:\n=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n\n"); - for_each_cpuid_range(range) + for_each_valid_cpuid_range(range) show_range(range); } =20 --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 963A22580C6 for ; Wed, 12 Mar 2025 14:38:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790315; cv=none; b=Jzq2pjz0UntuayQYguQGpfkC+xlPdQaXyWFOlMZ7o9VsmCb9pSIywTr9C0GQESZKxDCgu/fPhMXY/dvqq/mi5UAOFjDC0qTEXjsFmZw+Kbl1AjQFJnvxPnQ7dx296offFVhH7yAP7VA31hGow2ch+XmM8d0jEnNjD0yhjEFIVmU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790315; c=relaxed/simple; bh=UsnpezwpD+qZnATw5ahEcRX4gvJjC41VMOm1eA78W/k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LE4wv/mTTVDN3hIovofPw8taQertA4ZSHzmb4V2DsYD2LEVmRRy0JPBcCR7qG5Ard6YMLHfT4brXPRs1HWjgdBrkPbvpuol4b00ub2/prLpV8J6FYnwMnHXAvt8XNxnxx0dDM3rWbgXSAo3EjKsxlK4LXze5JRwfNIz2wlazmPI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=sOj7qFDL; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=/Wg0uvn7; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="sOj7qFDL"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="/Wg0uvn7" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 15/20] tools/x86/kcpuid: Define Transmeta and Centaur index ranges Date: Wed, 12 Mar 2025 15:37:32 +0100 Message-ID: <20250312143738.458507-16-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Explicitly define the CPUID index ranges for Transmeta (0x80860000) and Centaur/Zhaoxin (0xc0000000). Without these explicit definitions, their respective CPUID indices would be skipped during CSV bitfield parsing. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 94a5926d00d0..12a4e245b15f 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -69,6 +69,8 @@ struct cpuid_func { enum range_index { RANGE_STD =3D 0, /* Standard */ RANGE_EXT =3D 0x80000000, /* Extended */ + RANGE_TSM =3D 0x80860000, /* Transmeta */ + RANGE_CTR =3D 0xc0000000, /* Centaur/Zhaoxin */ }; =20 #define CPUID_INDEX_MASK 0xffff0000 @@ -85,6 +87,8 @@ struct cpuid_range { static struct cpuid_range ranges[] =3D { { .index =3D RANGE_STD, }, { .index =3D RANGE_EXT, }, + { .index =3D RANGE_TSM, }, + { .index =3D RANGE_CTR, }, }; =20 static char *range_to_str(struct cpuid_range *range) @@ -92,6 +96,8 @@ static char *range_to_str(struct cpuid_range *range) switch (range->index) { case RANGE_STD: return "Standard"; case RANGE_EXT: return "Extended"; + case RANGE_TSM: return "Transmeta"; + case RANGE_CTR: return "Centaur"; default: return NULL; } } --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88DDB251783 for ; Wed, 12 Mar 2025 14:38:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790321; cv=none; b=PezVzfhuY4cSJQU9tr6KFAtITv04VYI3t93WxfJ20b6yFq9oIzRJxEbsq9AVob7cV9CXhmZDCfaVZbDXrqi+cgfHuQ1QqRNEDjBdG7siW0MSsQB7PsokOqIdEHfwP8tPbLjp1k5WDoAzLZirNDUzw9jw+3LHg0WN87pVyrQobk4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741790321; c=relaxed/simple; bh=NTnMZadmr4Sj90nKyJAUR7lTtfyM8C/bU6ghbsZB9eY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=blGqMO0tXYWW728xg1wQOUMQmXWaX9MVmay9zy1U07nLhnvpYboPoCniStQCNihthkpA5K7XhIshpgWz0umQegBw5G33EzVuVRQKtcBk6PZH4l0VprHy65JfGTyxomc933IwBCTpW8TXIDWX6065KqS1+GXwGxjtp8da9eafZ3c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=BcFSCPJ3; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=wX2nliCf; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="BcFSCPJ3"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="wX2nliCf" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 16/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.0 Date: Wed, 12 Mar 2025 15:37:33 +0100 Message-ID: <20250312143738.458507-17-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update kcpuid's CSV file to version v2.0, as generated by x86-cpuid-db. Summary of the v2.0 changes: * Introduce the leaves: - Leaf 0x00000003, Transmeta Processor serial number - Leaf 0x80860000, Transmeta max leaf number + CPU vendor ID - Leaf 0x80860001, Transmeta extended CPU information - Leaf 0x80860002, Transmeta Code Morphing Software (CMS) enumeration - Leaf 0x80860003 =3D> 0x80860006, Transmeta CPU information string - Leaf 0x80860007, Transmeta "live" CPU information - Leaf 0xc0000000, Centaur/Zhaoxin's max leaf number - Leaf 0xc0000001, Centaur/Zhaoxin's extended CPU features * Add a 0x prefix for leaves 0x0 to 0x9. This maintains consistency with the rest of the CSV entries. * Add the new bitfields: - Leaf 0x7: nmi_src, NMI-source reporting - Leaf 0x80000001: e_base_type and e_mmx (Transmeta) * Update the section headers for leaves 0x80000000 and 0x80000005 to indicate that they are also valid for Transmeta. Signed-off-by: Ahmed S. Darwish Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.0/CHANGELOG.r= st --- Notes: Leaf 0x3, being not unique to Transmeta, is handled at the generated CSV file v2.3 update, later in this patch queue. =20 Leaf 0x80000001 EDX:23 bit, e_mmx, is also available on AMD. A bugfix is already merged at x86-cpuid-db's -tip for that, and it will be part of the project's upcoming v2.4 release.: =20 https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/commit/65fff25daa41 tools/arch/x86/kcpuid/cpuid.csv | 648 +++++++++++++++++++------------- 1 file changed, 382 insertions(+), 266 deletions(-) diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.= csv index d751eb8585d0..d0f7159f99ba 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,5 +1,5 @@ # SPDX-License-Identifier: CC0-1.0 -# Generator: x86-cpuid-db v1.0 +# Generator: x86-cpuid-db v2.0 =20 # # Auto-generated file. @@ -12,297 +12,306 @@ # Leaf 0H # Maximum standard leaf number + CPU vendor string =20 - 0, 0, eax, 31:0, max_std_leaf , Highest = cpuid standard leaf supported - 0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vend= or ID string bytes 0 - 3 - 0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vend= or ID string bytes 8 - 11 - 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vend= or ID string bytes 4 - 7 + 0x0, 0, eax, 31:0, max_std_leaf , Highest = cpuid standard leaf supported + 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vend= or ID string bytes 0 - 3 + 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vend= or ID string bytes 8 - 11 + 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vend= or ID string bytes 4 - 7 =20 # Leaf 1H # CPU FMS (Family/Model/Stepping) + standard feature flags =20 - 1, 0, eax, 3:0, stepping , Stepping= ID - 1, 0, eax, 7:4, base_model , Base CPU= model ID - 1, 0, eax, 11:8, base_family_id , Base CPU= family ID - 1, 0, eax, 13:12, cpu_type , CPU type - 1, 0, eax, 19:16, ext_model , Extended= CPU model ID - 1, 0, eax, 27:20, ext_family , Extended= CPU family ID - 1, 0, ebx, 7:0, brand_id , Brand in= dex - 1, 0, ebx, 15:8, clflush_size , CLFLUSH = instruction cache line size - 1, 0, ebx, 23:16, n_logical_cpu , Logical = CPU (HW threads) count - 1, 0, ebx, 31:24, local_apic_id , Initial = local APIC physical ID - 1, 0, ecx, 0, pni , Streamin= g SIMD Extensions 3 (SSE3) - 1, 0, ecx, 1, pclmulqdq , PCLMULQD= Q instruction support - 1, 0, ecx, 2, dtes64 , 64-bit D= S save area - 1, 0, ecx, 3, monitor , MONITOR/= MWAIT support - 1, 0, ecx, 4, ds_cpl , CPL Qual= ified Debug Store - 1, 0, ecx, 5, vmx , Virtual = Machine Extensions - 1, 0, ecx, 6, smx , Safer Mo= de Extensions - 1, 0, ecx, 7, est , Enhanced= Intel SpeedStep - 1, 0, ecx, 8, tm2 , Thermal = Monitor 2 - 1, 0, ecx, 9, ssse3 , Suppleme= ntal SSE3 - 1, 0, ecx, 10, cid , L1 Conte= xt ID - 1, 0, ecx, 11, sdbg , Sillicon= Debug - 1, 0, ecx, 12, fma , FMA exte= nsions using YMM state - 1, 0, ecx, 13, cx16 , CMPXCHG1= 6B instruction support - 1, 0, ecx, 14, xtpr , xTPR Upd= ate Control - 1, 0, ecx, 15, pdcm , Perfmon = and Debug Capability - 1, 0, ecx, 17, pcid , Process-= context identifiers - 1, 0, ecx, 18, dca , Direct C= ache Access - 1, 0, ecx, 19, sse4_1 , SSE4.1 - 1, 0, ecx, 20, sse4_2 , SSE4.2 - 1, 0, ecx, 21, x2apic , X2APIC s= upport - 1, 0, ecx, 22, movbe , MOVBE in= struction support - 1, 0, ecx, 23, popcnt , POPCNT i= nstruction support - 1, 0, ecx, 24, tsc_deadline_timer , APIC tim= er one-shot operation - 1, 0, ecx, 25, aes , AES inst= ructions - 1, 0, ecx, 26, xsave , XSAVE (a= nd related instructions) support - 1, 0, ecx, 27, osxsave , XSAVE (a= nd related instructions) are enabled by OS - 1, 0, ecx, 28, avx , AVX inst= ructions support - 1, 0, ecx, 29, f16c , Half-pre= cision floating-point conversion support - 1, 0, ecx, 30, rdrand , RDRAND i= nstruction support - 1, 0, ecx, 31, guest_status , System i= s running as guest; (para-)virtualized system - 1, 0, edx, 0, fpu , Floating= -Point Unit on-chip (x87) - 1, 0, edx, 1, vme , Virtual-= 8086 Mode Extensions - 1, 0, edx, 2, de , Debuggin= g Extensions - 1, 0, edx, 3, pse , Page Siz= e Extension - 1, 0, edx, 4, tsc , Time Sta= mp Counter - 1, 0, edx, 5, msr , Model-Sp= ecific Registers (RDMSR and WRMSR support) - 1, 0, edx, 6, pae , Physical= Address Extensions - 1, 0, edx, 7, mce , Machine = Check Exception - 1, 0, edx, 8, cx8 , CMPXCHG8= B instruction - 1, 0, edx, 9, apic , APIC on-= chip - 1, 0, edx, 11, sep , SYSENTER= , SYSEXIT, and associated MSRs - 1, 0, edx, 12, mtrr , Memory T= ype Range Registers - 1, 0, edx, 13, pge , Page Glo= bal Extensions - 1, 0, edx, 14, mca , Machine = Check Architecture - 1, 0, edx, 15, cmov , Conditio= nal Move Instruction - 1, 0, edx, 16, pat , Page Att= ribute Table - 1, 0, edx, 17, pse36 , Page Siz= e Extension (36-bit) - 1, 0, edx, 18, pn , Processo= r Serial Number - 1, 0, edx, 19, clflush , CLFLUSH = instruction - 1, 0, edx, 21, dts , Debug St= ore - 1, 0, edx, 22, acpi , Thermal = monitor and clock control - 1, 0, edx, 23, mmx , MMX inst= ructions - 1, 0, edx, 24, fxsr , FXSAVE a= nd FXRSTOR instructions - 1, 0, edx, 25, sse , SSE inst= ructions - 1, 0, edx, 26, sse2 , SSE2 ins= tructions - 1, 0, edx, 27, ss , Self Sno= op - 1, 0, edx, 28, ht , Hyper-th= reading - 1, 0, edx, 29, tm , Thermal = Monitor - 1, 0, edx, 30, ia64 , Legacy I= A-64 (Itanium) support bit, now resreved - 1, 0, edx, 31, pbe , Pending = Break Enable + 0x1, 0, eax, 3:0, stepping , Stepping= ID + 0x1, 0, eax, 7:4, base_model , Base CPU= model ID + 0x1, 0, eax, 11:8, base_family_id , Base CPU= family ID + 0x1, 0, eax, 13:12, cpu_type , CPU type + 0x1, 0, eax, 19:16, ext_model , Extended= CPU model ID + 0x1, 0, eax, 27:20, ext_family , Extended= CPU family ID + 0x1, 0, ebx, 7:0, brand_id , Brand in= dex + 0x1, 0, ebx, 15:8, clflush_size , CLFLUSH = instruction cache line size + 0x1, 0, ebx, 23:16, n_logical_cpu , Logical = CPU (HW threads) count + 0x1, 0, ebx, 31:24, local_apic_id , Initial = local APIC physical ID + 0x1, 0, ecx, 0, pni , Streamin= g SIMD Extensions 3 (SSE3) + 0x1, 0, ecx, 1, pclmulqdq , PCLMULQD= Q instruction support + 0x1, 0, ecx, 2, dtes64 , 64-bit D= S save area + 0x1, 0, ecx, 3, monitor , MONITOR/= MWAIT support + 0x1, 0, ecx, 4, ds_cpl , CPL Qual= ified Debug Store + 0x1, 0, ecx, 5, vmx , Virtual = Machine Extensions + 0x1, 0, ecx, 6, smx , Safer Mo= de Extensions + 0x1, 0, ecx, 7, est , Enhanced= Intel SpeedStep + 0x1, 0, ecx, 8, tm2 , Thermal = Monitor 2 + 0x1, 0, ecx, 9, ssse3 , Suppleme= ntal SSE3 + 0x1, 0, ecx, 10, cid , L1 Conte= xt ID + 0x1, 0, ecx, 11, sdbg , Sillicon= Debug + 0x1, 0, ecx, 12, fma , FMA exte= nsions using YMM state + 0x1, 0, ecx, 13, cx16 , CMPXCHG1= 6B instruction support + 0x1, 0, ecx, 14, xtpr , xTPR Upd= ate Control + 0x1, 0, ecx, 15, pdcm , Perfmon = and Debug Capability + 0x1, 0, ecx, 17, pcid , Process-= context identifiers + 0x1, 0, ecx, 18, dca , Direct C= ache Access + 0x1, 0, ecx, 19, sse4_1 , SSE4.1 + 0x1, 0, ecx, 20, sse4_2 , SSE4.2 + 0x1, 0, ecx, 21, x2apic , X2APIC s= upport + 0x1, 0, ecx, 22, movbe , MOVBE in= struction support + 0x1, 0, ecx, 23, popcnt , POPCNT i= nstruction support + 0x1, 0, ecx, 24, tsc_deadline_timer , APIC tim= er one-shot operation + 0x1, 0, ecx, 25, aes , AES inst= ructions + 0x1, 0, ecx, 26, xsave , XSAVE (a= nd related instructions) support + 0x1, 0, ecx, 27, osxsave , XSAVE (a= nd related instructions) are enabled by OS + 0x1, 0, ecx, 28, avx , AVX inst= ructions support + 0x1, 0, ecx, 29, f16c , Half-pre= cision floating-point conversion support + 0x1, 0, ecx, 30, rdrand , RDRAND i= nstruction support + 0x1, 0, ecx, 31, guest_status , System i= s running as guest; (para-)virtualized system + 0x1, 0, edx, 0, fpu , Floating= -Point Unit on-chip (x87) + 0x1, 0, edx, 1, vme , Virtual-= 8086 Mode Extensions + 0x1, 0, edx, 2, de , Debuggin= g Extensions + 0x1, 0, edx, 3, pse , Page Siz= e Extension + 0x1, 0, edx, 4, tsc , Time Sta= mp Counter + 0x1, 0, edx, 5, msr , Model-Sp= ecific Registers (RDMSR and WRMSR support) + 0x1, 0, edx, 6, pae , Physical= Address Extensions + 0x1, 0, edx, 7, mce , Machine = Check Exception + 0x1, 0, edx, 8, cx8 , CMPXCHG8= B instruction + 0x1, 0, edx, 9, apic , APIC on-= chip + 0x1, 0, edx, 11, sep , SYSENTER= , SYSEXIT, and associated MSRs + 0x1, 0, edx, 12, mtrr , Memory T= ype Range Registers + 0x1, 0, edx, 13, pge , Page Glo= bal Extensions + 0x1, 0, edx, 14, mca , Machine = Check Architecture + 0x1, 0, edx, 15, cmov , Conditio= nal Move Instruction + 0x1, 0, edx, 16, pat , Page Att= ribute Table + 0x1, 0, edx, 17, pse36 , Page Siz= e Extension (36-bit) + 0x1, 0, edx, 18, pn , Processo= r Serial Number + 0x1, 0, edx, 19, clflush , CLFLUSH = instruction + 0x1, 0, edx, 21, dts , Debug St= ore + 0x1, 0, edx, 22, acpi , Thermal = monitor and clock control + 0x1, 0, edx, 23, mmx , MMX inst= ructions + 0x1, 0, edx, 24, fxsr , FXSAVE a= nd FXRSTOR instructions + 0x1, 0, edx, 25, sse , SSE inst= ructions + 0x1, 0, edx, 26, sse2 , SSE2 ins= tructions + 0x1, 0, edx, 27, ss , Self Sno= op + 0x1, 0, edx, 28, ht , Hyper-th= reading + 0x1, 0, edx, 29, tm , Thermal = Monitor + 0x1, 0, edx, 30, ia64 , Legacy I= A-64 (Itanium) support bit, now resreved + 0x1, 0, edx, 31, pbe , Pending = Break Enable =20 # Leaf 2H # Intel cache and TLB information one-byte descriptors =20 - 2, 0, eax, 7:0, iteration_count , Number o= f times this CPUD leaf must be queried - 2, 0, eax, 15:8, desc1 , Descript= or #1 - 2, 0, eax, 23:16, desc2 , Descript= or #2 - 2, 0, eax, 30:24, desc3 , Descript= or #3 - 2, 0, eax, 31, eax_invalid , Descript= ors 1-3 are invalid if set - 2, 0, ebx, 7:0, desc4 , Descript= or #4 - 2, 0, ebx, 15:8, desc5 , Descript= or #5 - 2, 0, ebx, 23:16, desc6 , Descript= or #6 - 2, 0, ebx, 30:24, desc7 , Descript= or #7 - 2, 0, ebx, 31, ebx_invalid , Descript= ors 4-7 are invalid if set - 2, 0, ecx, 7:0, desc8 , Descript= or #8 - 2, 0, ecx, 15:8, desc9 , Descript= or #9 - 2, 0, ecx, 23:16, desc10 , Descript= or #10 - 2, 0, ecx, 30:24, desc11 , Descript= or #11 - 2, 0, ecx, 31, ecx_invalid , Descript= ors 8-11 are invalid if set - 2, 0, edx, 7:0, desc12 , Descript= or #12 - 2, 0, edx, 15:8, desc13 , Descript= or #13 - 2, 0, edx, 23:16, desc14 , Descript= or #14 - 2, 0, edx, 30:24, desc15 , Descript= or #15 - 2, 0, edx, 31, edx_invalid , Descript= ors 12-15 are invalid if set + 0x2, 0, eax, 7:0, iteration_count , Number o= f times this CPUD leaf must be queried + 0x2, 0, eax, 15:8, desc1 , Descript= or #1 + 0x2, 0, eax, 23:16, desc2 , Descript= or #2 + 0x2, 0, eax, 30:24, desc3 , Descript= or #3 + 0x2, 0, eax, 31, eax_invalid , Descript= ors 1-3 are invalid if set + 0x2, 0, ebx, 7:0, desc4 , Descript= or #4 + 0x2, 0, ebx, 15:8, desc5 , Descript= or #5 + 0x2, 0, ebx, 23:16, desc6 , Descript= or #6 + 0x2, 0, ebx, 30:24, desc7 , Descript= or #7 + 0x2, 0, ebx, 31, ebx_invalid , Descript= ors 4-7 are invalid if set + 0x2, 0, ecx, 7:0, desc8 , Descript= or #8 + 0x2, 0, ecx, 15:8, desc9 , Descript= or #9 + 0x2, 0, ecx, 23:16, desc10 , Descript= or #10 + 0x2, 0, ecx, 30:24, desc11 , Descript= or #11 + 0x2, 0, ecx, 31, ecx_invalid , Descript= ors 8-11 are invalid if set + 0x2, 0, edx, 7:0, desc12 , Descript= or #12 + 0x2, 0, edx, 15:8, desc13 , Descript= or #13 + 0x2, 0, edx, 23:16, desc14 , Descript= or #14 + 0x2, 0, edx, 30:24, desc15 , Descript= or #15 + 0x2, 0, edx, 31, edx_invalid , Descript= ors 12-15 are invalid if set + +# Leaf 3H +# Transmeta Processor Serial Number (PSN) + + 0x3, 0, eax, 31:0, cpu_psn_0 , Processo= r Serial Number bytes 0 - 3 + 0x3, 0, ebx, 31:0, cpu_psn_1 , Processo= r Serial Number bytes 4 - 7 + 0x3, 0, ecx, 31:0, cpu_psn_2 , Processo= r Serial Number bytes 8 - 11 + 0x3, 0, edx, 31:0, cpu_psn_3 , Processo= r Serial Number bytes 12 - 15 =20 # Leaf 4H # Intel deterministic cache parameters =20 - 4, 31:0, eax, 4:0, cache_type , Cache ty= pe field - 4, 31:0, eax, 7:5, cache_level , Cache le= vel (1-based) - 4, 31:0, eax, 8, cache_self_init , Self-ini= tialializing cache level - 4, 31:0, eax, 9, fully_associative , Fully-as= sociative cache - 4, 31:0, eax, 25:14, num_threads_sharing , Number l= ogical CPUs sharing this cache - 4, 31:0, eax, 31:26, num_cores_on_die , Number o= f cores in the physical package - 4, 31:0, ebx, 11:0, cache_linesize , System c= oherency line size (0-based) - 4, 31:0, ebx, 21:12, cache_npartitions , Physical= line partitions (0-based) - 4, 31:0, ebx, 31:22, cache_nways , Ways of = associativity (0-based) - 4, 31:0, ecx, 30:0, cache_nsets , Cache nu= mber of sets (0-based) - 4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/I= NVD not guaranteed for Remote Lower-Level caches - 4, 31:0, edx, 1, ll_inclusive , Cache is= inclusive of Lower-Level caches - 4, 31:0, edx, 2, complex_indexing , Not a di= rect-mapped cache (complex function) + 0x4, 31:0, eax, 4:0, cache_type , Cache ty= pe field + 0x4, 31:0, eax, 7:5, cache_level , Cache le= vel (1-based) + 0x4, 31:0, eax, 8, cache_self_init , Self-ini= tialializing cache level + 0x4, 31:0, eax, 9, fully_associative , Fully-as= sociative cache + 0x4, 31:0, eax, 25:14, num_threads_sharing , Number l= ogical CPUs sharing this cache + 0x4, 31:0, eax, 31:26, num_cores_on_die , Number o= f cores in the physical package + 0x4, 31:0, ebx, 11:0, cache_linesize , System c= oherency line size (0-based) + 0x4, 31:0, ebx, 21:12, cache_npartitions , Physical= line partitions (0-based) + 0x4, 31:0, ebx, 31:22, cache_nways , Ways of = associativity (0-based) + 0x4, 31:0, ecx, 30:0, cache_nsets , Cache nu= mber of sets (0-based) + 0x4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/I= NVD not guaranteed for Remote Lower-Level caches + 0x4, 31:0, edx, 1, ll_inclusive , Cache is= inclusive of Lower-Level caches + 0x4, 31:0, edx, 2, complex_indexing , Not a di= rect-mapped cache (complex function) =20 # Leaf 5H # MONITOR/MWAIT instructions enumeration =20 - 5, 0, eax, 15:0, min_mon_size , Smallest= monitor-line size, in bytes - 5, 0, ebx, 15:0, max_mon_size , Largest = monitor-line size, in bytes - 5, 0, ecx, 0, mwait_ext , Enumerat= ion of MONITOR/MWAIT extensions is supported - 5, 0, ecx, 1, mwait_irq_break , Interrup= ts as a break-event for MWAIT is supported - 5, 0, edx, 3:0, n_c0_substates , Number o= f C0 sub C-states supported using MWAIT - 5, 0, edx, 7:4, n_c1_substates , Number o= f C1 sub C-states supported using MWAIT - 5, 0, edx, 11:8, n_c2_substates , Number o= f C2 sub C-states supported using MWAIT - 5, 0, edx, 15:12, n_c3_substates , Number o= f C3 sub C-states supported using MWAIT - 5, 0, edx, 19:16, n_c4_substates , Number o= f C4 sub C-states supported using MWAIT - 5, 0, edx, 23:20, n_c5_substates , Number o= f C5 sub C-states supported using MWAIT - 5, 0, edx, 27:24, n_c6_substates , Number o= f C6 sub C-states supported using MWAIT - 5, 0, edx, 31:28, n_c7_substates , Number o= f C7 sub C-states supported using MWAIT + 0x5, 0, eax, 15:0, min_mon_size , Smallest= monitor-line size, in bytes + 0x5, 0, ebx, 15:0, max_mon_size , Largest = monitor-line size, in bytes + 0x5, 0, ecx, 0, mwait_ext , Enumerat= ion of MONITOR/MWAIT extensions is supported + 0x5, 0, ecx, 1, mwait_irq_break , Interrup= ts as a break-event for MWAIT is supported + 0x5, 0, edx, 3:0, n_c0_substates , Number o= f C0 sub C-states supported using MWAIT + 0x5, 0, edx, 7:4, n_c1_substates , Number o= f C1 sub C-states supported using MWAIT + 0x5, 0, edx, 11:8, n_c2_substates , Number o= f C2 sub C-states supported using MWAIT + 0x5, 0, edx, 15:12, n_c3_substates , Number o= f C3 sub C-states supported using MWAIT + 0x5, 0, edx, 19:16, n_c4_substates , Number o= f C4 sub C-states supported using MWAIT + 0x5, 0, edx, 23:20, n_c5_substates , Number o= f C5 sub C-states supported using MWAIT + 0x5, 0, edx, 27:24, n_c6_substates , Number o= f C6 sub C-states supported using MWAIT + 0x5, 0, edx, 31:28, n_c7_substates , Number o= f C7 sub C-states supported using MWAIT =20 # Leaf 6H # Thermal and Power Management enumeration =20 - 6, 0, eax, 0, dtherm , Digital = temprature sensor - 6, 0, eax, 1, turbo_boost , Intel Tu= rbo Boost - 6, 0, eax, 2, arat , Always-R= unning APIC Timer (not affected by p-state) - 6, 0, eax, 4, pln , Power Li= mit Notification (PLN) event - 6, 0, eax, 5, ecmd , Clock mo= dulation duty cycle extension - 6, 0, eax, 6, pts , Package = thermal management - 6, 0, eax, 7, hwp , HWP (Har= dware P-states) base registers are supported - 6, 0, eax, 8, hwp_notify , HWP noti= fication (IA32_HWP_INTERRUPT MSR) - 6, 0, eax, 9, hwp_act_window , HWP acti= vity window (IA32_HWP_REQUEST[bits 41:32]) supported - 6, 0, eax, 10, hwp_epp , HWP Ener= gy Performance Preference - 6, 0, eax, 11, hwp_pkg_req , HWP Pack= age Level Request - 6, 0, eax, 13, hdc_base_regs , HDC base= registers are supported - 6, 0, eax, 14, turbo_boost_3_0 , Intel Tu= rbo Boost Max 3.0 - 6, 0, eax, 15, hwp_capabilities , HWP High= est Performance change - 6, 0, eax, 16, hwp_peci_override , HWP PECI= override - 6, 0, eax, 17, hwp_flexible , Flexible= HWP - 6, 0, eax, 18, hwp_fast , IA32_HWP= _REQUEST MSR fast access mode - 6, 0, eax, 19, hfi , HW_FEEDB= ACK MSRs supported - 6, 0, eax, 20, hwp_ignore_idle , Ignoring= idle logical CPU HWP req is supported - 6, 0, eax, 23, thread_director , Intel th= read director support - 6, 0, eax, 24, therm_interrupt_bit25 , IA32_THE= RM_INTERRUPT MSR bit 25 is supported - 6, 0, ebx, 3:0, n_therm_thresholds , Digital = thermometer thresholds - 6, 0, ecx, 0, aperfmperf , MPERF/AP= ERF MSRs (effective frequency interface) - 6, 0, ecx, 3, epb , IA32_ENE= RGY_PERF_BIAS MSR support - 6, 0, ecx, 15:8, thrd_director_nclasses , Number o= f classes, Intel thread director - 6, 0, edx, 0, perfcap_reporting , Performa= nce capability reporting - 6, 0, edx, 1, encap_reporting , Energy e= fficiency capability reporting - 6, 0, edx, 11:8, feedback_sz , HW feedb= ack interface struct size, in 4K pages - 6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU index @ HW feedback struct, 0-based + 0x6, 0, eax, 0, dtherm , Digital = temprature sensor + 0x6, 0, eax, 1, turbo_boost , Intel Tu= rbo Boost + 0x6, 0, eax, 2, arat , Always-R= unning APIC Timer (not affected by p-state) + 0x6, 0, eax, 4, pln , Power Li= mit Notification (PLN) event + 0x6, 0, eax, 5, ecmd , Clock mo= dulation duty cycle extension + 0x6, 0, eax, 6, pts , Package = thermal management + 0x6, 0, eax, 7, hwp , HWP (Har= dware P-states) base registers are supported + 0x6, 0, eax, 8, hwp_notify , HWP noti= fication (IA32_HWP_INTERRUPT MSR) + 0x6, 0, eax, 9, hwp_act_window , HWP acti= vity window (IA32_HWP_REQUEST[bits 41:32]) supported + 0x6, 0, eax, 10, hwp_epp , HWP Ener= gy Performance Preference + 0x6, 0, eax, 11, hwp_pkg_req , HWP Pack= age Level Request + 0x6, 0, eax, 13, hdc_base_regs , HDC base= registers are supported + 0x6, 0, eax, 14, turbo_boost_3_0 , Intel Tu= rbo Boost Max 3.0 + 0x6, 0, eax, 15, hwp_capabilities , HWP High= est Performance change + 0x6, 0, eax, 16, hwp_peci_override , HWP PECI= override + 0x6, 0, eax, 17, hwp_flexible , Flexible= HWP + 0x6, 0, eax, 18, hwp_fast , IA32_HWP= _REQUEST MSR fast access mode + 0x6, 0, eax, 19, hfi , HW_FEEDB= ACK MSRs supported + 0x6, 0, eax, 20, hwp_ignore_idle , Ignoring= idle logical CPU HWP req is supported + 0x6, 0, eax, 23, thread_director , Intel th= read director support + 0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THE= RM_INTERRUPT MSR bit 25 is supported + 0x6, 0, ebx, 3:0, n_therm_thresholds , Digital = thermometer thresholds + 0x6, 0, ecx, 0, aperfmperf , MPERF/AP= ERF MSRs (effective frequency interface) + 0x6, 0, ecx, 3, epb , IA32_ENE= RGY_PERF_BIAS MSR support + 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number o= f classes, Intel thread director + 0x6, 0, edx, 0, perfcap_reporting , Performa= nce capability reporting + 0x6, 0, edx, 1, encap_reporting , Energy e= fficiency capability reporting + 0x6, 0, edx, 11:8, feedback_sz , HW feedb= ack interface struct size, in 4K pages + 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU index @ HW feedback struct, 0-based =20 # Leaf 7H # Extended CPU features enumeration =20 - 7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f cpuid 0x7 subleaves - 7, 0, ebx, 0, fsgsbase , FSBASE/G= SBASE read/write support - 7, 0, ebx, 1, tsc_adjust , IA32_TSC= _ADJUST MSR supported - 7, 0, ebx, 2, sgx , Intel SG= X (Software Guard Extensions) - 7, 0, ebx, 3, bmi1 , Bit mani= pulation extensions group 1 - 7, 0, ebx, 4, hle , Hardware= Lock Elision - 7, 0, ebx, 5, avx2 , AVX2 ins= truction set - 7, 0, ebx, 6, fdp_excptn_only , FPU Data= Pointer updated only on x87 exceptions - 7, 0, ebx, 7, smep , Supervis= or Mode Execution Protection - 7, 0, ebx, 8, bmi2 , Bit mani= pulation extensions group 2 - 7, 0, ebx, 9, erms , Enhanced= REP MOVSB/STOSB - 7, 0, ebx, 10, invpcid , INVPCID = instruction (Invalidate Processor Context ID) - 7, 0, ebx, 11, rtm , Intel re= stricted transactional memory - 7, 0, ebx, 12, cqm , Intel RD= T-CMT / AMD Platform-QoS cache monitoring - 7, 0, ebx, 13, zero_fcs_fds , Deprecat= ed FPU CS/DS (stored as zero) - 7, 0, ebx, 14, mpx , Intel me= mory protection extensions - 7, 0, ebx, 15, rdt_a , Intel RD= T / AMD Platform-QoS Enforcemeent - 7, 0, ebx, 16, avx512f , AVX-512 = foundation instructions - 7, 0, ebx, 17, avx512dq , AVX-512 = double/quadword instructions - 7, 0, ebx, 18, rdseed , RDSEED i= nstruction - 7, 0, ebx, 19, adx , ADCX/ADO= X instructions - 7, 0, ebx, 20, smap , Supervis= or mode access prevention - 7, 0, ebx, 21, avx512ifma , AVX-512 = integer fused multiply add - 7, 0, ebx, 23, clflushopt , CLFLUSHO= PT instruction - 7, 0, ebx, 24, clwb , CLWB ins= truction - 7, 0, ebx, 25, intel_pt , Intel pr= ocessor trace - 7, 0, ebx, 26, avx512pf , AVX-512 = prefetch instructions - 7, 0, ebx, 27, avx512er , AVX-512 = exponent/reciprocal instrs - 7, 0, ebx, 28, avx512cd , AVX-512 = conflict detection instrs - 7, 0, ebx, 29, sha_ni , SHA/SHA2= 56 instructions - 7, 0, ebx, 30, avx512bw , AVX-512 = BW (byte/word granular) instructions - 7, 0, ebx, 31, avx512vl , AVX-512 = VL (128/256 vector length) extensions - 7, 0, ecx, 0, prefetchwt1 , PREFETCH= WT1 (Intel Xeon Phi only) - 7, 0, ecx, 1, avx512vbmi , AVX-512 = Vector byte manipulation instrs - 7, 0, ecx, 2, umip , User mod= e instruction protection - 7, 0, ecx, 3, pku , Protecti= on keys for user-space - 7, 0, ecx, 4, ospke , OS prote= ction keys enable - 7, 0, ecx, 5, waitpkg , WAITPKG = instructions - 7, 0, ecx, 6, avx512_vbmi2 , AVX-512 = vector byte manipulation instrs group 2 - 7, 0, ecx, 7, cet_ss , CET shad= ow stack features - 7, 0, ecx, 8, gfni , Galois f= ield new instructions - 7, 0, ecx, 9, vaes , Vector A= ES instrs - 7, 0, ecx, 10, vpclmulqdq , VPCLMULQ= DQ 256-bit instruction support - 7, 0, ecx, 11, avx512_vnni , Vector n= eural network instructions - 7, 0, ecx, 12, avx512_bitalg , AVX-512 = bit count/shiffle - 7, 0, ecx, 13, tme , Intel to= tal memory encryption - 7, 0, ecx, 14, avx512_vpopcntdq , AVX-512:= POPCNT for vectors of DW/QW - 7, 0, ecx, 16, la57 , 57-bit l= inear addreses (five-level paging) - 7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/B= NDSTX MAWAU value in 64-bit mode - 7, 0, ecx, 22, rdpid , RDPID in= struction - 7, 0, ecx, 23, key_locker , Intel ke= y locker support - 7, 0, ecx, 24, bus_lock_detect , OS bus-l= ock detection - 7, 0, ecx, 25, cldemote , CLDEMOTE= instruction - 7, 0, ecx, 27, movdiri , MOVDIRI = instruction - 7, 0, ecx, 28, movdir64b , MOVDIR64= B instruction - 7, 0, ecx, 29, enqcmd , Enqueue = stores supported (ENQCMD{,S}) - 7, 0, ecx, 30, sgx_lc , Intel SG= X launch configuration - 7, 0, ecx, 31, pks , Protecti= on keys for supervisor-mode pages - 7, 0, edx, 1, sgx_keys , Intel SG= X attestation services - 7, 0, edx, 2, avx512_4vnniw , AVX-512 = neural network instructions - 7, 0, edx, 3, avx512_4fmaps , AVX-512 = multiply accumulation single precision - 7, 0, edx, 4, fsrm , Fast sho= rt REP MOV - 7, 0, edx, 5, uintr , CPU supp= orts user interrupts - 7, 0, edx, 8, avx512_vp2intersect , VP2INTER= SECT{D,Q} instructions - 7, 0, edx, 9, srdbs_ctrl , SRBDS mi= tigation MSR available - 7, 0, edx, 10, md_clear , VERW MD_= CLEAR microcode support - 7, 0, edx, 11, rtm_always_abort , XBEGIN (= RTM transaction) always aborts - 7, 0, edx, 13, tsx_force_abort , MSR TSX_= FORCE_ABORT, RTM_ABORT bit, supported - 7, 0, edx, 14, serialize , SERIALIZ= E instruction - 7, 0, edx, 15, hybrid_cpu , The CPU = is identified as a 'hybrid part' - 7, 0, edx, 16, tsxldtrk , TSX susp= end/resume load address tracking - 7, 0, edx, 18, pconfig , PCONFIG = instruction - 7, 0, edx, 19, arch_lbr , Intel ar= chitectural LBRs - 7, 0, edx, 20, ibt , CET indi= rect branch tracking - 7, 0, edx, 22, amx_bf16 , AMX-BF16= : tile bfloat16 support - 7, 0, edx, 23, avx512_fp16 , AVX-512 = FP16 instructions - 7, 0, edx, 24, amx_tile , AMX-TILE= : tile architecture support - 7, 0, edx, 25, amx_int8 , AMX-INT8= : tile 8-bit integer support - 7, 0, edx, 26, spec_ctrl , Speculat= ion Control (IBRS/IBPB: indirect branch restrictions) - 7, 0, edx, 27, intel_stibp , Single t= hread indirect branch predictors - 7, 0, edx, 28, flush_l1d , FLUSH L1= D cache: IA32_FLUSH_CMD MSR - 7, 0, edx, 29, arch_capabilities , Intel IA= 32_ARCH_CAPABILITIES MSR - 7, 0, edx, 30, core_capabilities , IA32_COR= E_CAPABILITIES MSR - 7, 0, edx, 31, spec_ctrl_ssbd , Speculat= ive store bypass disable - 7, 1, eax, 4, avx_vnni , AVX-VNNI= instructions - 7, 1, eax, 5, avx512_bf16 , AVX-512 = bFloat16 instructions - 7, 1, eax, 6, lass , Linear a= ddress space separation - 7, 1, eax, 7, cmpccxadd , CMPccXAD= D instructions - 7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: CPUID leaf 0x23 is supported - 7, 1, eax, 10, fzrm , Fast zer= o-length REP MOVSB - 7, 1, eax, 11, fsrs , Fast sho= rt REP STOSB - 7, 1, eax, 12, fsrc , Fast Sho= rt REP CMPSB/SCASB - 7, 1, eax, 17, fred , FRED: Fl= exible return and event delivery transitions - 7, 1, eax, 18, lkgs , LKGS: Lo= ad 'kernel' (userspace) GS - 7, 1, eax, 19, wrmsrns , WRMSRNS = instr (WRMSR-non-serializing) - 7, 1, eax, 21, amx_fp16 , AMX-FP16= : FP16 tile operations - 7, 1, eax, 22, hreset , History = reset support - 7, 1, eax, 23, avx_ifma , Integer = fused multiply add - 7, 1, eax, 26, lam , Linear a= ddress masking - 7, 1, eax, 27, rd_wr_msrlist , RDMSRLIS= T/WRMSRLIST instructions - 7, 1, ebx, 0, intel_ppin , Protecte= d processor inventory number (PPIN{,_CTL} MSRs) - 7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI= -INT8 instructions - 7, 1, edx, 5, avx_ne_convert , AVX-NE-C= ONVERT instructions - 7, 1, edx, 8, amx_complex , AMX-COMP= LEX instructions (starting from Granite Rapids) - 7, 1, edx, 14, prefetchit_0_1 , PREFETCH= IT0/1 instructions - 7, 1, edx, 18, cet_sss , CET supe= rvisor shadow stacks safe to use - 7, 2, edx, 0, intel_psfd , Intel pr= edictive store forward disable - 7, 2, edx, 1, ipred_ctrl , MSR bits= IA32_SPEC_CTRL.IPRED_DIS_{U,S} - 7, 2, edx, 2, rrsba_ctrl , MSR bits= IA32_SPEC_CTRL.RRSBA_DIS_{U,S} - 7, 2, edx, 3, ddp_ctrl , MSR bit = IA32_SPEC_CTRL.DDPD_U - 7, 2, edx, 4, bhi_ctrl , MSR bit = IA32_SPEC_CTRL.BHI_DIS_S - 7, 2, edx, 5, mcdt_no , MCDT mit= igation not needed - 7, 2, edx, 6, uclock_disable , UC-lock = disable is supported + 0x7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f cpuid 0x7 subleaves + 0x7, 0, ebx, 0, fsgsbase , FSBASE/G= SBASE read/write support + 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC= _ADJUST MSR supported + 0x7, 0, ebx, 2, sgx , Intel SG= X (Software Guard Extensions) + 0x7, 0, ebx, 3, bmi1 , Bit mani= pulation extensions group 1 + 0x7, 0, ebx, 4, hle , Hardware= Lock Elision + 0x7, 0, ebx, 5, avx2 , AVX2 ins= truction set + 0x7, 0, ebx, 6, fdp_excptn_only , FPU Data= Pointer updated only on x87 exceptions + 0x7, 0, ebx, 7, smep , Supervis= or Mode Execution Protection + 0x7, 0, ebx, 8, bmi2 , Bit mani= pulation extensions group 2 + 0x7, 0, ebx, 9, erms , Enhanced= REP MOVSB/STOSB + 0x7, 0, ebx, 10, invpcid , INVPCID = instruction (Invalidate Processor Context ID) + 0x7, 0, ebx, 11, rtm , Intel re= stricted transactional memory + 0x7, 0, ebx, 12, cqm , Intel RD= T-CMT / AMD Platform-QoS cache monitoring + 0x7, 0, ebx, 13, zero_fcs_fds , Deprecat= ed FPU CS/DS (stored as zero) + 0x7, 0, ebx, 14, mpx , Intel me= mory protection extensions + 0x7, 0, ebx, 15, rdt_a , Intel RD= T / AMD Platform-QoS Enforcemeent + 0x7, 0, ebx, 16, avx512f , AVX-512 = foundation instructions + 0x7, 0, ebx, 17, avx512dq , AVX-512 = double/quadword instructions + 0x7, 0, ebx, 18, rdseed , RDSEED i= nstruction + 0x7, 0, ebx, 19, adx , ADCX/ADO= X instructions + 0x7, 0, ebx, 20, smap , Supervis= or mode access prevention + 0x7, 0, ebx, 21, avx512ifma , AVX-512 = integer fused multiply add + 0x7, 0, ebx, 23, clflushopt , CLFLUSHO= PT instruction + 0x7, 0, ebx, 24, clwb , CLWB ins= truction + 0x7, 0, ebx, 25, intel_pt , Intel pr= ocessor trace + 0x7, 0, ebx, 26, avx512pf , AVX-512 = prefetch instructions + 0x7, 0, ebx, 27, avx512er , AVX-512 = exponent/reciprocal instrs + 0x7, 0, ebx, 28, avx512cd , AVX-512 = conflict detection instrs + 0x7, 0, ebx, 29, sha_ni , SHA/SHA2= 56 instructions + 0x7, 0, ebx, 30, avx512bw , AVX-512 = BW (byte/word granular) instructions + 0x7, 0, ebx, 31, avx512vl , AVX-512 = VL (128/256 vector length) extensions + 0x7, 0, ecx, 0, prefetchwt1 , PREFETCH= WT1 (Intel Xeon Phi only) + 0x7, 0, ecx, 1, avx512vbmi , AVX-512 = Vector byte manipulation instrs + 0x7, 0, ecx, 2, umip , User mod= e instruction protection + 0x7, 0, ecx, 3, pku , Protecti= on keys for user-space + 0x7, 0, ecx, 4, ospke , OS prote= ction keys enable + 0x7, 0, ecx, 5, waitpkg , WAITPKG = instructions + 0x7, 0, ecx, 6, avx512_vbmi2 , AVX-512 = vector byte manipulation instrs group 2 + 0x7, 0, ecx, 7, cet_ss , CET shad= ow stack features + 0x7, 0, ecx, 8, gfni , Galois f= ield new instructions + 0x7, 0, ecx, 9, vaes , Vector A= ES instrs + 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQ= DQ 256-bit instruction support + 0x7, 0, ecx, 11, avx512_vnni , Vector n= eural network instructions + 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 = bit count/shiffle + 0x7, 0, ecx, 13, tme , Intel to= tal memory encryption + 0x7, 0, ecx, 14, avx512_vpopcntdq , AVX-512:= POPCNT for vectors of DW/QW + 0x7, 0, ecx, 16, la57 , 57-bit l= inear addreses (five-level paging) + 0x7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/B= NDSTX MAWAU value in 64-bit mode + 0x7, 0, ecx, 22, rdpid , RDPID in= struction + 0x7, 0, ecx, 23, key_locker , Intel ke= y locker support + 0x7, 0, ecx, 24, bus_lock_detect , OS bus-l= ock detection + 0x7, 0, ecx, 25, cldemote , CLDEMOTE= instruction + 0x7, 0, ecx, 27, movdiri , MOVDIRI = instruction + 0x7, 0, ecx, 28, movdir64b , MOVDIR64= B instruction + 0x7, 0, ecx, 29, enqcmd , Enqueue = stores supported (ENQCMD{,S}) + 0x7, 0, ecx, 30, sgx_lc , Intel SG= X launch configuration + 0x7, 0, ecx, 31, pks , Protecti= on keys for supervisor-mode pages + 0x7, 0, edx, 1, sgx_keys , Intel SG= X attestation services + 0x7, 0, edx, 2, avx512_4vnniw , AVX-512 = neural network instructions + 0x7, 0, edx, 3, avx512_4fmaps , AVX-512 = multiply accumulation single precision + 0x7, 0, edx, 4, fsrm , Fast sho= rt REP MOV + 0x7, 0, edx, 5, uintr , CPU supp= orts user interrupts + 0x7, 0, edx, 8, avx512_vp2intersect , VP2INTER= SECT{D,Q} instructions + 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mi= tigation MSR available + 0x7, 0, edx, 10, md_clear , VERW MD_= CLEAR microcode support + 0x7, 0, edx, 11, rtm_always_abort , XBEGIN (= RTM transaction) always aborts + 0x7, 0, edx, 13, tsx_force_abort , MSR TSX_= FORCE_ABORT, RTM_ABORT bit, supported + 0x7, 0, edx, 14, serialize , SERIALIZ= E instruction + 0x7, 0, edx, 15, hybrid_cpu , The CPU = is identified as a 'hybrid part' + 0x7, 0, edx, 16, tsxldtrk , TSX susp= end/resume load address tracking + 0x7, 0, edx, 18, pconfig , PCONFIG = instruction + 0x7, 0, edx, 19, arch_lbr , Intel ar= chitectural LBRs + 0x7, 0, edx, 20, ibt , CET indi= rect branch tracking + 0x7, 0, edx, 22, amx_bf16 , AMX-BF16= : tile bfloat16 support + 0x7, 0, edx, 23, avx512_fp16 , AVX-512 = FP16 instructions + 0x7, 0, edx, 24, amx_tile , AMX-TILE= : tile architecture support + 0x7, 0, edx, 25, amx_int8 , AMX-INT8= : tile 8-bit integer support + 0x7, 0, edx, 26, spec_ctrl , Speculat= ion Control (IBRS/IBPB: indirect branch restrictions) + 0x7, 0, edx, 27, intel_stibp , Single t= hread indirect branch predictors + 0x7, 0, edx, 28, flush_l1d , FLUSH L1= D cache: IA32_FLUSH_CMD MSR + 0x7, 0, edx, 29, arch_capabilities , Intel IA= 32_ARCH_CAPABILITIES MSR + 0x7, 0, edx, 30, core_capabilities , IA32_COR= E_CAPABILITIES MSR + 0x7, 0, edx, 31, spec_ctrl_ssbd , Speculat= ive store bypass disable + 0x7, 1, eax, 4, avx_vnni , AVX-VNNI= instructions + 0x7, 1, eax, 5, avx512_bf16 , AVX-512 = bFloat16 instructions + 0x7, 1, eax, 6, lass , Linear a= ddress space separation + 0x7, 1, eax, 7, cmpccxadd , CMPccXAD= D instructions + 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: CPUID leaf 0x23 is supported + 0x7, 1, eax, 10, fzrm , Fast zer= o-length REP MOVSB + 0x7, 1, eax, 11, fsrs , Fast sho= rt REP STOSB + 0x7, 1, eax, 12, fsrc , Fast Sho= rt REP CMPSB/SCASB + 0x7, 1, eax, 17, fred , FRED: Fl= exible return and event delivery transitions + 0x7, 1, eax, 18, lkgs , LKGS: Lo= ad 'kernel' (userspace) GS + 0x7, 1, eax, 19, wrmsrns , WRMSRNS = instr (WRMSR-non-serializing) + 0x7, 1, eax, 20, nmi_src , NMI-sour= ce reporting with FRED event data + 0x7, 1, eax, 21, amx_fp16 , AMX-FP16= : FP16 tile operations + 0x7, 1, eax, 22, hreset , History = reset support + 0x7, 1, eax, 23, avx_ifma , Integer = fused multiply add + 0x7, 1, eax, 26, lam , Linear a= ddress masking + 0x7, 1, eax, 27, rd_wr_msrlist , RDMSRLIS= T/WRMSRLIST instructions + 0x7, 1, ebx, 0, intel_ppin , Protecte= d processor inventory number (PPIN{,_CTL} MSRs) + 0x7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI= -INT8 instructions + 0x7, 1, edx, 5, avx_ne_convert , AVX-NE-C= ONVERT instructions + 0x7, 1, edx, 8, amx_complex , AMX-COMP= LEX instructions (starting from Granite Rapids) + 0x7, 1, edx, 14, prefetchit_0_1 , PREFETCH= IT0/1 instructions + 0x7, 1, edx, 18, cet_sss , CET supe= rvisor shadow stacks safe to use + 0x7, 2, edx, 0, intel_psfd , Intel pr= edictive store forward disable + 0x7, 2, edx, 1, ipred_ctrl , MSR bits= IA32_SPEC_CTRL.IPRED_DIS_{U,S} + 0x7, 2, edx, 2, rrsba_ctrl , MSR bits= IA32_SPEC_CTRL.RRSBA_DIS_{U,S} + 0x7, 2, edx, 3, ddp_ctrl , MSR bit = IA32_SPEC_CTRL.DDPD_U + 0x7, 2, edx, 4, bhi_ctrl , MSR bit = IA32_SPEC_CTRL.BHI_DIS_S + 0x7, 2, edx, 5, mcdt_no , MCDT mit= igation not needed + 0x7, 2, edx, 6, uclock_disable , UC-lock = disable is supported =20 # Leaf 9H # Intel DCA (Direct Cache Access) enumeration =20 - 9, 0, eax, 0, dca_enabled_in_bios , DCA is e= nabled in BIOS + 0x9, 0, eax, 0, dca_enabled_in_bios , DCA is e= nabled in BIOS =20 # Leaf AH # Intel PMU (Performance Monitoring Unit) enumeration @@ -623,7 +632,7 @@ 0x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervis= or ID string bytes 8 - 11 =20 # Leaf 80000000H -# Maximum extended leaf number + CPU vendor string (AMD) +# Maximum extended leaf number + AMD/Transmeta CPU vendor string =20 0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum = extended cpuid leaf supported 0x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor I= D string bytes 0 - 3 @@ -636,6 +645,7 @@ 0x80000001, 0, eax, 3:0, e_stepping_id , Stepping= ID 0x80000001, 0, eax, 7:4, e_base_model , Base pro= cessor model 0x80000001, 0, eax, 11:8, e_base_family , Base pro= cessor family +0x80000001, 0, eax, 13:12, e_base_type , Base pro= cessor type (Transmeta) 0x80000001, 0, eax, 19:16, e_ext_model , Extended= processor model 0x80000001, 0, eax, 27:20, e_ext_family , Extended= processor family 0x80000001, 0, ebx, 15:0, brand_id , Brand ID @@ -687,6 +697,7 @@ 0x80000001, 0, edx, 19, mp , Out-of-s= pec AMD Multiprocessing bit 0x80000001, 0, edx, 20, nx , No-execu= te page protection 0x80000001, 0, edx, 22, mmxext , AMD MMX = extensions +0x80000001, 0, edx, 23, e_mmx , MMX inst= ructions (Transmeta) 0x80000001, 0, edx, 24, e_fxsr , FXSAVE a= nd FXRSTOR instructions 0x80000001, 0, edx, 25, fxsr_opt , FXSAVE a= nd FXRSTOR optimizations 0x80000001, 0, edx, 26, pdpe1gb , 1-GB lar= ge page support @@ -720,7 +731,7 @@ 0x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU bran= d ID string, bytes 44 - 47 =20 # Leaf 80000005H -# AMD L1 cache and L1 TLB enumeration +# AMD/Transmeta L1 cache and L1 TLB enumeration =20 0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB = #entires, 2M and 4M pages 0x80000005, 0, eax, 15:8, l1_itlb_2m_4m_assoc , L1 ITLB = associativity, 2M and 4M pages @@ -1051,3 +1062,108 @@ 0x80000026, 3:0, ecx, 7:0, domain_level , This dom= ain level (subleaf ID) 0x80000026, 3:0, ecx, 15:8, domain_type , This dom= ain type 0x80000026, 3:0, edx, 31:0, x2apic_id , x2APIC I= D of current logical CPU + +# Leaf 80860000H +# Maximum Transmeta leaf number + CPU vendor ID string + +0x80860000, 0, eax, 31:0, max_tra_leaf , Maximum = supported Transmeta leaf number +0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmet= a Vendor ID string bytes 0 - 3 +0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmet= a Vendor ID string bytes 8 - 11 +0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmet= a Vendor ID string bytes 4 - 7 + +# Leaf 80860001H +# Transmeta extended CPU information + +0x80860001, 0, eax, 3:0, stepping , Stepping= ID +0x80860001, 0, eax, 7:4, base_model , Base CPU= model ID +0x80860001, 0, eax, 11:8, base_family_id , Base CPU= family ID +0x80860001, 0, eax, 13:12, cpu_type , CPU type +0x80860001, 0, ebx, 7:0, cpu_rev_mask_minor , CPU revi= sion ID, mask minor +0x80860001, 0, ebx, 15:8, cpu_rev_mask_major , CPU revi= sion ID, mask major +0x80860001, 0, ebx, 23:16, cpu_rev_minor , CPU revi= sion ID, minor +0x80860001, 0, ebx, 31:24, cpu_rev_major , CPU revi= sion ID, major +0x80860001, 0, ecx, 31:0, cpu_base_mhz , CPU nomi= nal frequency, in MHz +0x80860001, 0, edx, 0, recovery , Recovery= CMS is active (after bad flush) +0x80860001, 0, edx, 1, longrun , LongRun = power management capabilities +0x80860001, 0, edx, 3, lrti , LongRun = Table Interface + +# Leaf 80860002H +# Transmeta Code Morphing Software (CMS) enumeration + +0x80860002, 0, eax, 31:0, cpu_rev_id , CPU revi= sion ID +0x80860002, 0, ebx, 7:0, cms_rev_mask_2 , CMS revi= sion ID, mask component 2 +0x80860002, 0, ebx, 15:8, cms_rev_mask_1 , CMS revi= sion ID, mask component 1 +0x80860002, 0, ebx, 23:16, cms_rev_minor , CMS revi= sion ID, minor +0x80860002, 0, ebx, 31:24, cms_rev_major , CMS revi= sion ID, major +0x80860002, 0, ecx, 31:0, cms_rev_mask_3 , CMS revi= sion ID, mask component 3 + +# Leaf 80860003H +# Transmeta CPU information string, bytes 0 - 15 + +0x80860003, 0, eax, 31:0, cpu_info_0 , CPU info= string bytes 0 - 3 +0x80860003, 0, ebx, 31:0, cpu_info_1 , CPU info= string bytes 4 - 7 +0x80860003, 0, ecx, 31:0, cpu_info_2 , CPU info= string bytes 8 - 11 +0x80860003, 0, edx, 31:0, cpu_info_3 , CPU info= string bytes 12 - 15 + +# Leaf 80860004H +# Transmeta CPU information string, bytes 16 - 31 + +0x80860004, 0, eax, 31:0, cpu_info_4 , CPU info= string bytes 16 - 19 +0x80860004, 0, ebx, 31:0, cpu_info_5 , CPU info= string bytes 20 - 23 +0x80860004, 0, ecx, 31:0, cpu_info_6 , CPU info= string bytes 24 - 27 +0x80860004, 0, edx, 31:0, cpu_info_7 , CPU info= string bytes 28 - 31 + +# Leaf 80860005H +# Transmeta CPU information string, bytes 32 - 47 + +0x80860005, 0, eax, 31:0, cpu_info_8 , CPU info= string bytes 32 - 35 +0x80860005, 0, ebx, 31:0, cpu_info_9 , CPU info= string bytes 36 - 39 +0x80860005, 0, ecx, 31:0, cpu_info_10 , CPU info= string bytes 40 - 43 +0x80860005, 0, edx, 31:0, cpu_info_11 , CPU info= string bytes 44 - 47 + +# Leaf 80860006H +# Transmeta CPU information string, bytes 48 - 63 + +0x80860006, 0, eax, 31:0, cpu_info_12 , CPU info= string bytes 48 - 51 +0x80860006, 0, ebx, 31:0, cpu_info_13 , CPU info= string bytes 52 - 55 +0x80860006, 0, ecx, 31:0, cpu_info_14 , CPU info= string bytes 56 - 59 +0x80860006, 0, edx, 31:0, cpu_info_15 , CPU info= string bytes 60 - 63 + +# Leaf 80860007H +# Transmeta live CPU information + +0x80860007, 0, eax, 31:0, cpu_cur_mhz , Current = CPU frequency, in MHz +0x80860007, 0, ebx, 31:0, cpu_cur_voltage , Current = CPU voltage, in millivolts +0x80860007, 0, ecx, 31:0, cpu_cur_perf_pctg , Current = CPU performance percentage, 0 - 100d +0x80860007, 0, edx, 31:0, cpu_cur_gate_delay , Current = CPU gate delay, in femtoseconds + +# Leaf C0000000H +# Maximum Centaur/Zhaoxin leaf number + +0xc0000000, 0, eax, 31:0, max_cntr_leaf , Maximum = Centaur/Zhaoxin leaf number + +# Leaf C0000001H +# Centaur/Zhaoxin extended CPU features + +0xc0000001, 0, edx, 0, ccs_sm2 , CCS SM2 = instructions +0xc0000001, 0, edx, 1, ccs_sm2_en , CCS SM2 = enabled +0xc0000001, 0, edx, 2, xstore , Random N= umber Generator +0xc0000001, 0, edx, 3, xstore_en , RNG enab= led +0xc0000001, 0, edx, 4, ccs_sm3_sm4 , CCS SM3 = and SM4 instructions +0xc0000001, 0, edx, 5, ccs_sm3_sm4_en , CCS SM3/= SM4 enabled +0xc0000001, 0, edx, 6, ace , Advanced= Cryptography Engine +0xc0000001, 0, edx, 7, ace_en , ACE enab= led +0xc0000001, 0, edx, 8, ace2 , Advanced= Cryptography Engine v2 +0xc0000001, 0, edx, 9, ace2_en , ACE v2 e= nabled +0xc0000001, 0, edx, 10, phe , PadLock = Hash Engine +0xc0000001, 0, edx, 11, phe_en , PHE enab= led +0xc0000001, 0, edx, 12, pmm , PadLock = Montgomery Multiplier +0xc0000001, 0, edx, 13, pmm_en , PMM enab= led +0xc0000001, 0, edx, 16, parallax , Parallax= auto adjust processor voltage +0xc0000001, 0, edx, 17, parallax_en , Parallax= enabled +0xc0000001, 0, edx, 20, tm3 , Thermal = Monitor v3 +0xc0000001, 0, edx, 21, tm3_en , TM v3 en= abled +0xc0000001, 0, edx, 25, phe2 , PadLock = Hash Engine v2 (SHA384/SHA512) +0xc0000001, 0, edx, 26, phe2_en , PHE v2 e= nabled +0xc0000001, 0, edx, 27, rsa , RSA inst= ructions (XMODEXP/MONTMUL2) +0xc0000001, 0, edx, 28, rsa_en , RSA inst= ructions enabled --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A487250BFC for ; Wed, 12 Mar 2025 14:38:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 17/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.1 Date: Wed, 12 Mar 2025 15:37:34 +0100 Message-ID: <20250312143738.458507-18-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update kcpuid's CSV file to version 2.1, as generated by x86-cpuid-db. Summary of the v2.1 changes: * Use a standardized style for all x86 trademarks, registers, opcodes, byte units, hexadecimal digits, and x86 technical terms. This was enforced by a number of x86-specific hunspell(5) dictionary and affix files at the x86-cpuid-db project's CI pipeline. * Expand abbreviated terms that might be OK in code but not in official listings (e.g., "addr", "instr", "reg", "virt", etc.) * Add new Zen5 SoC bits to leaf 0x80000020 and leaf 0x80000021. Signed-off-by: Ahmed S. Darwish Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.1/CHANGELOG.r= st --- tools/arch/x86/kcpuid/cpuid.csv | 171 +++++++++++++++++--------------- 1 file changed, 91 insertions(+), 80 deletions(-) diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.= csv index d0f7159f99ba..0f9c11208674 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,5 +1,5 @@ # SPDX-License-Identifier: CC0-1.0 -# Generator: x86-cpuid-db v2.0 +# Generator: x86-cpuid-db v2.1 =20 # # Auto-generated file. @@ -28,7 +28,7 @@ 0x1, 0, eax, 27:20, ext_family , Extended= CPU family ID 0x1, 0, ebx, 7:0, brand_id , Brand in= dex 0x1, 0, ebx, 15:8, clflush_size , CLFLUSH = instruction cache line size - 0x1, 0, ebx, 23:16, n_logical_cpu , Logical = CPU (HW threads) count + 0x1, 0, ebx, 23:16, n_logical_cpu , Logical = CPU count 0x1, 0, ebx, 31:24, local_apic_id , Initial = local APIC physical ID 0x1, 0, ecx, 0, pni , Streamin= g SIMD Extensions 3 (SSE3) 0x1, 0, ecx, 1, pclmulqdq , PCLMULQD= Q instruction support @@ -41,7 +41,7 @@ 0x1, 0, ecx, 8, tm2 , Thermal = Monitor 2 0x1, 0, ecx, 9, ssse3 , Suppleme= ntal SSE3 0x1, 0, ecx, 10, cid , L1 Conte= xt ID - 0x1, 0, ecx, 11, sdbg , Sillicon= Debug + 0x1, 0, ecx, 11, sdbg , Silicon = Debug 0x1, 0, ecx, 12, fma , FMA exte= nsions using YMM state 0x1, 0, ecx, 13, cx16 , CMPXCHG1= 6B instruction support 0x1, 0, ecx, 14, xtpr , xTPR Upd= ate Control @@ -89,13 +89,13 @@ 0x1, 0, edx, 27, ss , Self Sno= op 0x1, 0, edx, 28, ht , Hyper-th= reading 0x1, 0, edx, 29, tm , Thermal = Monitor - 0x1, 0, edx, 30, ia64 , Legacy I= A-64 (Itanium) support bit, now resreved + 0x1, 0, edx, 30, ia64 , Legacy I= A-64 (Itanium) support bit, now reserved 0x1, 0, edx, 31, pbe , Pending = Break Enable =20 # Leaf 2H # Intel cache and TLB information one-byte descriptors =20 - 0x2, 0, eax, 7:0, iteration_count , Number o= f times this CPUD leaf must be queried + 0x2, 0, eax, 7:0, iteration_count , Number o= f times this leaf must be queried 0x2, 0, eax, 15:8, desc1 , Descript= or #1 0x2, 0, eax, 23:16, desc2 , Descript= or #2 0x2, 0, eax, 30:24, desc3 , Descript= or #3 @@ -129,7 +129,7 @@ =20 0x4, 31:0, eax, 4:0, cache_type , Cache ty= pe field 0x4, 31:0, eax, 7:5, cache_level , Cache le= vel (1-based) - 0x4, 31:0, eax, 8, cache_self_init , Self-ini= tialializing cache level + 0x4, 31:0, eax, 8, cache_self_init , Self-ini= tializing cache level 0x4, 31:0, eax, 9, fully_associative , Fully-as= sociative cache 0x4, 31:0, eax, 25:14, num_threads_sharing , Number l= ogical CPUs sharing this cache 0x4, 31:0, eax, 31:26, num_cores_on_die , Number o= f cores in the physical package @@ -160,7 +160,7 @@ # Leaf 6H # Thermal and Power Management enumeration =20 - 0x6, 0, eax, 0, dtherm , Digital = temprature sensor + 0x6, 0, eax, 0, dtherm , Digital = temperature sensor 0x6, 0, eax, 1, turbo_boost , Intel Tu= rbo Boost 0x6, 0, eax, 2, arat , Always-R= unning APIC Timer (not affected by p-state) 0x6, 0, eax, 4, pln , Power Li= mit Notification (PLN) event @@ -187,8 +187,8 @@ 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number o= f classes, Intel thread director 0x6, 0, edx, 0, perfcap_reporting , Performa= nce capability reporting 0x6, 0, edx, 1, encap_reporting , Energy e= fficiency capability reporting - 0x6, 0, edx, 11:8, feedback_sz , HW feedb= ack interface struct size, in 4K pages - 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU index @ HW feedback struct, 0-based + 0x6, 0, edx, 11:8, feedback_sz , Feedback= interface structure size, in 4K pages + 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU hardware feedback interface index =20 # Leaf 7H # Extended CPU features enumeration @@ -209,7 +209,7 @@ 0x7, 0, ebx, 12, cqm , Intel RD= T-CMT / AMD Platform-QoS cache monitoring 0x7, 0, ebx, 13, zero_fcs_fds , Deprecat= ed FPU CS/DS (stored as zero) 0x7, 0, ebx, 14, mpx , Intel me= mory protection extensions - 0x7, 0, ebx, 15, rdt_a , Intel RD= T / AMD Platform-QoS Enforcemeent + 0x7, 0, ebx, 15, rdt_a , Intel RD= T / AMD Platform-QoS Enforcement 0x7, 0, ebx, 16, avx512f , AVX-512 = foundation instructions 0x7, 0, ebx, 17, avx512dq , AVX-512 = double/quadword instructions 0x7, 0, ebx, 18, rdseed , RDSEED i= nstruction @@ -220,27 +220,27 @@ 0x7, 0, ebx, 24, clwb , CLWB ins= truction 0x7, 0, ebx, 25, intel_pt , Intel pr= ocessor trace 0x7, 0, ebx, 26, avx512pf , AVX-512 = prefetch instructions - 0x7, 0, ebx, 27, avx512er , AVX-512 = exponent/reciprocal instrs - 0x7, 0, ebx, 28, avx512cd , AVX-512 = conflict detection instrs + 0x7, 0, ebx, 27, avx512er , AVX-512 = exponent/reciprocal instructions + 0x7, 0, ebx, 28, avx512cd , AVX-512 = conflict detection instructions 0x7, 0, ebx, 29, sha_ni , SHA/SHA2= 56 instructions - 0x7, 0, ebx, 30, avx512bw , AVX-512 = BW (byte/word granular) instructions + 0x7, 0, ebx, 30, avx512bw , AVX-512 = byte/word instructions 0x7, 0, ebx, 31, avx512vl , AVX-512 = VL (128/256 vector length) extensions 0x7, 0, ecx, 0, prefetchwt1 , PREFETCH= WT1 (Intel Xeon Phi only) - 0x7, 0, ecx, 1, avx512vbmi , AVX-512 = Vector byte manipulation instrs + 0x7, 0, ecx, 1, avx512vbmi , AVX-512 = Vector byte manipulation instructions 0x7, 0, ecx, 2, umip , User mod= e instruction protection 0x7, 0, ecx, 3, pku , Protecti= on keys for user-space 0x7, 0, ecx, 4, ospke , OS prote= ction keys enable 0x7, 0, ecx, 5, waitpkg , WAITPKG = instructions - 0x7, 0, ecx, 6, avx512_vbmi2 , AVX-512 = vector byte manipulation instrs group 2 + 0x7, 0, ecx, 6, avx512_vbmi2 , AVX-512 = vector byte manipulation instructions group 2 0x7, 0, ecx, 7, cet_ss , CET shad= ow stack features 0x7, 0, ecx, 8, gfni , Galois f= ield new instructions - 0x7, 0, ecx, 9, vaes , Vector A= ES instrs + 0x7, 0, ecx, 9, vaes , Vector A= ES instructions 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQ= DQ 256-bit instruction support 0x7, 0, ecx, 11, avx512_vnni , Vector n= eural network instructions - 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 = bit count/shiffle + 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 = bitwise algorithms 0x7, 0, ecx, 13, tme , Intel to= tal memory encryption - 0x7, 0, ecx, 14, avx512_vpopcntdq , AVX-512:= POPCNT for vectors of DW/QW - 0x7, 0, ecx, 16, la57 , 57-bit l= inear addreses (five-level paging) + 0x7, 0, ecx, 14, avx512_vpopcntdq , AVX-512:= POPCNT for vectors of DWORD/QWORD + 0x7, 0, ecx, 16, la57 , 57-bit l= inear addresses (five-level paging) 0x7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/B= NDSTX MAWAU value in 64-bit mode 0x7, 0, ecx, 22, rdpid , RDPID in= struction 0x7, 0, ecx, 23, key_locker , Intel ke= y locker support @@ -278,7 +278,7 @@ 0x7, 0, edx, 30, core_capabilities , IA32_COR= E_CAPABILITIES MSR 0x7, 0, edx, 31, spec_ctrl_ssbd , Speculat= ive store bypass disable 0x7, 1, eax, 4, avx_vnni , AVX-VNNI= instructions - 0x7, 1, eax, 5, avx512_bf16 , AVX-512 = bFloat16 instructions + 0x7, 1, eax, 5, avx512_bf16 , AVX-512 = bfloat16 instructions 0x7, 1, eax, 6, lass , Linear a= ddress space separation 0x7, 1, eax, 7, cmpccxadd , CMPccXAD= D instructions 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: CPUID leaf 0x23 is supported @@ -287,7 +287,7 @@ 0x7, 1, eax, 12, fsrc , Fast Sho= rt REP CMPSB/SCASB 0x7, 1, eax, 17, fred , FRED: Fl= exible return and event delivery transitions 0x7, 1, eax, 18, lkgs , LKGS: Lo= ad 'kernel' (userspace) GS - 0x7, 1, eax, 19, wrmsrns , WRMSRNS = instr (WRMSR-non-serializing) + 0x7, 1, eax, 19, wrmsrns , WRMSRNS = instruction (WRMSR-non-serializing) 0x7, 1, eax, 20, nmi_src , NMI-sour= ce reporting with FRED event data 0x7, 1, eax, 21, amx_fp16 , AMX-FP16= : FP16 tile operations 0x7, 1, eax, 22, hreset , History = reset support @@ -348,18 +348,18 @@ 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87= (bit 0) supported 0xd, 0, eax, 1, xcr0_sse , XCR0.SEE= (bit 1) supported 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX= (bit 2) supported - 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BND= REGS (bit 3) supported (MPX BND0-BND3 regs) - 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BND= CSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs) - 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPM= ASK (bit 5) supported (AVX-512 k0-k7 regs) - 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM= _Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs) - 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI1= 6_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs) - 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKR= U (bit 9) supported (XSAVE PKRU reg) - 0xd, 0, eax, 11, xcr0_cet_u , AMD XCR0= .CET_U (bit 11) supported (CET supervisor state) - 0xd, 0, eax, 12, xcr0_cet_s , AMD XCR0= .CET_S (bit 12) support (CET user state) + 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BND= REGS (bit 3) supported (MPX BND0-BND3 registers) + 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BND= CSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers) + 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPM= ASK (bit 5) supported (AVX-512 k0-k7 registers) + 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM= _Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers) + 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI1= 6_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers) + 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKR= U (bit 9) supported (XSAVE PKRU registers) + 0xd, 0, eax, 11, xcr0_cet_u , XCR0.CET= _U (bit 11) supported (CET user state) + 0xd, 0, eax, 12, xcr0_cet_s , XCR0.CET= _S (bit 12) supported (CET supervisor state) 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TIL= ECONFIG (bit 17) supported (AMX can manage TILECONFIG) 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TIL= EDATA (bit 18) supported (AMX can manage TILEDATA) - 0xd, 0, ebx, 31:0, xsave_sz_xcr0_enabled , XSAVE/XR= STR area byte size, for XCR0 enabled features - 0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XR= STR area max byte size, all CPU features + 0xd, 0, ebx, 31:0, xsave_sz_xcr0_enabled , XSAVE/XR= STOR area byte size, for XCR0 enabled features + 0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XR= STOR area max byte size, all CPU features 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0= .LWP (bit 62) supported (Light-weight Profiling) 0xd, 1, eax, 0, xsaveopt , XSAVEOPT= instruction 0xd, 1, eax, 1, xsavec , XSAVEC i= nstruction @@ -378,7 +378,7 @@ 0xd, 63:2, eax, 31:0, xsave_sz , Size of = save area for subleaf-N feature, in bytes 0xd, 63:2, ebx, 31:0, xsave_offset , Offset o= f save area for subleaf-N feature, in bytes 0xd, 63:2, ecx, 0, is_xss_bit , Subleaf = N describes an XSS bit, otherwise XCR0 bit - 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, W= hen compacted, subleaf-N feature xsave area is 64-byte aligned + 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, W= hen compacted, subleaf-N feature XSAVE area is 64-byte aligned =20 # Leaf FH # Intel RDT / AMD PQoS resource monitoring @@ -435,17 +435,17 @@ 0x12, 1, ecx, 0, xfrm_x87 , Enclave = XFRM.X87 (bit 0) supported 0x12, 1, ecx, 1, xfrm_sse , Enclave = XFRM.SEE (bit 1) supported 0x12, 1, ecx, 2, xfrm_avx , Enclave = XFRM.AVX (bit 2) supported - 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave = XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 regs) - 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave = XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs) - 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave = XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 regs) - 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave = XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs) - 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave = XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs) - 0x12, 1, ecx, 9, xfrm_pkru , Enclave = XFRM.PKRU (bit 9) supported (XSAVE PKRU reg) + 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave = XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 registers) + 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave = XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers) + 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave = XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 registers) + 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave = XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers) + 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave = XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers) + 0x12, 1, ecx, 9, xfrm_pkru , Enclave = XFRM.PKRU (bit 9) supported (XSAVE PKRU registers) 0x12, 1, ecx, 17, xfrm_tileconfig , Enclave = XFRM.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG) 0x12, 1, ecx, 18, xfrm_tiledata , Enclave = XFRM.TILEDATA (bit 18) supported (AMX can manage TILEDATA) 0x12, 31:2, eax, 3:0, subleaf_type , Subleaf = type (dictates output layout) - 0x12, 31:2, eax, 31:12, epc_sec_base_addr_0 , EPC sect= ion base addr, bits[12:31] - 0x12, 31:2, ebx, 19:0, epc_sec_base_addr_1 , EPC sect= ion base addr, bits[32:51] + 0x12, 31:2, eax, 31:12, epc_sec_base_addr_0 , EPC sect= ion base address, bits[12:31] + 0x12, 31:2, ebx, 19:0, epc_sec_base_addr_1 , EPC sect= ion base address, bits[32:51] 0x12, 31:2, ecx, 3:0, epc_sec_type , EPC sect= ion type / property encoding 0x12, 31:2, ecx, 31:12, epc_sec_size_0 , EPC sect= ion size, bits[12:31] 0x12, 31:2, edx, 19:0, epc_sec_size_1 , EPC sect= ion size, bits[32:51] @@ -481,7 +481,7 @@ 0x15, 0, ecx, 31:0, cpu_crystal_hz , Core cry= stal clock nominal frequency, in Hz =20 # Leaf 16H -# Intel processor fequency enumeration +# Intel processor frequency enumeration =20 0x16, 0, eax, 15:0, cpu_base_mhz , Processo= r base frequency, in MHz 0x16, 0, ebx, 15:0, cpu_max_mhz , Processo= r max frequency, in MHz @@ -492,7 +492,7 @@ =20 0x17, 0, eax, 31:0, soc_max_subleaf , Max cpui= d leaf 0x17 subleaf 0x17, 0, ebx, 15:0, soc_vendor_id , SoC vend= or ID - 0x17, 0, ebx, 16, is_vendor_scheme , Assigned= by industry enumaeratoion scheme (not Intel) + 0x17, 0, ebx, 16, is_vendor_scheme , Assigned= by industry enumeration scheme (not Intel) 0x17, 0, ecx, 31:0, soc_proj_id , SoC proj= ect ID, assigned by vendor 0x17, 0, edx, 31:0, soc_stepping_id , Soc proj= ect stepping ID, assigned by vendor 0x17, 3:1, eax, 31:0, vendor_brand_a , Vendor B= rand ID string, bytes subleaf_nr * (0 -> 3) @@ -508,13 +508,13 @@ 0x18, 31:0, ebx, 1, tlb_2m_page , TLB 2MB-= page entries supported 0x18, 31:0, ebx, 2, tlb_4m_page , TLB 4MB-= page entries supported 0x18, 31:0, ebx, 3, tlb_1g_page , TLB 1GB-= page entries supported - 0x18, 31:0, ebx, 10:8, hard_partitioning , (Hard/So= ft) partitioning between logical CPUs sharing this struct + 0x18, 31:0, ebx, 10:8, hard_partitioning , (Hard/So= ft) partitioning between logical CPUs sharing this structure 0x18, 31:0, ebx, 31:16, n_way_associative , Ways of = associativity 0x18, 31:0, ecx, 31:0, n_sets , Number o= f sets 0x18, 31:0, edx, 4:0, tlb_type , Translat= ion cache type (TLB type) 0x18, 31:0, edx, 7:5, tlb_cache_level , Translat= ion cache level (1-based) 0x18, 31:0, edx, 8, is_fully_associative , Fully-as= sociative structure - 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max num = of addressible IDs for logical CPUs sharing this TLB - 1 + 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max numb= er of addressable IDs for logical CPUs sharing this TLB - 1 =20 # Leaf 19H # Intel Key Locker enumeration @@ -577,7 +577,7 @@ # Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration =20 0x1e, 0, ebx, 7:0, tmul_maxk , TMUL uni= t maximum height, K (rows or columns) - 0x1e, 0, ebx, 23:8, tmul_maxn , TMUL uni= t maxiumum SIMD dimension, N (column bytes) + 0x1e, 0, ebx, 23:8, tmul_maxn , TMUL uni= t maximum SIMD dimension, N (column bytes) =20 # Leaf 1FH # Intel extended topology enumeration v2 @@ -733,9 +733,9 @@ # Leaf 80000005H # AMD/Transmeta L1 cache and L1 TLB enumeration =20 -0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB = #entires, 2M and 4M pages +0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB = #entries, 2M and 4M pages 0x80000005, 0, eax, 15:8, l1_itlb_2m_4m_assoc , L1 ITLB = associativity, 2M and 4M pages -0x80000005, 0, eax, 23:16, l1_dtlb_2m_4m_nentries , L1 DTLB = #entires, 2M and 4M pages +0x80000005, 0, eax, 23:16, l1_dtlb_2m_4m_nentries , L1 DTLB = #entries, 2M and 4M pages 0x80000005, 0, eax, 31:24, l1_dtlb_2m_4m_assoc , L1 DTLB = associativity, 2M and 4M pages 0x80000005, 0, ebx, 7:0, l1_itlb_4k_nentries , L1 ITLB = #entries, 4K pages 0x80000005, 0, ebx, 15:8, l1_itlb_4k_assoc , L1 ITLB = associativity, 4K pages @@ -774,11 +774,11 @@ # CPU power management (mostly AMD) and AMD RAS enumeration =20 0x80000007, 0, ebx, 0, overflow_recov , MCA over= flow conditions not fatal -0x80000007, 0, ebx, 1, succor , Software= containment of UnCORRectable errors +0x80000007, 0, ebx, 1, succor , Software= containment of uncorrectable errors 0x80000007, 0, ebx, 2, hw_assert , Hardware= assert MSRs 0x80000007, 0, ebx, 3, smca , Scalable= MCA (MCAX MSRs) 0x80000007, 0, ecx, 31:0, cpu_pwr_sample_ratio , CPU powe= r sample time ratio -0x80000007, 0, edx, 0, digital_temp , Digital = temprature sensor +0x80000007, 0, edx, 0, digital_temp , Digital = temperature sensor 0x80000007, 0, edx, 1, powernow_freq_id , PowerNOW= ! frequency scaling 0x80000007, 0, edx, 2, powernow_volt_id , PowerNOW= ! voltage scaling 0x80000007, 0, edx, 3, thermal_trip , THERMTRI= P (Thermal Trip) @@ -821,7 +821,7 @@ 0x80000008, 0, ebx, 23, amd_ppin , Protecte= d Processor Inventory Number 0x80000008, 0, ebx, 24, amd_ssbd , Speculat= ive Store Bypass Disable 0x80000008, 0, ebx, 25, virt_ssbd , virtuali= zed SSBD (Speculative Store Bypass Disable) -0x80000008, 0, ebx, 26, amd_ssb_no , SSBD not= needed (fixed in HW) +0x80000008, 0, ebx, 26, amd_ssb_no , SSBD is = not needed (fixed in hardware) 0x80000008, 0, ebx, 27, cppc , Collabor= ative Processor Performance Control 0x80000008, 0, ebx, 28, amd_psfd , Predicti= ve Store Forward Disable 0x80000008, 0, ebx, 29, btc_no , CPU not = affected by Branch Type Confusion @@ -849,7 +849,7 @@ 0x8000000a, 0, edx, 10, pausefilter , Pause in= tercept filter 0x8000000a, 0, edx, 12, pfthreshold , Pause fi= lter threshold 0x8000000a, 0, edx, 13, avic , Advanced= virtual interrupt controller -0x8000000a, 0, edx, 15, v_vmsave_vmload , Virtual = VMSAVE/VMLOAD (nested virt) +0x8000000a, 0, edx, 15, v_vmsave_vmload , Virtual = VMSAVE/VMLOAD (nested virtualization) 0x8000000a, 0, edx, 16, vgif , Virtuali= ze the Global Interrupt Flag 0x8000000a, 0, edx, 17, gmet , Guest mo= de execution trap 0x8000000a, 0, edx, 18, x2avic , Virtual = x2APIC @@ -861,7 +861,7 @@ 0x8000000a, 0, edx, 25, vnmi , NMI virt= ualization 0x8000000a, 0, edx, 26, ibs_virt , IBS Virt= ualization 0x8000000a, 0, edx, 27, ext_lvt_off_chg , Extended= LVT offset fault change -0x8000000a, 0, edx, 28, svme_addr_chk , Guest SV= ME addr check +0x8000000a, 0, edx, 28, svme_addr_chk , Guest SV= ME address check =20 # Leaf 80000019H # AMD TLB 1G-pages enumeration @@ -902,20 +902,20 @@ # AMD LWP (Lightweight Profiling) =20 0x8000001c, 0, eax, 0, os_lwp_avail , LWP is a= vailable to application programs (supported by OS) -0x8000001c, 0, eax, 1, os_lpwval , LWPVAL i= nstruction (EventId=3D1) is supported by OS -0x8000001c, 0, eax, 2, os_lwp_ire , Instruct= ions Retired Event (EventId=3D2) is supported by OS -0x8000001c, 0, eax, 3, os_lwp_bre , Branch R= etired Event (EventId=3D3) is supported by OS -0x8000001c, 0, eax, 4, os_lwp_dme , DCache M= iss Event (EventId=3D4) is supported by OS -0x8000001c, 0, eax, 5, os_lwp_cnh , CPU Cloc= ks Not Halted event (EventId=3D5) is supported by OS -0x8000001c, 0, eax, 6, os_lwp_rnh , CPU Refe= rence clocks Not Halted event (EventId=3D6) is supported by OS +0x8000001c, 0, eax, 1, os_lpwval , LWPVAL i= nstruction is supported by OS +0x8000001c, 0, eax, 2, os_lwp_ire , Instruct= ions Retired Event is supported by OS +0x8000001c, 0, eax, 3, os_lwp_bre , Branch R= etired Event is supported by OS +0x8000001c, 0, eax, 4, os_lwp_dme , Dcache M= iss Event is supported by OS +0x8000001c, 0, eax, 5, os_lwp_cnh , CPU Cloc= ks Not Halted event is supported by OS +0x8000001c, 0, eax, 6, os_lwp_rnh , CPU Refe= rence clocks Not Halted event is supported by OS 0x8000001c, 0, eax, 29, os_lwp_cont , LWP samp= ling in continuous mode is supported by OS 0x8000001c, 0, eax, 30, os_lwp_ptsc , Performa= nce Time Stamp Counter in event records is supported by OS 0x8000001c, 0, eax, 31, os_lwp_int , Interrup= t on threshold overflow is supported by OS 0x8000001c, 0, ebx, 7:0, lwp_lwpcb_sz , LWP Cont= rol Block size, in quadwords 0x8000001c, 0, ebx, 15:8, lwp_event_sz , LWP even= t record size, in bytes -0x8000001c, 0, ebx, 23:16, lwp_max_events , LWP max = supported EventId value (EventID 255 not included) +0x8000001c, 0, ebx, 23:16, lwp_max_events , LWP max = supported EventID value (EventID 255 not included) 0x8000001c, 0, ebx, 31:24, lwp_event_offset , LWP even= ts area offset in the LWP Control Block -0x8000001c, 0, ecx, 4:0, lwp_latency_max , Num of b= its in cache latency counters (10 to 31) +0x8000001c, 0, ecx, 4:0, lwp_latency_max , Number o= f bits in cache latency counters (10 to 31) 0x8000001c, 0, ecx, 5, lwp_data_adddr , Cache mi= ss events report the data address of the reference 0x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Amount b= y which cache latency is rounded 0x8000001c, 0, ecx, 15:9, lwp_version , LWP impl= ementation version @@ -924,16 +924,16 @@ 0x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filte= ring (IPI, IPF, BaseIP, and LimitIP @ LWPCP) supported 0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-re= lated events can be filtered by cache level 0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-re= lated events can be filtered by latency -0x8000001c, 0, edx, 0, hw_lwp_avail , LWP is a= vailable in Hardware -0x8000001c, 0, edx, 1, hw_lpwval , LWPVAL i= nstruction (EventId=3D1) is available in HW -0x8000001c, 0, edx, 2, hw_lwp_ire , Instruct= ions Retired Event (EventId=3D2) is available in HW -0x8000001c, 0, edx, 3, hw_lwp_bre , Branch R= etired Event (EventId=3D3) is available in HW -0x8000001c, 0, edx, 4, hw_lwp_dme , DCache M= iss Event (EventId=3D4) is available in HW -0x8000001c, 0, edx, 5, hw_lwp_cnh , CPU Cloc= ks Not Halted event (EventId=3D5) is available in HW -0x8000001c, 0, edx, 6, hw_lwp_rnh , CPU Refe= rence clocks Not Halted event (EventId=3D6) is available in HW -0x8000001c, 0, edx, 29, hw_lwp_cont , LWP samp= ling in continuous mode is available in HW -0x8000001c, 0, edx, 30, hw_lwp_ptsc , Performa= nce Time Stamp Counter in event records is available in HW -0x8000001c, 0, edx, 31, hw_lwp_int , Interrup= t on threshold overflow is available in HW +0x8000001c, 0, edx, 0, hw_lwp_avail , LWP is a= vailable in hardware +0x8000001c, 0, edx, 1, hw_lpwval , LWPVAL i= nstruction is available in hardware +0x8000001c, 0, edx, 2, hw_lwp_ire , Instruct= ions Retired Event is available in hardware +0x8000001c, 0, edx, 3, hw_lwp_bre , Branch R= etired Event is available in hardware +0x8000001c, 0, edx, 4, hw_lwp_dme , Dcache M= iss Event is available in hardware +0x8000001c, 0, edx, 5, hw_lwp_cnh , Clocks N= ot Halted event is available in hardware +0x8000001c, 0, edx, 6, hw_lwp_rnh , Referenc= e clocks Not Halted event is available in hardware +0x8000001c, 0, edx, 29, hw_lwp_cont , LWP samp= ling in continuous mode is available in hardware +0x8000001c, 0, edx, 30, hw_lwp_ptsc , Performa= nce Time Stamp Counter in event records is available in hardware +0x8000001c, 0, edx, 31, hw_lwp_int , Interrup= t on threshold overflow is available in hardware =20 # Leaf 8000001DH # AMD deterministic cache parameters @@ -969,10 +969,10 @@ 0x8000001f, 0, eax, 4, sev_nested_paging , SEV secu= re nested paging supported 0x8000001f, 0, eax, 5, vm_permission_levels , VMPL sup= ported 0x8000001f, 0, eax, 6, rpmquery , RPMQUERY= instruction supported -0x8000001f, 0, eax, 7, vmpl_sss , VMPL sup= ervisor shadwo stack supported +0x8000001f, 0, eax, 7, vmpl_sss , VMPL sup= ervisor shadow stack supported 0x8000001f, 0, eax, 8, secure_tsc , Secure T= SC supported 0x8000001f, 0, eax, 9, v_tsc_aux , Hardware= virtualizes TSC_AUX -0x8000001f, 0, eax, 10, sme_coherent , HW enfor= ces cache coherency across encryption domains +0x8000001f, 0, eax, 10, sme_coherent , Cache co= herency is enforced across encryption domains 0x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV gues= t mandates 64-bit hypervisor 0x8000001f, 0, eax, 12, restricted_injection , Restrict= ed Injection supported 0x8000001f, 0, eax, 13, alternate_injection , Alternat= e Injection supported @@ -984,13 +984,13 @@ 0x8000001f, 0, eax, 19, virt_ibs , IBS stat= e virtualization is supported for SEV-ES guests 0x8000001f, 0, eax, 24, vmsa_reg_protection , VMSA reg= ister protection is supported 0x8000001f, 0, eax, 25, smt_protection , SMT prot= ection is supported -0x8000001f, 0, eax, 28, svsm_page_msr , SVSM com= munication page MSR (0xc001f000h) is supported +0x8000001f, 0, eax, 28, svsm_page_msr , SVSM com= munication page MSR (0xc001f000) is supported 0x8000001f, 0, eax, 29, nested_virt_snp_msr , VIRT_RMP= UPDATE/VIRT_PSMASH MSRs are supported 0x8000001f, 0, ebx, 5:0, pte_cbit_pos , PTE bit = number used to enable memory encryption 0x8000001f, 0, ebx, 11:6, phys_addr_reduction_nbits, Reduct= ion of phys address space when encryption is enabled, in bits 0x8000001f, 0, ebx, 15:12, vmpl_count , Number o= f VM permission levels (VMPL) supported 0x8000001f, 0, ecx, 31:0, enc_guests_max , Max supp= orted number of simultaneous encrypted guests -0x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Mininum = ASID for SEV-enabled SEV-ES-disabled guest +0x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Minimum = ASID for SEV-enabled SEV-ES-disabled guest =20 # Leaf 80000020H # AMD Platform QoS extended feature IDs @@ -999,6 +999,8 @@ 0x80000020, 0, ebx, 2, smba , Slow Mem= ory Bandwidth Allocation support 0x80000020, 0, ebx, 3, bmec , Bandwidt= h Monitoring Event Configuration support 0x80000020, 0, ebx, 4, l3rr , L3 Range= Reservation support +0x80000020, 0, ebx, 5, abmc , Assignab= le Bandwidth Monitoring Counters +0x80000020, 0, ebx, 6, sdciae , Smart Da= ta Cache Injection (SDCI) Allocation Enforcement 0x80000020, 1, eax, 31:0, mba_limit_len , MBA enfo= rcement limit size 0x80000020, 1, edx, 31:0, mba_cos_max , MBA max = Class of Service number (zero-based) 0x80000020, 2, eax, 31:0, smba_limit_len , SMBA enf= orcement limit size @@ -1023,12 +1025,21 @@ 0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR= Upper Address Ignore Enable bit supported 0x80000021, 0, eax, 8, autoibrs , EFER MSR= Automatic IBRS enable bit supported 0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL = MSR (0xc0010116) is not present -0x80000021, 0, eax, 10, fsrs_supported , Fast Sho= rt Rep Stosb (FSRS) is supported -0x80000021, 0, eax, 11, fsrc_supported , Fast Sho= rt Repe Cmpsb (FSRC) is supported +0x80000021, 0, eax, 10, fsrs_supported , Fast Sho= rt Rep STOSB (FSRS) is supported +0x80000021, 0, eax, 11, fsrc_supported , Fast Sho= rt Rep CMPSB (FSRC) is supported 0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch= control MSR is supported +0x80000021, 0, eax, 16, opcode_reclaim , Reserves= opcode space 0x80000021, 0, eax, 17, user_cpuid_disable , #GP when= executing CPUID at CPL > 0 is supported 0x80000021, 0, eax, 18, epsf_supported , Enhanced= Predictive Store Forwarding (EPSF) is supported -0x80000021, 0, ebx, 11:0, microcode_patch_size , Size of = microcode patch, in 16-byte units +0x80000021, 0, eax, 22, wl_feedback , Workload= -based heuristic feedback to OS +0x80000021, 0, eax, 24, eraps_support , Enhanced= Return Address Predictor Security +0x80000021, 0, eax, 27, sbpb , Support = for the Selective Branch Predictor Barrier +0x80000021, 0, eax, 28, ibpb_brtype , Branch p= redictions flushed from CPU branch predictor +0x80000021, 0, eax, 29, srso_no , CPU is n= ot subject to the SRSO vulnerability +0x80000021, 0, eax, 30, srso_uk_no , CPU is n= ot vulnerable to SRSO at user-kernel boundary +0x80000021, 0, eax, 31, srso_msr_fix , Software= may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO +0x80000021, 0, ebx, 15:0, microcode_patch_size , Size of = microcode patch, in 16-byte units +0x80000021, 0, ebx, 23:16, rap_size , Return A= ddress Predictor size =20 # Leaf 80000022H # AMD Performance Monitoring v2 enumeration @@ -1036,7 +1047,7 @@ 0x80000022, 0, eax, 0, perfmon_v2 , Performa= nce monitoring v2 supported 0x80000022, 0, eax, 1, lbr_v2 , Last Bra= nch Record v2 extensions (LBR Stack) 0x80000022, 0, eax, 2, lbr_pmc_freeze , Freezing= core performance counters / LBR Stack supported -0x80000022, 0, ebx, 3:0, n_pmc_core , Number o= f core perfomance counters +0x80000022, 0, ebx, 3:0, n_pmc_core , Number o= f core performance counters 0x80000022, 0, ebx, 9:4, lbr_v2_stack_size , Number o= f available LBR stack entries 0x80000022, 0, ebx, 15:10, n_pmc_northbridge , Number o= f available northbridge (data fabric) performance counters 0x80000022, 0, ebx, 21:16, n_pmc_umc , Number o= f available UMC performance counters @@ -1046,7 +1057,7 @@ # AMD Secure Multi-key Encryption enumeration =20 0x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK = encryption mode is supported -0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , MEM-HMK = mode: total num of available encryption keys +0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , MEM-HMK = mode: total number of available encryption keys =20 # Leaf 80000026H # AMD extended topology enumeration v2 @@ -1134,7 +1145,7 @@ =20 0x80860007, 0, eax, 31:0, cpu_cur_mhz , Current = CPU frequency, in MHz 0x80860007, 0, ebx, 31:0, cpu_cur_voltage , Current = CPU voltage, in millivolts -0x80860007, 0, ecx, 31:0, cpu_cur_perf_pctg , Current = CPU performance percentage, 0 - 100d +0x80860007, 0, ecx, 31:0, cpu_cur_perf_pctg , Current = CPU performance percentage, 0 - 100 0x80860007, 0, edx, 31:0, cpu_cur_gate_delay , Current = CPU gate delay, in femtoseconds =20 # Leaf C0000000H --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D66123A563 for ; Wed, 12 Mar 2025 14:38:44 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 18/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.2 Date: Wed, 12 Mar 2025 15:37:35 +0100 Message-ID: <20250312143738.458507-19-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update kcpuid's CSV file to version 2.2, as generated by x86-cpuid-db. Per Ingo Molnar's feedback, it is desired to always use CPUID in its capitalized form. The v2.2 release fixed all instances of small case "cpuid" at the project's XML database, and thus all of its generated files. Reported-by: Ingo Molnar Closes: https://lkml.kernel.org/r/Z8bHK391zKE4gUEW@gmail.com Signed-off-by: Ahmed S. Darwish Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.2/CHANGELOG.r= st --- tools/arch/x86/kcpuid/cpuid.csv | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.= csv index 0f9c11208674..9613e09cbfb3 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,5 +1,5 @@ # SPDX-License-Identifier: CC0-1.0 -# Generator: x86-cpuid-db v2.1 +# Generator: x86-cpuid-db v2.2 =20 # # Auto-generated file. @@ -12,7 +12,7 @@ # Leaf 0H # Maximum standard leaf number + CPU vendor string =20 - 0x0, 0, eax, 31:0, max_std_leaf , Highest = cpuid standard leaf supported + 0x0, 0, eax, 31:0, max_std_leaf , Highest = standard CPUID leaf supported 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vend= or ID string bytes 0 - 3 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vend= or ID string bytes 8 - 11 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vend= or ID string bytes 4 - 7 @@ -193,7 +193,7 @@ # Leaf 7H # Extended CPU features enumeration =20 - 0x7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f cpuid 0x7 subleaves + 0x7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f leaf 0x7 subleaves 0x7, 0, ebx, 0, fsgsbase , FSBASE/G= SBASE read/write support 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC= _ADJUST MSR supported 0x7, 0, ebx, 2, sgx , Intel SG= X (Software Guard Extensions) @@ -281,7 +281,7 @@ 0x7, 1, eax, 5, avx512_bf16 , AVX-512 = bfloat16 instructions 0x7, 1, eax, 6, lass , Linear a= ddress space separation 0x7, 1, eax, 7, cmpccxadd , CMPccXAD= D instructions - 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: CPUID leaf 0x23 is supported + 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: leaf 0x23 is supported 0x7, 1, eax, 10, fzrm , Fast zer= o-length REP MOVSB 0x7, 1, eax, 11, fsrs , Fast sho= rt REP STOSB 0x7, 1, eax, 12, fsrc , Fast Sho= rt REP CMPSB/SCASB @@ -319,7 +319,7 @@ 0xa, 0, eax, 7:0, pmu_version , Performa= nce monitoring unit version ID 0xa, 0, eax, 15:8, pmu_n_gcounters , Number o= f general PMU counters per logical CPU 0xa, 0, eax, 23:16, pmu_gcounters_nbits , Bitwidth= of PMU general counters - 0xa, 0, eax, 31:24, pmu_cpuid_ebx_bits , Length o= f cpuid leaf 0xa EBX bit vector + 0xa, 0, eax, 31:24, pmu_cpuid_ebx_bits , Length o= f leaf 0xa EBX bit vector 0xa, 0, ebx, 0, no_core_cycle_evt , Core cyc= le event not available 0xa, 0, ebx, 1, no_insn_retired_evt , Instruct= ion retired event not available 0xa, 0, ebx, 2, no_refcycle_evt , Referenc= e cycles event not available @@ -453,7 +453,7 @@ # Leaf 14H # Intel Processor Trace enumeration =20 - 0x14, 0, eax, 31:0, pt_max_subleaf , Max cpui= d 0x14 subleaf + 0x14, 0, eax, 31:0, pt_max_subleaf , Maximum = leaf 0x14 subleaf 0x14, 0, ebx, 0, cr3_filtering , IA32_RTI= T_CR3_MATCH is accessible 0x14, 0, ebx, 1, psb_cyc , Configur= able PSB and cycle-accurate mode 0x14, 0, ebx, 2, ip_filtering , IP/Trace= Stop filtering; Warm-reset PT MSRs preservation @@ -490,7 +490,7 @@ # Leaf 17H # Intel SoC vendor attributes enumeration =20 - 0x17, 0, eax, 31:0, soc_max_subleaf , Max cpui= d leaf 0x17 subleaf + 0x17, 0, eax, 31:0, soc_max_subleaf , Maximum = leaf 0x17 subleaf 0x17, 0, ebx, 15:0, soc_vendor_id , SoC vend= or ID 0x17, 0, ebx, 16, is_vendor_scheme , Assigned= by industry enumeration scheme (not Intel) 0x17, 0, ecx, 31:0, soc_proj_id , SoC proj= ect ID, assigned by vendor @@ -503,7 +503,7 @@ # Leaf 18H # Intel determenestic address translation (TLB) parameters =20 - 0x18, 31:0, eax, 31:0, tlb_max_subleaf , Max cpui= d 0x18 subleaf + 0x18, 31:0, eax, 31:0, tlb_max_subleaf , Maximum = leaf 0x18 subleaf 0x18, 31:0, ebx, 0, tlb_4k_page , TLB 4KB-= page entries supported 0x18, 31:0, ebx, 1, tlb_2m_page , TLB 2MB-= page entries supported 0x18, 31:0, ebx, 2, tlb_4m_page , TLB 4MB-= page entries supported @@ -634,7 +634,7 @@ # Leaf 80000000H # Maximum extended leaf number + AMD/Transmeta CPU vendor string =20 -0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum = extended cpuid leaf supported +0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum = extended CPUID leaf supported 0x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor I= D string bytes 0 - 3 0x80000000, 0, ecx, 31:0, cpu_vendorid_2 , Vendor I= D string bytes 8 - 11 0x80000000, 0, edx, 31:0, cpu_vendorid_1 , Vendor I= D string bytes 4 - 7 @@ -669,7 +669,7 @@ 0x80000001, 0, ecx, 17, tce , Translat= ion cache extension 0x80000001, 0, ecx, 19, nodeid_msr , NodeId M= SR (0xc001100c) 0x80000001, 0, ecx, 21, tbm , Trailing= bit manipulations -0x80000001, 0, ecx, 22, topoext , Topology= Extensions (cpuid leaf 0x8000001d) +0x80000001, 0, ecx, 22, topoext , Topology= Extensions (leaf 0x8000001d) 0x80000001, 0, ecx, 23, perfctr_core , Core per= formance counter extensions 0x80000001, 0, ecx, 24, perfctr_nb , NB/DF pe= rformance counter extensions 0x80000001, 0, ecx, 26, bpext , Data acc= ess breakpoint extension --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C1D4252904 for ; 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 19/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.3 Date: Wed, 12 Mar 2025 15:37:36 +0100 Message-ID: <20250312143738.458507-20-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update kcpuid's CSV file to version 2.3, as generated by x86-cpuid-db. Summary of the v2.3 changes: * Per H. Peter Anvin's feedback, leaf 0x3 is not unique to Transmeta as the CSV file earlier claimed. Since leaf 0x3's format differs between Intel and Transmeta, and the project does not yet support having the same CPUID bitfield with varying interpretations across vendors, leaf 0x3 is removed for now. Given that Intel discontinued support for PSN from Pentium 4 onward, and Linux force disables it on early boot for privacy concerns, this should have minimal impact. * Leaf 0x80000021: Make bitfield IDs and descriptions coherent with each other. Remove "_support" from bitfield IDs, as no other leaf has such convention. Reported-by: "H. Peter Anvin" Closes: https://lkml.kernel.org/r/C7684E03-36E0-4D58-B6F0-78F4DB82D737@zyto= r.com Signed-off-by: Ahmed S. Darwish Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.3/CHANGELOG.r= st --- tools/arch/x86/kcpuid/cpuid.csv | 30 +++++++++++------------------- 1 file changed, 11 insertions(+), 19 deletions(-) diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.= csv index 9613e09cbfb3..8d25b0b49f3b 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,5 +1,5 @@ # SPDX-License-Identifier: CC0-1.0 -# Generator: x86-cpuid-db v2.2 +# Generator: x86-cpuid-db v2.3 =20 # # Auto-generated file. @@ -116,14 +116,6 @@ 0x2, 0, edx, 30:24, desc15 , Descript= or #15 0x2, 0, edx, 31, edx_invalid , Descript= ors 12-15 are invalid if set =20 -# Leaf 3H -# Transmeta Processor Serial Number (PSN) - - 0x3, 0, eax, 31:0, cpu_psn_0 , Processo= r Serial Number bytes 0 - 3 - 0x3, 0, ebx, 31:0, cpu_psn_1 , Processo= r Serial Number bytes 4 - 7 - 0x3, 0, ecx, 31:0, cpu_psn_2 , Processo= r Serial Number bytes 8 - 11 - 0x3, 0, edx, 31:0, cpu_psn_3 , Processo= r Serial Number bytes 12 - 15 - # Leaf 4H # Intel deterministic cache parameters =20 @@ -1020,20 +1012,20 @@ 0x80000021, 0, eax, 0, no_nested_data_bp , No neste= d data breakpoints 0x80000021, 0, eax, 1, fsgs_non_serializing , WRMSR to= {FS,GS,KERNEL_GS}_BASE is non-serializing 0x80000021, 0, eax, 2, lfence_rdtsc , LFENCE a= lways serializing / synchronizes RDTSC -0x80000021, 0, eax, 3, smm_page_cfg_lock , SMM pagi= ng configuration lock is supported +0x80000021, 0, eax, 3, smm_page_cfg_lock , SMM pagi= ng configuration lock 0x80000021, 0, eax, 6, null_sel_clr_base , Null sel= ector clears base -0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR= Upper Address Ignore Enable bit supported -0x80000021, 0, eax, 8, autoibrs , EFER MSR= Automatic IBRS enable bit supported -0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL = MSR (0xc0010116) is not present -0x80000021, 0, eax, 10, fsrs_supported , Fast Sho= rt Rep STOSB (FSRS) is supported -0x80000021, 0, eax, 11, fsrc_supported , Fast Sho= rt Rep CMPSB (FSRC) is supported -0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch= control MSR is supported +0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR= Upper Address Ignore +0x80000021, 0, eax, 8, autoibrs , EFER MSR= Automatic IBRS +0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL = MSR (0xc0010116) is not available +0x80000021, 0, eax, 10, fsrs , Fast Sho= rt Rep STOSB +0x80000021, 0, eax, 11, fsrc , Fast Sho= rt Rep CMPSB +0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch= control MSR is available 0x80000021, 0, eax, 16, opcode_reclaim , Reserves= opcode space 0x80000021, 0, eax, 17, user_cpuid_disable , #GP when= executing CPUID at CPL > 0 is supported -0x80000021, 0, eax, 18, epsf_supported , Enhanced= Predictive Store Forwarding (EPSF) is supported +0x80000021, 0, eax, 18, epsf , Enhanced= Predictive Store Forwarding 0x80000021, 0, eax, 22, wl_feedback , Workload= -based heuristic feedback to OS -0x80000021, 0, eax, 24, eraps_support , Enhanced= Return Address Predictor Security -0x80000021, 0, eax, 27, sbpb , Support = for the Selective Branch Predictor Barrier +0x80000021, 0, eax, 24, eraps , Enhanced= Return Address Predictor Security +0x80000021, 0, eax, 27, sbpb , Selectiv= e Branch Predictor Barrier 0x80000021, 0, eax, 28, ibpb_brtype , Branch p= redictions flushed from CPU branch predictor 0x80000021, 0, eax, 29, srso_no , CPU is n= ot subject to the SRSO vulnerability 0x80000021, 0, eax, 30, srso_uk_no , CPU is n= ot vulnerable to SRSO at user-kernel boundary --=20 2.48.1 From nobody Fri Dec 19 02:57:14 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48ABF258CFF for ; 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 20/20] MAINTAINERS: Include kcpuid under X86 CPUID DATABASE Date: Wed, 12 Mar 2025 15:37:37 +0100 Message-ID: <20250312143738.458507-21-darwi@linutronix.de> In-Reply-To: <20250312143738.458507-1-darwi@linutronix.de> References: <20250312143738.458507-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" kcpuid's CSV file is covered by the "x86 CPUID database" MAINTAINERS entry. Recent patches have shown that changes to that file may require updates to the kcpuid code, so include the whole of tools/x86/kcpuid under the same entry. This also ensures that myself and the x86-cpuid mailing list are CCed on future kcpuid patches. Signed-off-by: Ahmed S. Darwish --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index ed7aa6867674..ce2742712140 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25695,7 +25695,7 @@ R: Ahmed S. Darwish L: x86-cpuid@lists.linux.dev S: Maintained W: https://x86-cpuid.org -F: tools/arch/x86/kcpuid/cpuid.csv +F: tools/arch/x86/kcpuid/ =20 X86 ENTRY CODE M: Andy Lutomirski --=20 2.48.1