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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2025 09:54:22.3670 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a3ad9894-b4ba-452c-6a00-08dd614bdd97 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8036 Content-Type: text/plain; charset="utf-8" AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. Modify existing binding description, pcs-handle description and add 2500base-x in phy-mode for 2500base-X only configuration. Signed-off-by: Suraj Gupta --- .../devicetree/bindings/net/xlnx,axi-ethernet.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b= /Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml index fb02e579463c..977f55b98f31 100644 --- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml +++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml @@ -9,10 +9,12 @@ title: AXI 1G/2.5G Ethernet Subsystem description: | Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP = core provides connectivity to an external ethernet PHY supporting different - interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two + interfaces: MII, GMII, RGMII, SGMII, 1000BaseX and 2500BaseX. It also in= cludes two segments of memory for buffering TX and RX, as well as the capability of offloading TX/RX checksum calculation off the processor. =20 + AXI 2.5G MAC is incremental speed upgrade of AXI 1G and supports 2.5G sp= eed. + Management configuration is done through the AXI interface, while payloa= d is sent and received through means of an AXI DMA controller. This driver includes the DMA driver code, so this driver is incompatible with AXI DMA @@ -62,6 +64,7 @@ properties: - rgmii - sgmii - 1000base-x + - 2500base-x =20 xlnx,phy-type: description: @@ -118,8 +121,8 @@ properties: type: object =20 pcs-handle: - description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X - modes, where "pcs-handle" should be used to point to the PCS/PMA PHY, + description: Phandle to the internal PCS/PMA PHY in SGMII or 1000base-= x/ + 2500base-x modes, where "pcs-handle" should be used to point to the = PCS/PMA PHY, and "phy-handle" should point to an external PHY if exists. maxItems: 1 =20 --=20 2.25.1 From nobody Tue Dec 16 11:08:28 2025 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2078.outbound.protection.outlook.com [40.107.94.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC21A23C376; Wed, 12 Mar 2025 09:54:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Add support for 2500base-X only configuration. Co-developed-by: Harini Katakam Signed-off-by: Harini Katakam Signed-off-by: Suraj Gupta --- drivers/net/ethernet/xilinx/xilinx_axienet.h | 2 +- .../net/ethernet/xilinx/xilinx_axienet_main.c | 24 +++++++++++++++---- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/eth= ernet/xilinx/xilinx_axienet.h index 5ff742103beb..ded3e32999d5 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -274,7 +274,7 @@ #define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */ #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ -#define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit = */ +#define XAE_EMMC_LINKSPD_1000_2500 0x80000000 /* Link Speed mask for 1000 = or 2500 Mbit */ =20 /* Bit masks for Axi Ethernet PHYC register */ #define XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/ diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/ne= t/ethernet/xilinx/xilinx_axienet_main.c index 054abf283ab3..0885ce201b0a 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -2583,6 +2583,7 @@ static struct phylink_pcs *axienet_mac_select_pcs(str= uct phylink_config *config, struct axienet_local *lp =3D netdev_priv(ndev); =20 if (interface =3D=3D PHY_INTERFACE_MODE_1000BASEX || + interface =3D=3D PHY_INTERFACE_MODE_2500BASEX || interface =3D=3D PHY_INTERFACE_MODE_SGMII) return &lp->pcs; =20 @@ -2616,8 +2617,9 @@ static void axienet_mac_link_up(struct phylink_config= *config, emmc_reg &=3D ~XAE_EMMC_LINKSPEED_MASK; =20 switch (speed) { + case SPEED_2500: case SPEED_1000: - emmc_reg |=3D XAE_EMMC_LINKSPD_1000; + emmc_reg |=3D XAE_EMMC_LINKSPD_1000_2500; break; case SPEED_100: emmc_reg |=3D XAE_EMMC_LINKSPD_100; @@ -2627,7 +2629,7 @@ static void axienet_mac_link_up(struct phylink_config= *config, break; default: dev_err(&ndev->dev, - "Speed other than 10, 100 or 1Gbps is not supported\n"); + "Speed other than 10, 100, 1Gbps or 2.5Gbps is not supported\n"); break; } =20 @@ -3055,7 +3057,8 @@ static int axienet_probe(struct platform_device *pdev) "error registering MDIO bus: %d\n", ret); =20 if (lp->phy_mode =3D=3D PHY_INTERFACE_MODE_SGMII || - lp->phy_mode =3D=3D PHY_INTERFACE_MODE_1000BASEX) { + lp->phy_mode =3D=3D PHY_INTERFACE_MODE_1000BASEX || + lp->phy_mode =3D=3D PHY_INTERFACE_MODE_2500BASEX) { np =3D of_parse_phandle(pdev->dev.of_node, "pcs-handle", 0); if (!np) { /* Deprecated: Always use "pcs-handle" for pcs_phy. @@ -3083,8 +3086,19 @@ static int axienet_probe(struct platform_device *pde= v) lp->phylink_config.dev =3D &ndev->dev; lp->phylink_config.type =3D PHYLINK_NETDEV; lp->phylink_config.mac_managed_pm =3D true; - lp->phylink_config.mac_capabilities =3D MAC_SYM_PAUSE | MAC_ASYM_PAUSE | - MAC_10FD | MAC_100FD | MAC_1000FD; + lp->phylink_config.mac_capabilities =3D MAC_SYM_PAUSE | MAC_ASYM_PAUSE; + + /* AXI 1G/2.5G ethernet IP has following synthesis options: + * 1) SGMII/1000base-X only. + * 2) 2500base-X only. + * 3) Dynamically switching between (1) and (2), and is not + * implemented in driver. + */ + + if (axienet_ior(lp, XAE_ABILITY_OFFSET) & XAE_ABILITY_2_5G) + lp->phylink_config.mac_capabilities |=3D MAC_2500FD; + else + lp->phylink_config.mac_capabilities |=3D MAC_10FD | MAC_100FD | MAC_1000= FD; =20 __set_bit(lp->phy_mode, lp->phylink_config.supported_interfaces); if (lp->switch_x_sgmii) { --=20 2.25.1