From nobody Fri Dec 19 19:33:52 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 101741E5713 for ; Wed, 12 Mar 2025 06:42:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741761772; cv=none; b=V7qtO5skk6vvKUQkbx6QAQmtXAIPmq8+kn+rKM8q8saAihweDiAEbzqSGqub4ipC1r6lT8Eegb6os5MsRfVy7xEpfXKQP58m9S8KjuiW3LQZM9z+SBQfY0FtWHKjcYlAH6Ld0QHy3sLJsTHTKxVXVqOTI+TSOx1x5W0sQmsU86I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741761772; c=relaxed/simple; bh=BXxmNwAR3XD+Lwcg6vWkjZWpbgVFft4baYm+h8YFV/Y=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=LQBAAjP0XvcA0XMW31esSn5hTcs0wWVN90R+N6Vd3aa6hXvHnv5NGGA8IqhbEV/gh2ttL3JfaEcA8h2F5SavU69JiX14PkMPMLdq4UbWDVVOYspd2i3STLQw8bjsAOIHQX/JPXidzm4YjZ9now4YVmf8u+jATkLt78x0KlMgTJU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=otuhekoT; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="otuhekoT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-ID:MIME-Version; bh=Y9A+G MGKN+/gUY1pm2Jf9qbSfuZPHc1NStiINtfiC4E=; b=otuhekoTwyJx+JqzGhknl /Iv7vVn5kEHxqjM52cwGzgtak+d431j79xyTzrismLDKslKWhSqlTn2MS2U1hNdE qYnxFLnpq1cDQLlFlXm4MJdqJO0UwhXd99Z+zVxZQ1jYNzw8O+d2KEc0SbRiX7Qc nMcy8ciC2LTSJWZfaSDNak= Received: from ProDesk.. (unknown []) by gzga-smtp-mtada-g1-0 (Coremail) with SMTP id _____wAnro3MLNFnNsQBSQ--.34149S2; Wed, 12 Mar 2025 14:42:23 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, piotr.oniszczuk@gmail.com, Andy Yan Subject: [PATCH] drm/rockchip: vop2: Fix interface enable/mux setting of DP1 on rk3588 Date: Wed, 12 Mar 2025 14:42:10 +0800 Message-ID: <20250312064218.524143-1-andyshrk@163.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wAnro3MLNFnNsQBSQ--.34149S2 X-Coremail-Antispam: 1Uf129KBjvJXoW7Cw1rKFyDJrWUWr1DGFWfKrg_yoW8JFW7pr s0yryYqrWkKrWjvF1fGF4Fyr4SkanFkayIka1fKa9xGa48tr1kGr98Ja1kAry7Xr17ZFyj krZIyrW3uFW2yFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jbwIDUUUUU= X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbB0hYOXmfRJTn62wAAsf Content-Type: text/plain; charset="utf-8" From: Andy Yan This is a copy-paste error, which affects DP1 usage. Fixes: 328e6885996c ("drm/rockchip: vop2: Add platform specific callback") Signed-off-by: Andy Yan --- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm= /rockchip/rockchip_vop2_reg.c index a8b1ebfc5af5..de2da4f4e434 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -1753,9 +1753,9 @@ static unsigned long rk3588_set_intf_mux(struct vop2_= video_port *vp, int id, u32 dip |=3D FIELD_PREP(RK3588_DSP_IF_POL__DP0_PIN_POL, polflags); break; case ROCKCHIP_VOP2_EP_DP1: - die &=3D ~RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX; - die |=3D RK3588_SYS_DSP_INFACE_EN_MIPI1 | - FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id); + die &=3D ~RK3588_SYS_DSP_INFACE_EN_DP1_MUX; + die |=3D RK3588_SYS_DSP_INFACE_EN_DP1 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_DP1_MUX, vp->id); dip &=3D ~RK3588_DSP_IF_POL__DP1_PIN_POL; dip |=3D FIELD_PREP(RK3588_DSP_IF_POL__DP1_PIN_POL, polflags); break; --=20 2.34.1