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charset="utf-8" There are many fuzzy register variables in the lpuart driver, such as temp, tmp, val, reg. Let's give these register variables more specific names. Signed-off-by: Sherry Sun --- drivers/tty/serial/fsl_lpuart.c | 220 ++++++++++++++++---------------- 1 file changed, 110 insertions(+), 110 deletions(-) diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuar= t.c index 3b48e320e7f4..c8cc0a241fba 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -441,36 +441,36 @@ static unsigned int lpuart_get_baud_clk_rate(struct l= puart_port *sport) =20 static void lpuart_stop_tx(struct uart_port *port) { - u8 temp; + u8 cr2; =20 - temp =3D readb(port->membase + UARTCR2); - temp &=3D ~(UARTCR2_TIE | UARTCR2_TCIE); - writeb(temp, port->membase + UARTCR2); + cr2 =3D readb(port->membase + UARTCR2); + cr2 &=3D ~(UARTCR2_TIE | UARTCR2_TCIE); + writeb(cr2, port->membase + UARTCR2); } =20 static void lpuart32_stop_tx(struct uart_port *port) { - u32 temp; + u32 ctrl; =20 - temp =3D lpuart32_read(port, UARTCTRL); - temp &=3D ~(UARTCTRL_TIE | UARTCTRL_TCIE); - lpuart32_write(port, temp, UARTCTRL); + ctrl =3D lpuart32_read(port, UARTCTRL); + ctrl &=3D ~(UARTCTRL_TIE | UARTCTRL_TCIE); + lpuart32_write(port, ctrl, UARTCTRL); } =20 static void lpuart_stop_rx(struct uart_port *port) { - u8 temp; + u8 cr2; =20 - temp =3D readb(port->membase + UARTCR2); - writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); + cr2 =3D readb(port->membase + UARTCR2); + writeb(cr2 & ~UARTCR2_RE, port->membase + UARTCR2); } =20 static void lpuart32_stop_rx(struct uart_port *port) { - u32 temp; + u32 ctrl; =20 - temp =3D lpuart32_read(port, UARTCTRL); - lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); + ctrl =3D lpuart32_read(port, UARTCTRL); + lpuart32_write(port, ctrl & ~UARTCTRL_RE, UARTCTRL); } =20 static void lpuart_dma_tx(struct lpuart_port *sport) @@ -599,7 +599,7 @@ static void lpuart_flush_buffer(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); struct dma_chan *chan =3D sport->dma_tx_chan; - u32 val; + u32 fifo; =20 if (sport->lpuart_dma_tx_use) { if (sport->dma_tx_in_progress) { @@ -611,13 +611,13 @@ static void lpuart_flush_buffer(struct uart_port *por= t) } =20 if (lpuart_is_32(sport)) { - val =3D lpuart32_read(port, UARTFIFO); - val |=3D UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; - lpuart32_write(port, val, UARTFIFO); + fifo =3D lpuart32_read(port, UARTFIFO); + fifo |=3D UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; + lpuart32_write(port, fifo, UARTFIFO); } else { - val =3D readb(port->membase + UARTCFIFO); - val |=3D UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; - writeb(val, port->membase + UARTCFIFO); + fifo =3D readb(port->membase + UARTCFIFO); + fifo |=3D UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; + writeb(fifo, port->membase + UARTCFIFO); } } =20 @@ -642,7 +642,7 @@ static int lpuart_poll_init(struct uart_port *port) struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port); unsigned long flags; - u8 temp; + u8 fifo; =20 port->fifosize =3D 0; =20 @@ -650,9 +650,9 @@ static int lpuart_poll_init(struct uart_port *port) /* Disable Rx & Tx */ writeb(0, port->membase + UARTCR2); =20 - temp =3D readb(port->membase + UARTPFIFO); + fifo =3D readb(port->membase + UARTPFIFO); /* Enable Rx and Tx FIFO */ - writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, + writeb(fifo | UARTPFIFO_RXFE | UARTPFIFO_TXFE, port->membase + UARTPFIFO); =20 /* flush Tx and Rx FIFO */ @@ -694,7 +694,7 @@ static int lpuart32_poll_init(struct uart_port *port) { unsigned long flags; struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); - u32 temp; + u32 fifo; =20 port->fifosize =3D 0; =20 @@ -703,10 +703,10 @@ static int lpuart32_poll_init(struct uart_port *port) /* Disable Rx & Tx */ lpuart32_write(port, 0, UARTCTRL); =20 - temp =3D lpuart32_read(port, UARTFIFO); + fifo =3D lpuart32_read(port, UARTFIFO); =20 /* Enable Rx and Tx FIFO */ - lpuart32_write(port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); + lpuart32_write(port, fifo | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); =20 /* flush Tx and Rx FIFO */ lpuart32_write(port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); @@ -789,10 +789,10 @@ static void lpuart_start_tx(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port); - u8 temp; + u8 cr2; =20 - temp =3D readb(port->membase + UARTCR2); - writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); + cr2 =3D readb(port->membase + UARTCR2); + writeb(cr2 | UARTCR2_TIE, port->membase + UARTCR2); =20 if (sport->lpuart_dma_tx_use) { if (!lpuart_stopped_or_empty(port)) @@ -806,14 +806,14 @@ static void lpuart_start_tx(struct uart_port *port) static void lpuart32_start_tx(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); - u32 temp; + u32 ctrl; =20 if (sport->lpuart_dma_tx_use) { if (!lpuart_stopped_or_empty(port)) lpuart_dma_tx(sport); } else { - temp =3D lpuart32_read(port, UARTCTRL); - lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); + ctrl =3D lpuart32_read(port, UARTCTRL); + lpuart32_write(port, ctrl | UARTCTRL_TIE, UARTCTRL); =20 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) lpuart32_transmit_buffer(sport); @@ -1411,9 +1411,9 @@ static inline int lpuart_start_rx_dma(struct lpuart_p= ort *sport) dma_async_issue_pending(chan); =20 if (lpuart_is_32(sport)) { - u32 temp =3D lpuart32_read(&sport->port, UARTBAUD); + u32 baud =3D lpuart32_read(&sport->port, UARTBAUD); =20 - lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); + lpuart32_write(&sport->port, baud | UARTBAUD_RDMAE, UARTBAUD); =20 if (sport->dma_idle_int) { u32 ctrl =3D lpuart32_read(&sport->port, UARTCTRL); @@ -1520,10 +1520,10 @@ static int lpuart32_config_rs485(struct uart_port *= port, struct ktermios *termio static unsigned int lpuart_get_mctrl(struct uart_port *port) { unsigned int mctrl =3D 0; - u8 reg; + u8 cr1; =20 - reg =3D readb(port->membase + UARTCR1); - if (reg & UARTCR1_LOOPS) + cr1 =3D readb(port->membase + UARTCR1); + if (cr1 & UARTCR1_LOOPS) mctrl |=3D TIOCM_LOOP; =20 return mctrl; @@ -1532,10 +1532,10 @@ static unsigned int lpuart_get_mctrl(struct uart_po= rt *port) static unsigned int lpuart32_get_mctrl(struct uart_port *port) { unsigned int mctrl =3D TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; - u32 reg; + u32 ctrl; =20 - reg =3D lpuart32_read(port, UARTCTRL); - if (reg & UARTCTRL_LOOPS) + ctrl =3D lpuart32_read(port, UARTCTRL); + if (ctrl & UARTCTRL_LOOPS) mctrl |=3D TIOCM_LOOP; =20 return mctrl; @@ -1543,49 +1543,49 @@ static unsigned int lpuart32_get_mctrl(struct uart_= port *port) =20 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) { - u8 reg; + u8 cr1; =20 - reg =3D readb(port->membase + UARTCR1); + cr1 =3D readb(port->membase + UARTCR1); =20 /* for internal loopback we need LOOPS=3D1 and RSRC=3D0 */ - reg &=3D ~(UARTCR1_LOOPS | UARTCR1_RSRC); + cr1 &=3D ~(UARTCR1_LOOPS | UARTCR1_RSRC); if (mctrl & TIOCM_LOOP) - reg |=3D UARTCR1_LOOPS; + cr1 |=3D UARTCR1_LOOPS; =20 - writeb(reg, port->membase + UARTCR1); + writeb(cr1, port->membase + UARTCR1); } =20 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) { - u32 reg; + u32 ctrl; =20 - reg =3D lpuart32_read(port, UARTCTRL); + ctrl =3D lpuart32_read(port, UARTCTRL); =20 /* for internal loopback we need LOOPS=3D1 and RSRC=3D0 */ - reg &=3D ~(UARTCTRL_LOOPS | UARTCTRL_RSRC); + ctrl &=3D ~(UARTCTRL_LOOPS | UARTCTRL_RSRC); if (mctrl & TIOCM_LOOP) - reg |=3D UARTCTRL_LOOPS; + ctrl |=3D UARTCTRL_LOOPS; =20 - lpuart32_write(port, reg, UARTCTRL); + lpuart32_write(port, ctrl, UARTCTRL); } =20 static void lpuart_break_ctl(struct uart_port *port, int break_state) { - u8 temp; + u8 cr2; =20 - temp =3D readb(port->membase + UARTCR2) & ~UARTCR2_SBK; + cr2 =3D readb(port->membase + UARTCR2) & ~UARTCR2_SBK; =20 if (break_state !=3D 0) - temp |=3D UARTCR2_SBK; + cr2 |=3D UARTCR2_SBK; =20 - writeb(temp, port->membase + UARTCR2); + writeb(cr2, port->membase + UARTCR2); } =20 static void lpuart32_break_ctl(struct uart_port *port, int break_state) { - u32 temp; + u32 ctrl; =20 - temp =3D lpuart32_read(port, UARTCTRL); + ctrl =3D lpuart32_read(port, UARTCTRL); =20 /* * LPUART IP now has two known bugs, one is CTS has higher priority than = the @@ -1602,22 +1602,22 @@ static void lpuart32_break_ctl(struct uart_port *po= rt, int break_state) * Disable the transmitter to prevent any data from being sent out * during break, then invert the TX line to send break. */ - temp &=3D ~UARTCTRL_TE; - lpuart32_write(port, temp, UARTCTRL); - temp |=3D UARTCTRL_TXINV; - lpuart32_write(port, temp, UARTCTRL); + ctrl &=3D ~UARTCTRL_TE; + lpuart32_write(port, ctrl, UARTCTRL); + ctrl |=3D UARTCTRL_TXINV; + lpuart32_write(port, ctrl, UARTCTRL); } else { /* Disable the TXINV to turn off break and re-enable transmitter. */ - temp &=3D ~UARTCTRL_TXINV; - lpuart32_write(port, temp, UARTCTRL); - temp |=3D UARTCTRL_TE; - lpuart32_write(port, temp, UARTCTRL); + ctrl &=3D ~UARTCTRL_TXINV; + lpuart32_write(port, ctrl, UARTCTRL); + ctrl |=3D UARTCTRL_TE; + lpuart32_write(port, ctrl, UARTCTRL); } } =20 static void lpuart_setup_watermark(struct lpuart_port *sport) { - u8 val, cr2, cr2_saved; + u8 fifo, cr2, cr2_saved; =20 cr2 =3D readb(sport->port.membase + UARTCR2); cr2_saved =3D cr2; @@ -1625,8 +1625,8 @@ static void lpuart_setup_watermark(struct lpuart_port= *sport) UARTCR2_RIE | UARTCR2_RE); writeb(cr2, sport->port.membase + UARTCR2); =20 - val =3D readb(sport->port.membase + UARTPFIFO); - writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, + fifo =3D readb(sport->port.membase + UARTPFIFO); + writeb(fifo | UARTPFIFO_TXFE | UARTPFIFO_RXFE, sport->port.membase + UARTPFIFO); =20 /* flush Tx and Rx FIFO */ @@ -1696,14 +1696,14 @@ static void lpuart32_setup_watermark(struct lpuart_= port *sport) =20 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) { - u32 temp; + u32 ctrl; =20 lpuart32_setup_watermark(sport); =20 - temp =3D lpuart32_read(&sport->port, UARTCTRL); - temp |=3D UARTCTRL_RE | UARTCTRL_TE; - temp |=3D FIELD_PREP(UARTCTRL_IDLECFG, 0x7); - lpuart32_write(&sport->port, temp, UARTCTRL); + ctrl =3D lpuart32_read(&sport->port, UARTCTRL); + ctrl |=3D UARTCTRL_RE | UARTCTRL_TE; + ctrl |=3D FIELD_PREP(UARTCTRL_IDLECFG, 0x7); + lpuart32_write(&sport->port, ctrl, UARTCTRL); } =20 static void rx_dma_timer_init(struct lpuart_port *sport) @@ -1820,16 +1820,16 @@ static void lpuart_hw_setup(struct lpuart_port *spo= rt) static int lpuart_startup(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); - u8 temp; + u8 fifo; =20 /* determine FIFO size and enable FIFO mode */ - temp =3D readb(port->membase + UARTPFIFO); + fifo =3D readb(port->membase + UARTPFIFO); =20 - sport->txfifo_size =3D UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & + sport->txfifo_size =3D UARTFIFO_DEPTH((fifo >> UARTPFIFO_TXSIZE_OFF) & UARTPFIFO_FIFOSIZE_MASK); port->fifosize =3D sport->txfifo_size; =20 - sport->rxfifo_size =3D UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & + sport->rxfifo_size =3D UARTFIFO_DEPTH((fifo >> UARTPFIFO_RXSIZE_OFF) & UARTPFIFO_FIFOSIZE_MASK); =20 lpuart_request_dma(sport); @@ -1840,24 +1840,24 @@ static int lpuart_startup(struct uart_port *port) =20 static void lpuart32_hw_disable(struct lpuart_port *sport) { - u32 temp; + u32 ctrl; =20 - temp =3D lpuart32_read(&sport->port, UARTCTRL); - temp &=3D ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE | + ctrl =3D lpuart32_read(&sport->port, UARTCTRL); + ctrl &=3D ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE | UARTCTRL_TIE | UARTCTRL_TE); - lpuart32_write(&sport->port, temp, UARTCTRL); + lpuart32_write(&sport->port, ctrl, UARTCTRL); } =20 static void lpuart32_configure(struct lpuart_port *sport) { - u32 temp; + u32 ctrl; =20 - temp =3D lpuart32_read(&sport->port, UARTCTRL); + ctrl =3D lpuart32_read(&sport->port, UARTCTRL); if (!sport->lpuart_dma_rx_use) - temp |=3D UARTCTRL_RIE | UARTCTRL_ILIE; + ctrl |=3D UARTCTRL_RIE | UARTCTRL_ILIE; if (!sport->lpuart_dma_tx_use) - temp |=3D UARTCTRL_TIE; - lpuart32_write(&sport->port, temp, UARTCTRL); + ctrl |=3D UARTCTRL_TIE; + lpuart32_write(&sport->port, ctrl, UARTCTRL); } =20 static void lpuart32_hw_setup(struct lpuart_port *sport) @@ -1880,16 +1880,16 @@ static void lpuart32_hw_setup(struct lpuart_port *s= port) static int lpuart32_startup(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); - u32 temp; + u32 fifo; =20 /* determine FIFO size */ - temp =3D lpuart32_read(port, UARTFIFO); + fifo =3D lpuart32_read(port, UARTFIFO); =20 - sport->txfifo_size =3D UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & + sport->txfifo_size =3D UARTFIFO_DEPTH((fifo >> UARTFIFO_TXSIZE_OFF) & UARTFIFO_FIFOSIZE_MASK); port->fifosize =3D sport->txfifo_size; =20 - sport->rxfifo_size =3D UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & + sport->rxfifo_size =3D UARTFIFO_DEPTH((fifo >> UARTFIFO_RXSIZE_OFF) & UARTFIFO_FIFOSIZE_MASK); =20 /* @@ -1934,16 +1934,16 @@ static void lpuart_dma_shutdown(struct lpuart_port = *sport) static void lpuart_shutdown(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); - u8 temp; + u8 cr2; unsigned long flags; =20 uart_port_lock_irqsave(port, &flags); =20 /* disable Rx/Tx and interrupts */ - temp =3D readb(port->membase + UARTCR2); - temp &=3D ~(UARTCR2_TE | UARTCR2_RE | + cr2 =3D readb(port->membase + UARTCR2); + cr2 &=3D ~(UARTCR2_TE | UARTCR2_RE | UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); - writeb(temp, port->membase + UARTCR2); + writeb(cr2, port->membase + UARTCR2); =20 uart_port_unlock_irqrestore(port, flags); =20 @@ -2141,7 +2141,7 @@ static void __lpuart32_serial_setbrg(struct uart_port= *port, unsigned int baudrate, bool use_rx_dma, bool use_tx_dma) { - u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; + u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, baud; u32 clk =3D port->uartclk; =20 /* @@ -2170,9 +2170,9 @@ static void __lpuart32_serial_setbrg(struct uart_port= *port, tmp_diff =3D clk / (tmp_osr * tmp_sbr) - baudrate; =20 /* select best values between sbr and sbr+1 */ - tmp =3D clk / (tmp_osr * (tmp_sbr + 1)); - if (tmp_diff > (baudrate - tmp)) { - tmp_diff =3D baudrate - tmp; + baud =3D clk / (tmp_osr * (tmp_sbr + 1)); + if (tmp_diff > (baudrate - baud)) { + tmp_diff =3D baudrate - baud; tmp_sbr++; } =20 @@ -2194,23 +2194,23 @@ static void __lpuart32_serial_setbrg(struct uart_po= rt *port, dev_warn(port->dev, "unacceptable baud rate difference of more than 3%%\n"); =20 - tmp =3D lpuart32_read(port, UARTBAUD); + baud =3D lpuart32_read(port, UARTBAUD); =20 if ((osr > 3) && (osr < 8)) - tmp |=3D UARTBAUD_BOTHEDGE; + baud |=3D UARTBAUD_BOTHEDGE; =20 - tmp &=3D ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); - tmp |=3D ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; + baud &=3D ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); + baud |=3D ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; =20 - tmp &=3D ~UARTBAUD_SBR_MASK; - tmp |=3D sbr & UARTBAUD_SBR_MASK; + baud &=3D ~UARTBAUD_SBR_MASK; + baud |=3D sbr & UARTBAUD_SBR_MASK; =20 if (!use_rx_dma) - tmp &=3D ~UARTBAUD_RDMAE; + baud &=3D ~UARTBAUD_RDMAE; if (!use_tx_dma) - tmp &=3D ~UARTBAUD_TDMAE; + baud &=3D ~UARTBAUD_TDMAE; =20 - lpuart32_write(port, tmp, UARTBAUD); + lpuart32_write(port, baud, UARTBAUD); } =20 static void lpuart32_serial_setbrg(struct lpuart_port *sport, @@ -3085,7 +3085,7 @@ static int lpuart_suspend_noirq(struct device *dev) static int lpuart_resume_noirq(struct device *dev) { struct lpuart_port *sport =3D dev_get_drvdata(dev); - u32 val; + u32 stat; =20 pinctrl_pm_select_default_state(dev); =20 @@ -3094,8 +3094,8 @@ static int lpuart_resume_noirq(struct device *dev) =20 /* clear the wakeup flags */ if (lpuart_is_32(sport)) { - val =3D lpuart32_read(&sport->port, UARTSTAT); - lpuart32_write(&sport->port, val, UARTSTAT); + stat =3D lpuart32_read(&sport->port, UARTSTAT); + lpuart32_write(&sport->port, stat, UARTSTAT); } } =20 --=20 2.34.1