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charset="utf-8" Use u32 and u8 rather than unsigned long or unsigned char for register variables for clarity and consistency. Signed-off-by: Sherry Sun --- drivers/tty/serial/fsl_lpuart.c | 93 ++++++++++++++++----------------- 1 file changed, 46 insertions(+), 47 deletions(-) diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuar= t.c index 203ec3b46304..6f64a3300a38 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -441,7 +441,7 @@ static unsigned int lpuart_get_baud_clk_rate(struct lpu= art_port *sport) =20 static void lpuart_stop_tx(struct uart_port *port) { - unsigned char temp; + u8 temp; =20 temp =3D readb(port->membase + UARTCR2); temp &=3D ~(UARTCR2_TIE | UARTCR2_TCIE); @@ -450,7 +450,7 @@ static void lpuart_stop_tx(struct uart_port *port) =20 static void lpuart32_stop_tx(struct uart_port *port) { - unsigned long temp; + u32 temp; =20 temp =3D lpuart32_read(port, UARTCTRL); temp &=3D ~(UARTCTRL_TIE | UARTCTRL_TCIE); @@ -459,7 +459,7 @@ static void lpuart32_stop_tx(struct uart_port *port) =20 static void lpuart_stop_rx(struct uart_port *port) { - unsigned char temp; + u8 temp; =20 temp =3D readb(port->membase + UARTCR2); writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); @@ -467,7 +467,7 @@ static void lpuart_stop_rx(struct uart_port *port) =20 static void lpuart32_stop_rx(struct uart_port *port) { - unsigned long temp; + u32 temp; =20 temp =3D lpuart32_read(port, UARTCTRL); lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); @@ -642,7 +642,7 @@ static int lpuart_poll_init(struct uart_port *port) struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port); unsigned long flags; - unsigned char temp; + u8 temp; =20 sport->port.fifosize =3D 0; =20 @@ -752,7 +752,7 @@ static inline void lpuart_transmit_buffer(struct lpuart= _port *sport) static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) { struct tty_port *tport =3D &sport->port.state->port; - unsigned long txcnt; + u32 txcnt; unsigned char c; =20 if (sport->port.x_char) { @@ -789,7 +789,7 @@ static void lpuart_start_tx(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port); - unsigned char temp; + u8 temp; =20 temp =3D readb(port->membase + UARTCR2); writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); @@ -806,7 +806,7 @@ static void lpuart_start_tx(struct uart_port *port) static void lpuart32_start_tx(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); - unsigned long temp; + u32 temp; =20 if (sport->lpuart_dma_tx_use) { if (!lpuart_stopped_or_empty(port)) @@ -839,8 +839,8 @@ static unsigned int lpuart_tx_empty(struct uart_port *p= ort) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port); - unsigned char sr1 =3D readb(port->membase + UARTSR1); - unsigned char sfifo =3D readb(port->membase + UARTSFIFO); + u8 sr1 =3D readb(port->membase + UARTSR1); + u8 sfifo =3D readb(port->membase + UARTSFIFO); =20 if (sport->dma_tx_in_progress) return 0; @@ -855,9 +855,9 @@ static unsigned int lpuart32_tx_empty(struct uart_port = *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port); - unsigned long stat =3D lpuart32_read(port, UARTSTAT); - unsigned long sfifo =3D lpuart32_read(port, UARTFIFO); - unsigned long ctrl =3D lpuart32_read(port, UARTCTRL); + u32 stat =3D lpuart32_read(port, UARTSTAT); + u32 sfifo =3D lpuart32_read(port, UARTFIFO); + u32 ctrl =3D lpuart32_read(port, UARTCTRL); =20 if (sport->dma_tx_in_progress) return 0; @@ -884,7 +884,7 @@ static void lpuart_rxint(struct lpuart_port *sport) { unsigned int flg, ignored =3D 0, overrun =3D 0; struct tty_port *port =3D &sport->port.state->port; - unsigned char rx, sr; + u8 rx, sr; =20 uart_port_lock(&sport->port); =20 @@ -961,7 +961,7 @@ static void lpuart32_rxint(struct lpuart_port *sport) { unsigned int flg, ignored =3D 0; struct tty_port *port =3D &sport->port.state->port; - unsigned long rx, sr; + u32 rx, sr; bool is_break; =20 uart_port_lock(&sport->port); @@ -1039,7 +1039,7 @@ static void lpuart32_rxint(struct lpuart_port *sport) static irqreturn_t lpuart_int(int irq, void *dev_id) { struct lpuart_port *sport =3D dev_id; - unsigned char sts; + u8 sts; =20 sts =3D readb(sport->port.membase + UARTSR1); =20 @@ -1113,7 +1113,7 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port = *sport) int count, copied; =20 if (lpuart_is_32(sport)) { - unsigned long sr =3D lpuart32_read(&sport->port, UARTSTAT); + u32 sr =3D lpuart32_read(&sport->port, UARTSTAT); =20 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { /* Clear the error flags */ @@ -1125,10 +1125,10 @@ static void lpuart_copy_rx_to_tty(struct lpuart_por= t *sport) sport->port.icount.frame++; } } else { - unsigned char sr =3D readb(sport->port.membase + UARTSR1); + u8 sr =3D readb(sport->port.membase + UARTSR1); =20 if (sr & (UARTSR1_PE | UARTSR1_FE)) { - unsigned char cr2; + u8 cr2; =20 /* Disable receiver during this operation... */ cr2 =3D readb(sport->port.membase + UARTCR2); @@ -1279,7 +1279,7 @@ static void lpuart32_dma_idleint(struct lpuart_port *= sport) static irqreturn_t lpuart32_int(int irq, void *dev_id) { struct lpuart_port *sport =3D dev_id; - unsigned long sts, rxcount; + u32 sts, rxcount; =20 sts =3D lpuart32_read(&sport->port, UARTSTAT); rxcount =3D lpuart32_read(&sport->port, UARTWATER); @@ -1411,12 +1411,12 @@ static inline int lpuart_start_rx_dma(struct lpuart= _port *sport) dma_async_issue_pending(chan); =20 if (lpuart_is_32(sport)) { - unsigned long temp =3D lpuart32_read(&sport->port, UARTBAUD); + u32 temp =3D lpuart32_read(&sport->port, UARTBAUD); =20 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); =20 if (sport->dma_idle_int) { - unsigned long ctrl =3D lpuart32_read(&sport->port, UARTCTRL); + u32 ctrl =3D lpuart32_read(&sport->port, UARTCTRL); =20 lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL); } @@ -1482,7 +1482,7 @@ static int lpuart32_config_rs485(struct uart_port *po= rt, struct ktermios *termio struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port); =20 - unsigned long modem =3D lpuart32_read(&sport->port, UARTMODIR) + u32 modem =3D lpuart32_read(&sport->port, UARTMODIR) & ~(UARTMODIR_TXRTSPOL | UARTMODIR_TXRTSE); u32 ctrl; =20 @@ -1577,7 +1577,7 @@ static void lpuart32_set_mctrl(struct uart_port *port= , unsigned int mctrl) =20 static void lpuart_break_ctl(struct uart_port *port, int break_state) { - unsigned char temp; + u8 temp; =20 temp =3D readb(port->membase + UARTCR2) & ~UARTCR2_SBK; =20 @@ -1589,7 +1589,7 @@ static void lpuart_break_ctl(struct uart_port *port, = int break_state) =20 static void lpuart32_break_ctl(struct uart_port *port, int break_state) { - unsigned long temp; + u32 temp; =20 temp =3D lpuart32_read(port, UARTCTRL); =20 @@ -1623,8 +1623,7 @@ static void lpuart32_break_ctl(struct uart_port *port= , int break_state) =20 static void lpuart_setup_watermark(struct lpuart_port *sport) { - unsigned char val, cr2; - unsigned char cr2_saved; + u8 val, cr2, cr2_saved; =20 cr2 =3D readb(sport->port.membase + UARTCR2); cr2_saved =3D cr2; @@ -1657,7 +1656,7 @@ static void lpuart_setup_watermark(struct lpuart_port= *sport) =20 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) { - unsigned char cr2; + u8 cr2; =20 lpuart_setup_watermark(sport); =20 @@ -1668,8 +1667,7 @@ static void lpuart_setup_watermark_enable(struct lpua= rt_port *sport) =20 static void lpuart32_setup_watermark(struct lpuart_port *sport) { - unsigned long val, ctrl; - unsigned long ctrl_saved; + u32 val, ctrl, ctrl_saved; =20 ctrl =3D lpuart32_read(&sport->port, UARTCTRL); ctrl_saved =3D ctrl; @@ -1778,7 +1776,7 @@ static void lpuart_tx_dma_startup(struct lpuart_port = *sport) static void lpuart_rx_dma_startup(struct lpuart_port *sport) { int ret; - unsigned char cr3; + u8 cr3; =20 if (uart_console(&sport->port)) goto err; @@ -1828,7 +1826,7 @@ static void lpuart_hw_setup(struct lpuart_port *sport) static int lpuart_startup(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); - unsigned char temp; + u8 temp; =20 /* determine FIFO size and enable FIFO mode */ temp =3D readb(sport->port.membase + UARTPFIFO); @@ -1848,7 +1846,7 @@ static int lpuart_startup(struct uart_port *port) =20 static void lpuart32_hw_disable(struct lpuart_port *sport) { - unsigned long temp; + u32 temp; =20 temp =3D lpuart32_read(&sport->port, UARTCTRL); temp &=3D ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE | @@ -1858,7 +1856,7 @@ static void lpuart32_hw_disable(struct lpuart_port *s= port) =20 static void lpuart32_configure(struct lpuart_port *sport) { - unsigned long temp; + u32 temp; =20 temp =3D lpuart32_read(&sport->port, UARTCTRL); if (!sport->lpuart_dma_rx_use) @@ -1888,7 +1886,7 @@ static void lpuart32_hw_setup(struct lpuart_port *spo= rt) static int lpuart32_startup(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); - unsigned long temp; + u32 temp; =20 /* determine FIFO size */ temp =3D lpuart32_read(&sport->port, UARTFIFO); @@ -1942,7 +1940,7 @@ static void lpuart_dma_shutdown(struct lpuart_port *s= port) static void lpuart_shutdown(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); - unsigned char temp; + u8 temp; unsigned long flags; =20 uart_port_lock_irqsave(port, &flags); @@ -1962,7 +1960,7 @@ static void lpuart32_shutdown(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port); - unsigned long temp; + u32 temp; unsigned long flags; =20 uart_port_lock_irqsave(port, &flags); @@ -1998,7 +1996,7 @@ lpuart_set_termios(struct uart_port *port, struct kte= rmios *termios, { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); unsigned long flags; - unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; + u8 cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; unsigned int baud; unsigned int old_csize =3D old ? old->c_cflag & CSIZE : CS8; unsigned int sbr, brfa; @@ -2236,7 +2234,7 @@ lpuart32_set_termios(struct uart_port *port, struct k= termios *termios, { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); unsigned long flags; - unsigned long ctrl, old_ctrl, bd, modem; + u32 ctrl, old_ctrl, bd, modem; unsigned int baud; unsigned int old_csize =3D old ? old->c_cflag & CSIZE : CS8; =20 @@ -2503,7 +2501,7 @@ static void lpuart_console_write(struct console *co, const char *s, unsigned int count) { struct lpuart_port *sport =3D lpuart_ports[co->index]; - unsigned char old_cr2, cr2; + u8 old_cr2, cr2; unsigned long flags; int locked =3D 1; =20 @@ -2533,7 +2531,7 @@ static void lpuart32_console_write(struct console *co, const char *s, unsigned int cou= nt) { struct lpuart_port *sport =3D lpuart_ports[co->index]; - unsigned long old_cr, cr; + u32 old_cr, cr; unsigned long flags; int locked =3D 1; =20 @@ -2567,7 +2565,7 @@ static void __init lpuart_console_get_options(struct lpuart_port *sport, int *baud, int *parity, int *bits) { - unsigned char cr, bdh, bdl, brfa; + u8 cr, bdh, bdl, brfa; unsigned int sbr, uartclk, baud_raw; =20 cr =3D readb(sport->port.membase + UARTCR2); @@ -2616,7 +2614,7 @@ static void __init lpuart32_console_get_options(struct lpuart_port *sport, int *baud, int *parity, int *bits) { - unsigned long cr, bd; + u32 cr, bd; unsigned int sbr, uartclk, baud_raw; =20 cr =3D lpuart32_read(&sport->port, UARTCTRL); @@ -2822,7 +2820,7 @@ static int lpuart_global_reset(struct lpuart_port *sp= ort) { struct uart_port *port =3D &sport->port; void __iomem *global_addr; - unsigned long ctrl, bd; + u32 ctrl, bd; unsigned int val =3D 0; int ret; =20 @@ -3028,7 +3026,7 @@ static int lpuart_runtime_resume(struct device *dev) =20 static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on) { - unsigned int val, baud; + u32 val, baud; =20 if (lpuart_is_32(sport)) { val =3D lpuart32_read(&sport->port, UARTCTRL); @@ -3093,7 +3091,7 @@ static int lpuart_suspend_noirq(struct device *dev) static int lpuart_resume_noirq(struct device *dev) { struct lpuart_port *sport =3D dev_get_drvdata(dev); - unsigned int val; + u32 val; =20 pinctrl_pm_select_default_state(dev); =20 @@ -3113,7 +3111,8 @@ static int lpuart_resume_noirq(struct device *dev) static int lpuart_suspend(struct device *dev) { struct lpuart_port *sport =3D dev_get_drvdata(dev); - unsigned long temp, flags; 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charset="utf-8" Most lpuart functions have the parameter struct uart_port *port, but still use the &sport->port to get the uart_port instead of use it directly, let's simply the code logic, directly use this struct instead of covert it from struct sport. Signed-off-by: Sherry Sun --- drivers/tty/serial/fsl_lpuart.c | 210 ++++++++++++++++---------------- 1 file changed, 102 insertions(+), 108 deletions(-) diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuar= t.c index 6f64a3300a38..3b48e320e7f4 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -581,7 +581,7 @@ static int lpuart_dma_tx_request(struct uart_port *port) ret =3D dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); =20 if (ret) { - dev_err(sport->port.dev, + dev_err(port->dev, "DMA slave config failed, err =3D %d\n", ret); return ret; } @@ -611,13 +611,13 @@ static void lpuart_flush_buffer(struct uart_port *por= t) } =20 if (lpuart_is_32(sport)) { - val =3D lpuart32_read(&sport->port, UARTFIFO); + val =3D lpuart32_read(port, UARTFIFO); val |=3D UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; - lpuart32_write(&sport->port, val, UARTFIFO); + lpuart32_write(port, val, UARTFIFO); } else { - val =3D readb(sport->port.membase + UARTCFIFO); + val =3D readb(port->membase + UARTCFIFO); val |=3D UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; - writeb(val, sport->port.membase + UARTCFIFO); + writeb(val, port->membase + UARTCFIFO); } } =20 @@ -644,33 +644,33 @@ static int lpuart_poll_init(struct uart_port *port) unsigned long flags; u8 temp; =20 - sport->port.fifosize =3D 0; + port->fifosize =3D 0; =20 - uart_port_lock_irqsave(&sport->port, &flags); + uart_port_lock_irqsave(port, &flags); /* Disable Rx & Tx */ - writeb(0, sport->port.membase + UARTCR2); + writeb(0, port->membase + UARTCR2); =20 - temp =3D readb(sport->port.membase + UARTPFIFO); + temp =3D readb(port->membase + UARTPFIFO); /* Enable Rx and Tx FIFO */ writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, - sport->port.membase + UARTPFIFO); + port->membase + UARTPFIFO); =20 /* flush Tx and Rx FIFO */ writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, - sport->port.membase + UARTCFIFO); + port->membase + UARTCFIFO); =20 /* explicitly clear RDRF */ - if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { - readb(sport->port.membase + UARTDR); - writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); + if (readb(port->membase + UARTSR1) & UARTSR1_RDRF) { + readb(port->membase + UARTDR); + writeb(UARTSFIFO_RXUF, port->membase + UARTSFIFO); } =20 - writeb(0, sport->port.membase + UARTTWFIFO); - writeb(1, sport->port.membase + UARTRWFIFO); + writeb(0, port->membase + UARTTWFIFO); + writeb(1, port->membase + UARTRWFIFO); =20 /* Enable Rx and Tx */ - writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); - uart_port_unlock_irqrestore(&sport->port, flags); + writeb(UARTCR2_RE | UARTCR2_TE, port->membase + UARTCR2); + uart_port_unlock_irqrestore(port, flags); =20 return 0; } @@ -696,30 +696,30 @@ static int lpuart32_poll_init(struct uart_port *port) struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); u32 temp; =20 - sport->port.fifosize =3D 0; + port->fifosize =3D 0; =20 - uart_port_lock_irqsave(&sport->port, &flags); + uart_port_lock_irqsave(port, &flags); =20 /* Disable Rx & Tx */ - lpuart32_write(&sport->port, 0, UARTCTRL); + lpuart32_write(port, 0, UARTCTRL); =20 - temp =3D lpuart32_read(&sport->port, UARTFIFO); + temp =3D lpuart32_read(port, UARTFIFO); =20 /* Enable Rx and Tx FIFO */ - lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFI= FO); + lpuart32_write(port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); =20 /* flush Tx and Rx FIFO */ - lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIF= O); + lpuart32_write(port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); =20 /* explicitly clear RDRF */ - if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { - lpuart32_read(&sport->port, UARTDATA); - lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); + if (lpuart32_read(port, UARTSTAT) & UARTSTAT_RDRF) { + lpuart32_read(port, UARTDATA); + lpuart32_write(port, UARTFIFO_RXUF, UARTFIFO); } =20 /* Enable Rx and Tx */ - lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); - uart_port_unlock_irqrestore(&sport->port, flags); + lpuart32_write(port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); + uart_port_unlock_irqrestore(port, flags); =20 return 0; } @@ -1449,12 +1449,9 @@ static void lpuart_dma_rx_free(struct uart_port *por= t) static int lpuart_config_rs485(struct uart_port *port, struct ktermios *te= rmios, struct serial_rs485 *rs485) { - struct lpuart_port *sport =3D container_of(port, - struct lpuart_port, port); - - u8 modem =3D readb(sport->port.membase + UARTMODEM) & + u8 modem =3D readb(port->membase + UARTMODEM) & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); - writeb(modem, sport->port.membase + UARTMODEM); + writeb(modem, port->membase + UARTMODEM); =20 if (rs485->flags & SER_RS485_ENABLED) { /* Enable auto RS-485 RTS mode */ @@ -1472,32 +1469,29 @@ static int lpuart_config_rs485(struct uart_port *po= rt, struct ktermios *termios, modem &=3D ~UARTMODEM_TXRTSPOL; } =20 - writeb(modem, sport->port.membase + UARTMODEM); + writeb(modem, port->membase + UARTMODEM); return 0; } =20 static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *= termios, struct serial_rs485 *rs485) { - struct lpuart_port *sport =3D container_of(port, - struct lpuart_port, port); - - u32 modem =3D lpuart32_read(&sport->port, UARTMODIR) + u32 modem =3D lpuart32_read(port, UARTMODIR) & ~(UARTMODIR_TXRTSPOL | UARTMODIR_TXRTSE); u32 ctrl; =20 /* TXRTSE and TXRTSPOL only can be changed when transmitter is disabled. = */ - ctrl =3D lpuart32_read(&sport->port, UARTCTRL); + ctrl =3D lpuart32_read(port, UARTCTRL); if (ctrl & UARTCTRL_TE) { /* wait for the transmit engine to complete */ - lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); - lpuart32_write(&sport->port, ctrl & ~UARTCTRL_TE, UARTCTRL); + lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TC); + lpuart32_write(port, ctrl & ~UARTCTRL_TE, UARTCTRL); =20 - while (lpuart32_read(&sport->port, UARTCTRL) & UARTCTRL_TE) + while (lpuart32_read(port, UARTCTRL) & UARTCTRL_TE) cpu_relax(); } =20 - lpuart32_write(&sport->port, modem, UARTMODIR); + lpuart32_write(port, modem, UARTMODIR); =20 if (rs485->flags & SER_RS485_ENABLED) { /* Enable auto RS-485 RTS mode */ @@ -1515,10 +1509,10 @@ static int lpuart32_config_rs485(struct uart_port *= port, struct ktermios *termio modem &=3D ~UARTMODIR_TXRTSPOL; } =20 - lpuart32_write(&sport->port, modem, UARTMODIR); + lpuart32_write(port, modem, UARTMODIR); =20 if (ctrl & UARTCTRL_TE) - lpuart32_write(&sport->port, ctrl, UARTCTRL); + lpuart32_write(port, ctrl, UARTCTRL); =20 return 0; } @@ -1829,11 +1823,11 @@ static int lpuart_startup(struct uart_port *port) u8 temp; =20 /* determine FIFO size and enable FIFO mode */ - temp =3D readb(sport->port.membase + UARTPFIFO); + temp =3D readb(port->membase + UARTPFIFO); =20 sport->txfifo_size =3D UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & UARTPFIFO_FIFOSIZE_MASK); - sport->port.fifosize =3D sport->txfifo_size; + port->fifosize =3D sport->txfifo_size; =20 sport->rxfifo_size =3D UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & UARTPFIFO_FIFOSIZE_MASK); @@ -1889,11 +1883,11 @@ static int lpuart32_startup(struct uart_port *port) u32 temp; =20 /* determine FIFO size */ - temp =3D lpuart32_read(&sport->port, UARTFIFO); + temp =3D lpuart32_read(port, UARTFIFO); =20 sport->txfifo_size =3D UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & UARTFIFO_FIFOSIZE_MASK); - sport->port.fifosize =3D sport->txfifo_size; + port->fifosize =3D sport->txfifo_size; =20 sport->rxfifo_size =3D UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & UARTFIFO_FIFOSIZE_MASK); @@ -1906,7 +1900,7 @@ static int lpuart32_startup(struct uart_port *port) if (is_layerscape_lpuart(sport)) { sport->rxfifo_size =3D 16; sport->txfifo_size =3D 16; - sport->port.fifosize =3D sport->txfifo_size; + port->fifosize =3D sport->txfifo_size; } =20 lpuart_request_dma(sport); @@ -1966,8 +1960,8 @@ static void lpuart32_shutdown(struct uart_port *port) uart_port_lock_irqsave(port, &flags); =20 /* clear status */ - temp =3D lpuart32_read(&sport->port, UARTSTAT); - lpuart32_write(&sport->port, temp, UARTSTAT); + temp =3D lpuart32_read(port, UARTSTAT); + lpuart32_write(port, temp, UARTSTAT); =20 /* disable Rx/Tx DMA */ temp =3D lpuart32_read(port, UARTBAUD); @@ -2001,12 +1995,12 @@ lpuart_set_termios(struct uart_port *port, struct k= termios *termios, unsigned int old_csize =3D old ? old->c_cflag & CSIZE : CS8; unsigned int sbr, brfa; =20 - cr1 =3D old_cr1 =3D readb(sport->port.membase + UARTCR1); - old_cr2 =3D readb(sport->port.membase + UARTCR2); - cr3 =3D readb(sport->port.membase + UARTCR3); - cr4 =3D readb(sport->port.membase + UARTCR4); - bdh =3D readb(sport->port.membase + UARTBDH); - modem =3D readb(sport->port.membase + UARTMODEM); + cr1 =3D old_cr1 =3D readb(port->membase + UARTCR1); + old_cr2 =3D readb(port->membase + UARTCR2); + cr3 =3D readb(port->membase + UARTCR3); + cr4 =3D readb(port->membase + UARTCR4); + bdh =3D readb(port->membase + UARTBDH); + modem =3D readb(port->membase + UARTMODEM); /* * only support CS8 and CS7, and for CS7 must enable PE. * supported mode: @@ -2038,7 +2032,7 @@ lpuart_set_termios(struct uart_port *port, struct kte= rmios *termios, * When auto RS-485 RTS mode is enabled, * hardware flow control need to be disabled. */ - if (sport->port.rs485.flags & SER_RS485_ENABLED) + if (port->rs485.flags & SER_RS485_ENABLED) termios->c_cflag &=3D ~CRTSCTS; =20 if (termios->c_cflag & CRTSCTS) @@ -2079,59 +2073,59 @@ lpuart_set_termios(struct uart_port *port, struct k= termios *termios, * Need to update the Ring buffer length according to the selected * baud rate and restart Rx DMA path. * - * Since timer function acqures sport->port.lock, need to stop before + * Since timer function acqures port->lock, need to stop before * acquring same lock because otherwise del_timer_sync() can deadlock. */ if (old && sport->lpuart_dma_rx_use) - lpuart_dma_rx_free(&sport->port); + lpuart_dma_rx_free(port); =20 - uart_port_lock_irqsave(&sport->port, &flags); + uart_port_lock_irqsave(port, &flags); =20 - sport->port.read_status_mask =3D 0; + port->read_status_mask =3D 0; if (termios->c_iflag & INPCK) - sport->port.read_status_mask |=3D UARTSR1_FE | UARTSR1_PE; + port->read_status_mask |=3D UARTSR1_FE | UARTSR1_PE; if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) - sport->port.read_status_mask |=3D UARTSR1_FE; + port->read_status_mask |=3D UARTSR1_FE; =20 /* characters to ignore */ - sport->port.ignore_status_mask =3D 0; + port->ignore_status_mask =3D 0; if (termios->c_iflag & IGNPAR) - sport->port.ignore_status_mask |=3D UARTSR1_PE; + port->ignore_status_mask |=3D UARTSR1_PE; if (termios->c_iflag & IGNBRK) { - sport->port.ignore_status_mask |=3D UARTSR1_FE; + port->ignore_status_mask |=3D UARTSR1_FE; /* * if we're ignoring parity and break indicators, * ignore overruns too (for real raw support). */ if (termios->c_iflag & IGNPAR) - sport->port.ignore_status_mask |=3D UARTSR1_OR; + port->ignore_status_mask |=3D UARTSR1_OR; } =20 /* update the per-port timeout */ uart_update_timeout(port, termios->c_cflag, baud); =20 /* wait transmit engin complete */ - lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); + lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TC); =20 /* disable transmit and receive */ writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), - sport->port.membase + UARTCR2); + port->membase + UARTCR2); =20 - sbr =3D sport->port.uartclk / (16 * baud); - brfa =3D ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; + sbr =3D port->uartclk / (16 * baud); + brfa =3D ((port->uartclk - (16 * sbr * baud)) * 2) / baud; bdh &=3D ~UARTBDH_SBR_MASK; bdh |=3D (sbr >> 8) & 0x1F; cr4 &=3D ~UARTCR4_BRFA_MASK; brfa &=3D UARTCR4_BRFA_MASK; - writeb(cr4 | brfa, sport->port.membase + UARTCR4); - writeb(bdh, sport->port.membase + UARTBDH); - writeb(sbr & 0xFF, sport->port.membase + UARTBDL); - writeb(cr3, sport->port.membase + UARTCR3); - writeb(cr1, sport->port.membase + UARTCR1); - writeb(modem, sport->port.membase + UARTMODEM); + writeb(cr4 | brfa, port->membase + UARTCR4); + writeb(bdh, port->membase + UARTBDH); + writeb(sbr & 0xFF, port->membase + UARTBDL); + writeb(cr3, port->membase + UARTCR3); + writeb(cr1, port->membase + UARTCR1); + writeb(modem, port->membase + UARTMODEM); =20 /* restore control register */ - writeb(old_cr2, sport->port.membase + UARTCR2); + writeb(old_cr2, port->membase + UARTCR2); =20 if (old && sport->lpuart_dma_rx_use) { if (!lpuart_start_rx_dma(sport)) @@ -2140,7 +2134,7 @@ lpuart_set_termios(struct uart_port *port, struct kte= rmios *termios, sport->lpuart_dma_rx_use =3D false; } =20 - uart_port_unlock_irqrestore(&sport->port, flags); + uart_port_unlock_irqrestore(port, flags); } =20 static void __lpuart32_serial_setbrg(struct uart_port *port, @@ -2238,9 +2232,9 @@ lpuart32_set_termios(struct uart_port *port, struct k= termios *termios, unsigned int baud; unsigned int old_csize =3D old ? old->c_cflag & CSIZE : CS8; =20 - ctrl =3D old_ctrl =3D lpuart32_read(&sport->port, UARTCTRL); - bd =3D lpuart32_read(&sport->port, UARTBAUD); - modem =3D lpuart32_read(&sport->port, UARTMODIR); + ctrl =3D old_ctrl =3D lpuart32_read(port, UARTCTRL); + bd =3D lpuart32_read(port, UARTBAUD); + modem =3D lpuart32_read(port, UARTMODIR); sport->is_cs7 =3D false; /* * only support CS8 and CS7 @@ -2274,7 +2268,7 @@ lpuart32_set_termios(struct uart_port *port, struct k= termios *termios, * When auto RS-485 RTS mode is enabled, * hardware flow control need to be disabled. */ - if (sport->port.rs485.flags & SER_RS485_ENABLED) + if (port->rs485.flags & SER_RS485_ENABLED) termios->c_cflag &=3D ~CRTSCTS; =20 if (termios->c_cflag & CRTSCTS) @@ -2324,32 +2318,32 @@ lpuart32_set_termios(struct uart_port *port, struct= ktermios *termios, * Need to update the Ring buffer length according to the selected * baud rate and restart Rx DMA path. * - * Since timer function acqures sport->port.lock, need to stop before + * Since timer function acqures port->lock, need to stop before * acquring same lock because otherwise del_timer_sync() can deadlock. */ if (old && sport->lpuart_dma_rx_use) - lpuart_dma_rx_free(&sport->port); + lpuart_dma_rx_free(port); =20 - uart_port_lock_irqsave(&sport->port, &flags); + uart_port_lock_irqsave(port, &flags); =20 - sport->port.read_status_mask =3D 0; + port->read_status_mask =3D 0; if (termios->c_iflag & INPCK) - sport->port.read_status_mask |=3D UARTSTAT_FE | UARTSTAT_PE; + port->read_status_mask |=3D UARTSTAT_FE | UARTSTAT_PE; if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) - sport->port.read_status_mask |=3D UARTSTAT_FE; + port->read_status_mask |=3D UARTSTAT_FE; =20 /* characters to ignore */ - sport->port.ignore_status_mask =3D 0; + port->ignore_status_mask =3D 0; if (termios->c_iflag & IGNPAR) - sport->port.ignore_status_mask |=3D UARTSTAT_PE; + port->ignore_status_mask |=3D UARTSTAT_PE; if (termios->c_iflag & IGNBRK) { - sport->port.ignore_status_mask |=3D UARTSTAT_FE; + port->ignore_status_mask |=3D UARTSTAT_FE; /* * if we're ignoring parity and break indicators, * ignore overruns too (for real raw support). */ if (termios->c_iflag & IGNPAR) - sport->port.ignore_status_mask |=3D UARTSTAT_OR; + port->ignore_status_mask |=3D UARTSTAT_OR; } =20 /* update the per-port timeout */ @@ -2361,22 +2355,22 @@ lpuart32_set_termios(struct uart_port *port, struct= ktermios *termios, * asserted. */ if (!(old_ctrl & UARTCTRL_SBK)) { - lpuart32_write(&sport->port, 0, UARTMODIR); - lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); + lpuart32_write(port, 0, UARTMODIR); + lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TC); } =20 /* disable transmit and receive */ - lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), + lpuart32_write(port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), UARTCTRL); =20 - lpuart32_write(&sport->port, bd, UARTBAUD); + lpuart32_write(port, bd, UARTBAUD); lpuart32_serial_setbrg(sport, baud); /* disable CTS before enabling UARTCTRL_TE to avoid pending idle preamble= */ - lpuart32_write(&sport->port, modem & ~UARTMODIR_TXCTSE, UARTMODIR); + lpuart32_write(port, modem & ~UARTMODIR_TXCTSE, UARTMODIR); /* restore control register */ - lpuart32_write(&sport->port, ctrl, UARTCTRL); + lpuart32_write(port, ctrl, UARTCTRL); /* re-enable the CTS if needed */ - lpuart32_write(&sport->port, modem, UARTMODIR); + lpuart32_write(port, modem, UARTMODIR); =20 if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) =3D=3D UARTCTRL_PE) sport->is_cs7 =3D true; @@ -2388,7 +2382,7 @@ lpuart32_set_termios(struct uart_port *port, struct k= termios *termios, sport->lpuart_dma_rx_use =3D false; } =20 - uart_port_unlock_irqrestore(&sport->port, flags); + uart_port_unlock_irqrestore(port, flags); } =20 static const char *lpuart_type(struct uart_port *port) @@ -2826,7 +2820,7 @@ static int lpuart_global_reset(struct lpuart_port *sp= ort) =20 ret =3D clk_prepare_enable(sport->ipg_clk); if (ret) { - dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret); + dev_err(port->dev, "failed to enable uart ipg clk: %d\n", ret); return ret; } =20 @@ -2837,10 +2831,10 @@ static int lpuart_global_reset(struct lpuart_port *= sport) */ ctrl =3D lpuart32_read(port, UARTCTRL); if (ctrl & UARTCTRL_TE) { - bd =3D lpuart32_read(&sport->port, UARTBAUD); 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charset="utf-8" There are many fuzzy register variables in the lpuart driver, such as temp, tmp, val, reg. Let's give these register variables more specific names. Signed-off-by: Sherry Sun --- drivers/tty/serial/fsl_lpuart.c | 220 ++++++++++++++++---------------- 1 file changed, 110 insertions(+), 110 deletions(-) diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuar= t.c index 3b48e320e7f4..c8cc0a241fba 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -441,36 +441,36 @@ static unsigned int lpuart_get_baud_clk_rate(struct l= puart_port *sport) =20 static void lpuart_stop_tx(struct uart_port *port) { - u8 temp; + u8 cr2; =20 - temp =3D readb(port->membase + UARTCR2); - temp &=3D ~(UARTCR2_TIE | UARTCR2_TCIE); - writeb(temp, port->membase + UARTCR2); + cr2 =3D readb(port->membase + UARTCR2); + cr2 &=3D ~(UARTCR2_TIE | UARTCR2_TCIE); + writeb(cr2, port->membase + UARTCR2); } =20 static void lpuart32_stop_tx(struct uart_port *port) { - u32 temp; + u32 ctrl; =20 - temp =3D lpuart32_read(port, UARTCTRL); - temp &=3D ~(UARTCTRL_TIE | UARTCTRL_TCIE); - lpuart32_write(port, temp, UARTCTRL); + ctrl =3D lpuart32_read(port, UARTCTRL); + ctrl &=3D ~(UARTCTRL_TIE | UARTCTRL_TCIE); + lpuart32_write(port, ctrl, UARTCTRL); } =20 static void lpuart_stop_rx(struct uart_port *port) { - u8 temp; + u8 cr2; =20 - temp =3D readb(port->membase + UARTCR2); - writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); + cr2 =3D readb(port->membase + UARTCR2); + writeb(cr2 & ~UARTCR2_RE, port->membase + UARTCR2); } =20 static void lpuart32_stop_rx(struct uart_port *port) { - u32 temp; + u32 ctrl; =20 - temp =3D lpuart32_read(port, UARTCTRL); - lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); + ctrl =3D lpuart32_read(port, UARTCTRL); + lpuart32_write(port, ctrl & ~UARTCTRL_RE, UARTCTRL); } =20 static void lpuart_dma_tx(struct lpuart_port *sport) @@ -599,7 +599,7 @@ static void lpuart_flush_buffer(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); struct dma_chan *chan =3D sport->dma_tx_chan; - u32 val; + u32 fifo; =20 if (sport->lpuart_dma_tx_use) { if (sport->dma_tx_in_progress) { @@ -611,13 +611,13 @@ static void lpuart_flush_buffer(struct uart_port *por= t) } =20 if (lpuart_is_32(sport)) { - val =3D lpuart32_read(port, UARTFIFO); - val |=3D UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; - lpuart32_write(port, val, UARTFIFO); + fifo =3D lpuart32_read(port, UARTFIFO); + fifo |=3D UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; + lpuart32_write(port, fifo, UARTFIFO); } else { - val =3D readb(port->membase + UARTCFIFO); - val |=3D UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; - writeb(val, port->membase + UARTCFIFO); + fifo =3D readb(port->membase + UARTCFIFO); + fifo |=3D UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; + writeb(fifo, port->membase + UARTCFIFO); } } =20 @@ -642,7 +642,7 @@ static int lpuart_poll_init(struct uart_port *port) struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port); unsigned long flags; - u8 temp; + u8 fifo; =20 port->fifosize =3D 0; =20 @@ -650,9 +650,9 @@ static int lpuart_poll_init(struct uart_port *port) /* Disable Rx & Tx */ writeb(0, port->membase + UARTCR2); =20 - temp =3D readb(port->membase + UARTPFIFO); + fifo =3D readb(port->membase + UARTPFIFO); /* Enable Rx and Tx FIFO */ - writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, + writeb(fifo | UARTPFIFO_RXFE | UARTPFIFO_TXFE, port->membase + UARTPFIFO); =20 /* flush Tx and Rx FIFO */ @@ -694,7 +694,7 @@ static int lpuart32_poll_init(struct uart_port *port) { unsigned long flags; struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); - u32 temp; + u32 fifo; =20 port->fifosize =3D 0; =20 @@ -703,10 +703,10 @@ static int lpuart32_poll_init(struct uart_port *port) /* Disable Rx & Tx */ lpuart32_write(port, 0, UARTCTRL); =20 - temp =3D lpuart32_read(port, UARTFIFO); + fifo =3D lpuart32_read(port, UARTFIFO); =20 /* Enable Rx and Tx FIFO */ - lpuart32_write(port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); + lpuart32_write(port, fifo | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); =20 /* flush Tx and Rx FIFO */ lpuart32_write(port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); @@ -789,10 +789,10 @@ static void lpuart_start_tx(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port); - u8 temp; + u8 cr2; =20 - temp =3D readb(port->membase + UARTCR2); - writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); + cr2 =3D readb(port->membase + UARTCR2); + writeb(cr2 | UARTCR2_TIE, port->membase + UARTCR2); =20 if (sport->lpuart_dma_tx_use) { if (!lpuart_stopped_or_empty(port)) @@ -806,14 +806,14 @@ static void lpuart_start_tx(struct uart_port *port) static void lpuart32_start_tx(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); - u32 temp; + u32 ctrl; =20 if (sport->lpuart_dma_tx_use) { if (!lpuart_stopped_or_empty(port)) lpuart_dma_tx(sport); } else { - temp =3D lpuart32_read(port, UARTCTRL); - lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); + ctrl =3D lpuart32_read(port, UARTCTRL); + lpuart32_write(port, ctrl | UARTCTRL_TIE, UARTCTRL); =20 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) lpuart32_transmit_buffer(sport); @@ -1411,9 +1411,9 @@ static inline int lpuart_start_rx_dma(struct lpuart_p= ort *sport) dma_async_issue_pending(chan); =20 if (lpuart_is_32(sport)) { - u32 temp =3D lpuart32_read(&sport->port, UARTBAUD); + u32 baud =3D lpuart32_read(&sport->port, UARTBAUD); =20 - lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); + lpuart32_write(&sport->port, baud | UARTBAUD_RDMAE, UARTBAUD); =20 if (sport->dma_idle_int) { u32 ctrl =3D lpuart32_read(&sport->port, UARTCTRL); @@ -1520,10 +1520,10 @@ static int lpuart32_config_rs485(struct uart_port *= port, struct ktermios *termio static unsigned int lpuart_get_mctrl(struct uart_port *port) { unsigned int mctrl =3D 0; - u8 reg; + u8 cr1; =20 - reg =3D readb(port->membase + UARTCR1); - if (reg & UARTCR1_LOOPS) + cr1 =3D readb(port->membase + UARTCR1); + if (cr1 & UARTCR1_LOOPS) mctrl |=3D TIOCM_LOOP; =20 return mctrl; @@ -1532,10 +1532,10 @@ static unsigned int lpuart_get_mctrl(struct uart_po= rt *port) static unsigned int lpuart32_get_mctrl(struct uart_port *port) { unsigned int mctrl =3D TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; - u32 reg; + u32 ctrl; =20 - reg =3D lpuart32_read(port, UARTCTRL); - if (reg & UARTCTRL_LOOPS) + ctrl =3D lpuart32_read(port, UARTCTRL); + if (ctrl & UARTCTRL_LOOPS) mctrl |=3D TIOCM_LOOP; =20 return mctrl; @@ -1543,49 +1543,49 @@ static unsigned int lpuart32_get_mctrl(struct uart_= port *port) =20 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) { - u8 reg; + u8 cr1; =20 - reg =3D readb(port->membase + UARTCR1); + cr1 =3D readb(port->membase + UARTCR1); =20 /* for internal loopback we need LOOPS=3D1 and RSRC=3D0 */ - reg &=3D ~(UARTCR1_LOOPS | UARTCR1_RSRC); + cr1 &=3D ~(UARTCR1_LOOPS | UARTCR1_RSRC); if (mctrl & TIOCM_LOOP) - reg |=3D UARTCR1_LOOPS; + cr1 |=3D UARTCR1_LOOPS; =20 - writeb(reg, port->membase + UARTCR1); + writeb(cr1, port->membase + UARTCR1); } =20 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) { - u32 reg; + u32 ctrl; =20 - reg =3D lpuart32_read(port, UARTCTRL); + ctrl =3D lpuart32_read(port, UARTCTRL); =20 /* for internal loopback we need LOOPS=3D1 and RSRC=3D0 */ - reg &=3D ~(UARTCTRL_LOOPS | UARTCTRL_RSRC); + ctrl &=3D ~(UARTCTRL_LOOPS | UARTCTRL_RSRC); if (mctrl & TIOCM_LOOP) - reg |=3D UARTCTRL_LOOPS; + ctrl |=3D UARTCTRL_LOOPS; =20 - lpuart32_write(port, reg, UARTCTRL); + lpuart32_write(port, ctrl, UARTCTRL); } =20 static void lpuart_break_ctl(struct uart_port *port, int break_state) { - u8 temp; + u8 cr2; =20 - temp =3D readb(port->membase + UARTCR2) & ~UARTCR2_SBK; + cr2 =3D readb(port->membase + UARTCR2) & ~UARTCR2_SBK; =20 if (break_state !=3D 0) - temp |=3D UARTCR2_SBK; + cr2 |=3D UARTCR2_SBK; =20 - writeb(temp, port->membase + UARTCR2); + writeb(cr2, port->membase + UARTCR2); } =20 static void lpuart32_break_ctl(struct uart_port *port, int break_state) { - u32 temp; + u32 ctrl; =20 - temp =3D lpuart32_read(port, UARTCTRL); + ctrl =3D lpuart32_read(port, UARTCTRL); =20 /* * LPUART IP now has two known bugs, one is CTS has higher priority than = the @@ -1602,22 +1602,22 @@ static void lpuart32_break_ctl(struct uart_port *po= rt, int break_state) * Disable the transmitter to prevent any data from being sent out * during break, then invert the TX line to send break. */ - temp &=3D ~UARTCTRL_TE; - lpuart32_write(port, temp, UARTCTRL); - temp |=3D UARTCTRL_TXINV; - lpuart32_write(port, temp, UARTCTRL); + ctrl &=3D ~UARTCTRL_TE; + lpuart32_write(port, ctrl, UARTCTRL); + ctrl |=3D UARTCTRL_TXINV; + lpuart32_write(port, ctrl, UARTCTRL); } else { /* Disable the TXINV to turn off break and re-enable transmitter. */ - temp &=3D ~UARTCTRL_TXINV; - lpuart32_write(port, temp, UARTCTRL); - temp |=3D UARTCTRL_TE; - lpuart32_write(port, temp, UARTCTRL); + ctrl &=3D ~UARTCTRL_TXINV; + lpuart32_write(port, ctrl, UARTCTRL); + ctrl |=3D UARTCTRL_TE; + lpuart32_write(port, ctrl, UARTCTRL); } } =20 static void lpuart_setup_watermark(struct lpuart_port *sport) { - u8 val, cr2, cr2_saved; + u8 fifo, cr2, cr2_saved; =20 cr2 =3D readb(sport->port.membase + UARTCR2); cr2_saved =3D cr2; @@ -1625,8 +1625,8 @@ static void lpuart_setup_watermark(struct lpuart_port= *sport) UARTCR2_RIE | UARTCR2_RE); writeb(cr2, sport->port.membase + UARTCR2); =20 - val =3D readb(sport->port.membase + UARTPFIFO); - writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, + fifo =3D readb(sport->port.membase + UARTPFIFO); + writeb(fifo | UARTPFIFO_TXFE | UARTPFIFO_RXFE, sport->port.membase + UARTPFIFO); =20 /* flush Tx and Rx FIFO */ @@ -1696,14 +1696,14 @@ static void lpuart32_setup_watermark(struct lpuart_= port *sport) =20 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) { - u32 temp; + u32 ctrl; =20 lpuart32_setup_watermark(sport); =20 - temp =3D lpuart32_read(&sport->port, UARTCTRL); - temp |=3D UARTCTRL_RE | UARTCTRL_TE; - temp |=3D FIELD_PREP(UARTCTRL_IDLECFG, 0x7); - lpuart32_write(&sport->port, temp, UARTCTRL); + ctrl =3D lpuart32_read(&sport->port, UARTCTRL); + ctrl |=3D UARTCTRL_RE | UARTCTRL_TE; + ctrl |=3D FIELD_PREP(UARTCTRL_IDLECFG, 0x7); + lpuart32_write(&sport->port, ctrl, UARTCTRL); } =20 static void rx_dma_timer_init(struct lpuart_port *sport) @@ -1820,16 +1820,16 @@ static void lpuart_hw_setup(struct lpuart_port *spo= rt) static int lpuart_startup(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); - u8 temp; + u8 fifo; =20 /* determine FIFO size and enable FIFO mode */ - temp =3D readb(port->membase + UARTPFIFO); + fifo =3D readb(port->membase + UARTPFIFO); =20 - sport->txfifo_size =3D UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & + sport->txfifo_size =3D UARTFIFO_DEPTH((fifo >> UARTPFIFO_TXSIZE_OFF) & UARTPFIFO_FIFOSIZE_MASK); port->fifosize =3D sport->txfifo_size; =20 - sport->rxfifo_size =3D UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & + sport->rxfifo_size =3D UARTFIFO_DEPTH((fifo >> UARTPFIFO_RXSIZE_OFF) & UARTPFIFO_FIFOSIZE_MASK); =20 lpuart_request_dma(sport); @@ -1840,24 +1840,24 @@ static int lpuart_startup(struct uart_port *port) =20 static void lpuart32_hw_disable(struct lpuart_port *sport) { - u32 temp; + u32 ctrl; =20 - temp =3D lpuart32_read(&sport->port, UARTCTRL); - temp &=3D ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE | + ctrl =3D lpuart32_read(&sport->port, UARTCTRL); + ctrl &=3D ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE | UARTCTRL_TIE | UARTCTRL_TE); - lpuart32_write(&sport->port, temp, UARTCTRL); + lpuart32_write(&sport->port, ctrl, UARTCTRL); } =20 static void lpuart32_configure(struct lpuart_port *sport) { - u32 temp; + u32 ctrl; =20 - temp =3D lpuart32_read(&sport->port, UARTCTRL); + ctrl =3D lpuart32_read(&sport->port, UARTCTRL); if (!sport->lpuart_dma_rx_use) - temp |=3D UARTCTRL_RIE | UARTCTRL_ILIE; + ctrl |=3D UARTCTRL_RIE | UARTCTRL_ILIE; if (!sport->lpuart_dma_tx_use) - temp |=3D UARTCTRL_TIE; - lpuart32_write(&sport->port, temp, UARTCTRL); + ctrl |=3D UARTCTRL_TIE; + lpuart32_write(&sport->port, ctrl, UARTCTRL); } =20 static void lpuart32_hw_setup(struct lpuart_port *sport) @@ -1880,16 +1880,16 @@ static void lpuart32_hw_setup(struct lpuart_port *s= port) static int lpuart32_startup(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); - u32 temp; + u32 fifo; =20 /* determine FIFO size */ - temp =3D lpuart32_read(port, UARTFIFO); + fifo =3D lpuart32_read(port, UARTFIFO); =20 - sport->txfifo_size =3D UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & + sport->txfifo_size =3D UARTFIFO_DEPTH((fifo >> UARTFIFO_TXSIZE_OFF) & UARTFIFO_FIFOSIZE_MASK); port->fifosize =3D sport->txfifo_size; =20 - sport->rxfifo_size =3D UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & + sport->rxfifo_size =3D UARTFIFO_DEPTH((fifo >> UARTFIFO_RXSIZE_OFF) & UARTFIFO_FIFOSIZE_MASK); =20 /* @@ -1934,16 +1934,16 @@ static void lpuart_dma_shutdown(struct lpuart_port = *sport) static void lpuart_shutdown(struct uart_port *port) { struct lpuart_port *sport =3D container_of(port, struct lpuart_port, port= ); - u8 temp; + u8 cr2; unsigned long flags; =20 uart_port_lock_irqsave(port, &flags); =20 /* disable Rx/Tx and interrupts */ - temp =3D readb(port->membase + UARTCR2); - temp &=3D ~(UARTCR2_TE | UARTCR2_RE | + cr2 =3D readb(port->membase + UARTCR2); + cr2 &=3D ~(UARTCR2_TE | UARTCR2_RE | UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); - writeb(temp, port->membase + UARTCR2); + writeb(cr2, port->membase + UARTCR2); =20 uart_port_unlock_irqrestore(port, flags); =20 @@ -2141,7 +2141,7 @@ static void __lpuart32_serial_setbrg(struct uart_port= *port, unsigned int baudrate, bool use_rx_dma, bool use_tx_dma) { - u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; + u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, baud; u32 clk =3D port->uartclk; =20 /* @@ -2170,9 +2170,9 @@ static void __lpuart32_serial_setbrg(struct uart_port= *port, tmp_diff =3D clk / (tmp_osr * tmp_sbr) - baudrate; =20 /* select best values between sbr and sbr+1 */ - tmp =3D clk / (tmp_osr * (tmp_sbr + 1)); - if (tmp_diff > (baudrate - tmp)) { - tmp_diff =3D baudrate - tmp; + baud =3D clk / (tmp_osr * (tmp_sbr + 1)); + if (tmp_diff > (baudrate - baud)) { + tmp_diff =3D baudrate - baud; tmp_sbr++; } =20 @@ -2194,23 +2194,23 @@ static void __lpuart32_serial_setbrg(struct uart_po= rt *port, dev_warn(port->dev, "unacceptable baud rate difference of more than 3%%\n"); =20 - tmp =3D lpuart32_read(port, UARTBAUD); + baud =3D lpuart32_read(port, UARTBAUD); =20 if ((osr > 3) && (osr < 8)) - tmp |=3D UARTBAUD_BOTHEDGE; + baud |=3D UARTBAUD_BOTHEDGE; =20 - tmp &=3D ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); - tmp |=3D ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; + baud &=3D ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); + baud |=3D ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; =20 - tmp &=3D ~UARTBAUD_SBR_MASK; - tmp |=3D sbr & UARTBAUD_SBR_MASK; + baud &=3D ~UARTBAUD_SBR_MASK; + baud |=3D sbr & UARTBAUD_SBR_MASK; =20 if (!use_rx_dma) - tmp &=3D ~UARTBAUD_RDMAE; + baud &=3D ~UARTBAUD_RDMAE; if (!use_tx_dma) - tmp &=3D ~UARTBAUD_TDMAE; + baud &=3D ~UARTBAUD_TDMAE; =20 - lpuart32_write(port, tmp, UARTBAUD); + lpuart32_write(port, baud, UARTBAUD); } =20 static void lpuart32_serial_setbrg(struct lpuart_port *sport, @@ -3085,7 +3085,7 @@ static int lpuart_suspend_noirq(struct device *dev) static int lpuart_resume_noirq(struct device *dev) { struct lpuart_port *sport =3D dev_get_drvdata(dev); - u32 val; + u32 stat; =20 pinctrl_pm_select_default_state(dev); =20 @@ -3094,8 +3094,8 @@ static int lpuart_resume_noirq(struct device *dev) =20 /* clear the wakeup flags */ if (lpuart_is_32(sport)) { - val =3D lpuart32_read(&sport->port, UARTSTAT); - lpuart32_write(&sport->port, val, UARTSTAT); + stat =3D lpuart32_read(&sport->port, UARTSTAT); + lpuart32_write(&sport->port, stat, UARTSTAT); } } =20 --=20 2.34.1